From a044626c3901e3f7d5074fa32b433a1cf6e132cf Mon Sep 17 00:00:00 2001 From: Ryan Kurtz Date: Mon, 23 Mar 2026 06:25:24 -0400 Subject: [PATCH 1/2] GP-6605: Adding more versions of pywin32 --- .../Debugger-agent-dbgeng/Module.manifest | 5 ++++ .../Debug/Debugger-agent-dbgeng/build.gradle | 5 ++++ gradle/support/fetchDependencies.gradle | 30 +++++++++++++++++++ 3 files changed, 40 insertions(+) diff --git a/Ghidra/Debug/Debugger-agent-dbgeng/Module.manifest b/Ghidra/Debug/Debugger-agent-dbgeng/Module.manifest index d7efbaa85e..8b48f96fca 100644 --- a/Ghidra/Debug/Debugger-agent-dbgeng/Module.manifest +++ b/Ghidra/Debug/Debugger-agent-dbgeng/Module.manifest @@ -1,7 +1,12 @@ MODULE FILE LICENSE: pypkg/dist/capstone-5.0.6-py3-none-win_amd64.whl BSD-3-CAPSTONE MODULE FILE LICENSE: pypkg/dist/comtypes-1.4.13-py3-none-any.whl MIT MODULE FILE LICENSE: pypkg/dist/pybag-2.2.16-py3-none-any.whl MIT +MODULE FILE LICENSE: pypkg/dist/pywin32-311-cp39-cp39-win_amd64.whl Python Software Foundation License +MODULE FILE LICENSE: pypkg/dist/pywin32-311-cp310-cp310-win_amd64.whl Python Software Foundation License +MODULE FILE LICENSE: pypkg/dist/pywin32-311-cp311-cp311-win_amd64.whl Python Software Foundation License +MODULE FILE LICENSE: pypkg/dist/pywin32-311-cp312-cp312-win_amd64.whl Python Software Foundation License MODULE FILE LICENSE: pypkg/dist/pywin32-311-cp313-cp313-win_amd64.whl Python Software Foundation License +MODULE FILE LICENSE: pypkg/dist/pywin32-311-cp314-cp314-win_amd64.whl Python Software Foundation License MODULE FILE LICENSE: pypkg/dist/win32more-0.7.0-py3-none-any.whl MIT MODULE FILE LICENSE: pypkg/dist/win32more_appsdk-0.7.3-py2.py3-none-any.whl MIT MODULE FILE LICENSE: pypkg/dist/win32more_core-0.7.0-py2.py3-none-any.whl MIT diff --git a/Ghidra/Debug/Debugger-agent-dbgeng/build.gradle b/Ghidra/Debug/Debugger-agent-dbgeng/build.gradle index 0bb21286bc..e805db4e6e 100644 --- a/Ghidra/Debug/Debugger-agent-dbgeng/build.gradle +++ b/Ghidra/Debug/Debugger-agent-dbgeng/build.gradle @@ -84,7 +84,12 @@ task prebuildTlb(type: Copy) { distributePyDep("pybag-2.2.16-py3-none-any.whl") distributePyDep("capstone-5.0.6-py3-none-win_amd64.whl") distributePyDep("comtypes-1.4.13-py3-none-any.whl") +distributePyDep("pywin32-311-cp39-cp39-win_amd64.whl") +distributePyDep("pywin32-311-cp310-cp310-win_amd64.whl") +distributePyDep("pywin32-311-cp311-cp311-win_amd64.whl") +distributePyDep("pywin32-311-cp312-cp312-win_amd64.whl") distributePyDep("pywin32-311-cp313-cp313-win_amd64.whl") +distributePyDep("pywin32-311-cp314-cp314-win_amd64.whl") distributePyDep("win32more-0.7.0-py3-none-any.whl") distributePyDep("win32more_appsdk-0.7.3-py2.py3-none-any.whl") distributePyDep("win32more_core-0.7.0-py2.py3-none-any.whl") diff --git a/gradle/support/fetchDependencies.gradle b/gradle/support/fetchDependencies.gradle index 5a0534df3f..322b2c9b15 100644 --- a/gradle/support/fetchDependencies.gradle +++ b/gradle/support/fetchDependencies.gradle @@ -253,12 +253,42 @@ ext.deps = [ sha256: "21546210748ba52e839e52112124b16ffab7d7fb68096493165fbc249e9023ad", destination: file("${DEPS_DIR}/Debugger-agent-dbgeng/") ], + [ + name: "pywin32-311-cp314-cp314-win_amd64.whl", + url: "https://files.pythonhosted.org/packages/90/4b/07c77d8ba0e01349358082713400435347df8426208171ce297da32c313d/pywin32-311-cp314-cp314-win_amd64.whl", + sha256: "3aca44c046bd2ed8c90de9cb8427f581c479e594e99b5c0bb19b29c10fd6cb87", + destination: file("${DEPS_DIR}/Debugger-agent-dbgeng/") + ], [ name: "pywin32-311-cp313-cp313-win_amd64.whl", url: "https://files.pythonhosted.org/packages/e3/28/e0a1909523c6890208295a29e05c2adb2126364e289826c0a8bc7297bd5c/pywin32-311-cp313-cp313-win_amd64.whl", sha256: "718a38f7e5b058e76aee1c56ddd06908116d35147e133427e59a3983f703a20d", destination: file("${DEPS_DIR}/Debugger-agent-dbgeng/") ], + [ + name: "pywin32-311-cp312-cp312-win_amd64.whl", + url: "https://files.pythonhosted.org/packages/d1/a8/a0e8d07d4d051ec7502cd58b291ec98dcc0c3fff027caad0470b72cfcc2f/pywin32-311-cp312-cp312-win_amd64.whl", + sha256: "b8c095edad5c211ff31c05223658e71bf7116daa0ecf3ad85f3201ea3190d067", + destination: file("${DEPS_DIR}/Debugger-agent-dbgeng/") + ], + [ + name: "pywin32-311-cp311-cp311-win_amd64.whl", + url: "https://files.pythonhosted.org/packages/51/8f/9bb81dd5bb77d22243d33c8397f09377056d5c687aa6d4042bea7fbf8364/pywin32-311-cp311-cp311-win_amd64.whl", + sha256: "3ce80b34b22b17ccbd937a6e78e7225d80c52f5ab9940fe0506a1a16f3dab503", + destination: file("${DEPS_DIR}/Debugger-agent-dbgeng/") + ], + [ + name: "pywin32-311-cp310-cp310-win_amd64.whl", + url: "https://files.pythonhosted.org/packages/5e/bf/360243b1e953bd254a82f12653974be395ba880e7ec23e3731d9f73921cc/pywin32-311-cp310-cp310-win_amd64.whl", + sha256: "797c2772017851984b97180b0bebe4b620bb86328e8a884bb626156295a63b3b", + destination: file("${DEPS_DIR}/Debugger-agent-dbgeng/") + ], + [ + name: "pywin32-311-cp39-cp39-win_amd64.whl", + url: "https://files.pythonhosted.org/packages/9f/8a/1403d0353f8c5a2f0829d2b1c4becbf9da2f0a4d040886404fc4a5431e4d/pywin32-311-cp39-cp39-win_amd64.whl", + sha256: "e0c4cfb0621281fe40387df582097fd796e80430597cb9944f0ae70447bacd91", + destination: file("${DEPS_DIR}/Debugger-agent-dbgeng/") + ], [ name: "win32more-0.7.0-py3-none-any.whl", url: "https://files.pythonhosted.org/packages/92/3a/658eb3ba88f067662be280f8f1aec07a70c96bac77e9edc48b1be38e446b/win32more-0.7.0-py3-none-any.whl", From 5636392395b9975c3dde72eb3246ba28a55cbcc0 Mon Sep 17 00:00:00 2001 From: ghidra1 Date: Mon, 23 Mar 2026 15:30:23 -0400 Subject: [PATCH 2/2] GP-6621 Add Hexagon processor --- Ghidra/Processors/Hexagon/Module.manifest | 0 Ghidra/Processors/Hexagon/build.gradle | 35 + .../Processors/Hexagon/certification.manifest | 16 + .../Hexagon/data/languages/Hexagon.opinion | 5 + .../Hexagon/data/languages/hexagon.cspec | 154 + .../Hexagon/data/languages/hexagon.dwarf | 19 + .../Hexagon/data/languages/hexagon.ldefs | 17 + .../Hexagon/data/languages/hexagon.pspec | 439 + .../Hexagon/data/languages/hexagon.sinc | 17384 ++++++++++++++++ .../Hexagon/data/languages/hexagon.slaspec | 888 + .../Hexagon/data/languages/hexagon_float.sinc | 872 + .../Hexagon/data/languages/hexagon_hvx.sinc | 6537 ++++++ .../Hexagon/data/languages/hexagon_hvx.txt | 618 + .../Hexagon/data/languages/hexagon_left.sinc | 648 + .../Hexagon/data/languages/hexagon_right.sinc | 776 + .../data/patterns/Hexagon_patterns.xml | 72 + .../data/patterns/patternconstraints.xml | 5 + .../VerifyHexagonTestVectors.java | 1201 ++ .../plugin/core/analysis/HexagonAnalyzer.java | 226 + .../analysis/HexagonPrologEpilogAnalyzer.java | 288 + .../core/analysis/HexagonThunkAnalyzer.java | 292 + .../HexagonUnsupportSemanticAnalyzer.java | 190 + .../bin/format/elf/Hexagon_ElfConstants.java | 71 + .../elf/extend/Hexagon_ElfExtension.java | 74 + .../Hexagon_ElfProgramHeaderConstants.java | 34 + .../Hexagon_ElfRelocationHandler.java | 219 + .../relocation/Hexagon_ElfRelocationType.java | 151 + .../HexagonParallelInstructionHelper.java | 63 + ...exagonEmulateInstructionStateModifier.java | 697 + .../ghidra/program/emulation/HexagonFp32.java | 56 + .../ghidra/program/emulation/HexagonFp64.java | 229 + .../HexagonPcodeUseropLibraryFactory.java | 210 + .../processors/HexagonPcodeEmulatorTest.java | 115 + .../processors/Hexagon_O0_EmulatorTest.java | 74 + .../processors/Hexagon_O3_EmulatorTest.java | 62 + .../assembler/sleigh/HexagonAssemblyTest.java | 70 + .../HexagonPcodeUseropLibraryTest.java | 237 + .../pcode/PcodeEmitContextCrossBuildTest.java | 906 + 38 files changed, 33950 insertions(+) create mode 100755 Ghidra/Processors/Hexagon/Module.manifest create mode 100755 Ghidra/Processors/Hexagon/build.gradle create mode 100755 Ghidra/Processors/Hexagon/certification.manifest create mode 100755 Ghidra/Processors/Hexagon/data/languages/Hexagon.opinion create mode 100755 Ghidra/Processors/Hexagon/data/languages/hexagon.cspec create mode 100644 Ghidra/Processors/Hexagon/data/languages/hexagon.dwarf create mode 100755 Ghidra/Processors/Hexagon/data/languages/hexagon.ldefs create mode 100755 Ghidra/Processors/Hexagon/data/languages/hexagon.pspec create mode 100755 Ghidra/Processors/Hexagon/data/languages/hexagon.sinc create mode 100755 Ghidra/Processors/Hexagon/data/languages/hexagon.slaspec create mode 100644 Ghidra/Processors/Hexagon/data/languages/hexagon_float.sinc create mode 100644 Ghidra/Processors/Hexagon/data/languages/hexagon_hvx.sinc create mode 100644 Ghidra/Processors/Hexagon/data/languages/hexagon_hvx.txt create mode 100644 Ghidra/Processors/Hexagon/data/languages/hexagon_left.sinc create mode 100644 Ghidra/Processors/Hexagon/data/languages/hexagon_right.sinc create mode 100755 Ghidra/Processors/Hexagon/data/patterns/Hexagon_patterns.xml create mode 100755 Ghidra/Processors/Hexagon/data/patterns/patternconstraints.xml create mode 100755 Ghidra/Processors/Hexagon/developer_scripts/VerifyHexagonTestVectors.java create mode 100755 Ghidra/Processors/Hexagon/src/main/java/ghidra/app/plugin/core/analysis/HexagonAnalyzer.java create mode 100755 Ghidra/Processors/Hexagon/src/main/java/ghidra/app/plugin/core/analysis/HexagonPrologEpilogAnalyzer.java create mode 100755 Ghidra/Processors/Hexagon/src/main/java/ghidra/app/plugin/core/analysis/HexagonThunkAnalyzer.java create mode 100755 Ghidra/Processors/Hexagon/src/main/java/ghidra/app/plugin/core/analysis/HexagonUnsupportSemanticAnalyzer.java create mode 100644 Ghidra/Processors/Hexagon/src/main/java/ghidra/app/util/bin/format/elf/Hexagon_ElfConstants.java create mode 100644 Ghidra/Processors/Hexagon/src/main/java/ghidra/app/util/bin/format/elf/extend/Hexagon_ElfExtension.java create mode 100644 Ghidra/Processors/Hexagon/src/main/java/ghidra/app/util/bin/format/elf/extend/Hexagon_ElfProgramHeaderConstants.java create mode 100644 Ghidra/Processors/Hexagon/src/main/java/ghidra/app/util/bin/format/elf/relocation/Hexagon_ElfRelocationHandler.java create mode 100644 Ghidra/Processors/Hexagon/src/main/java/ghidra/app/util/bin/format/elf/relocation/Hexagon_ElfRelocationType.java create mode 100755 Ghidra/Processors/Hexagon/src/main/java/ghidra/app/util/viewer/field/HexagonParallelInstructionHelper.java create mode 100755 Ghidra/Processors/Hexagon/src/main/java/ghidra/program/emulation/HexagonEmulateInstructionStateModifier.java create mode 100644 Ghidra/Processors/Hexagon/src/main/java/ghidra/program/emulation/HexagonFp32.java create mode 100644 Ghidra/Processors/Hexagon/src/main/java/ghidra/program/emulation/HexagonFp64.java create mode 100644 Ghidra/Processors/Hexagon/src/main/java/ghidra/program/emulation/HexagonPcodeUseropLibraryFactory.java create mode 100644 Ghidra/Processors/Hexagon/src/test.processors/java/ghidra/test/processors/HexagonPcodeEmulatorTest.java create mode 100644 Ghidra/Processors/Hexagon/src/test.processors/java/ghidra/test/processors/Hexagon_O0_EmulatorTest.java create mode 100644 Ghidra/Processors/Hexagon/src/test.processors/java/ghidra/test/processors/Hexagon_O3_EmulatorTest.java create mode 100644 Ghidra/Processors/Hexagon/src/test/java/ghidra/app/plugin/assembler/sleigh/HexagonAssemblyTest.java create mode 100644 Ghidra/Processors/Hexagon/src/test/java/ghidra/program/emulation/HexagonPcodeUseropLibraryTest.java create mode 100644 Ghidra/Test/IntegrationTest/src/test.slow/java/ghidra/program/model/pcode/PcodeEmitContextCrossBuildTest.java diff --git a/Ghidra/Processors/Hexagon/Module.manifest b/Ghidra/Processors/Hexagon/Module.manifest new file mode 100755 index 0000000000..e69de29bb2 diff --git a/Ghidra/Processors/Hexagon/build.gradle b/Ghidra/Processors/Hexagon/build.gradle new file mode 100755 index 0000000000..8696fe91ea --- /dev/null +++ b/Ghidra/Processors/Hexagon/build.gradle @@ -0,0 +1,35 @@ +/* ### + * IP: GHIDRA + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +apply from: "$rootProject.projectDir/gradle/distributableGhidraModule.gradle" +apply from: "$rootProject.projectDir/gradle/javaProject.gradle" +apply from: "$rootProject.projectDir/gradle/jacocoProject.gradle" +apply from: "$rootProject.projectDir/gradle/javaTestProject.gradle" +apply from: "$rootProject.projectDir/gradle/processorProject.gradle" +apply plugin: 'eclipse' +eclipse.project.name = 'Processors Hexagon' + +dependencies { + api project(":BytePatterns") + api project(":Emulation") + + testImplementation project(path: ':SoftwareModeling', configuration: 'testArtifacts') + testImplementation project(path: ':Emulation', configuration: 'testArtifacts') +} + +sleighCompileOptions = [ + "-l", + "-t" +] diff --git a/Ghidra/Processors/Hexagon/certification.manifest b/Ghidra/Processors/Hexagon/certification.manifest new file mode 100755 index 0000000000..db3305d019 --- /dev/null +++ b/Ghidra/Processors/Hexagon/certification.manifest @@ -0,0 +1,16 @@ +##VERSION: 2.0 +Module.manifest||GHIDRA||||END| +data/languages/Hexagon.opinion||GHIDRA||||END| +data/languages/hexagon.cspec||GHIDRA||||END| +data/languages/hexagon.dwarf||GHIDRA||||END| +data/languages/hexagon.ldefs||GHIDRA||||END| +data/languages/hexagon.pspec||GHIDRA||||END| +data/languages/hexagon.sinc||GHIDRA||||END| +data/languages/hexagon.slaspec||GHIDRA||||END| +data/languages/hexagon_float.sinc||GHIDRA||||END| +data/languages/hexagon_hvx.sinc||GHIDRA||||END| +data/languages/hexagon_hvx.txt||GHIDRA|exclude|||END| +data/languages/hexagon_left.sinc||GHIDRA||||END| +data/languages/hexagon_right.sinc||GHIDRA||||END| +data/patterns/Hexagon_patterns.xml||GHIDRA||||END| +data/patterns/patternconstraints.xml||GHIDRA||||END| diff --git a/Ghidra/Processors/Hexagon/data/languages/Hexagon.opinion b/Ghidra/Processors/Hexagon/data/languages/Hexagon.opinion new file mode 100755 index 0000000000..ba3f687b46 --- /dev/null +++ b/Ghidra/Processors/Hexagon/data/languages/Hexagon.opinion @@ -0,0 +1,5 @@ + + + + + diff --git a/Ghidra/Processors/Hexagon/data/languages/hexagon.cspec b/Ghidra/Processors/Hexagon/data/languages/hexagon.cspec new file mode 100755 index 0000000000..91e10ecfef --- /dev/null +++ b/Ghidra/Processors/Hexagon/data/languages/hexagon.cspec @@ -0,0 +1,154 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/Ghidra/Processors/Hexagon/data/languages/hexagon.dwarf b/Ghidra/Processors/Hexagon/data/languages/hexagon.dwarf new file mode 100644 index 0000000000..7420ce370c --- /dev/null +++ b/Ghidra/Processors/Hexagon/data/languages/hexagon.dwarf @@ -0,0 +1,19 @@ + + + + + + + + + + + + + + + + + + + diff --git a/Ghidra/Processors/Hexagon/data/languages/hexagon.ldefs b/Ghidra/Processors/Hexagon/data/languages/hexagon.ldefs new file mode 100755 index 0000000000..0c21cea52a --- /dev/null +++ b/Ghidra/Processors/Hexagon/data/languages/hexagon.ldefs @@ -0,0 +1,17 @@ + + + + + Qualcomm Hexagon V69 processor (QDSP6) 32-bit little-endian + + + + + diff --git a/Ghidra/Processors/Hexagon/data/languages/hexagon.pspec b/Ghidra/Processors/Hexagon/data/languages/hexagon.pspec new file mode 100755 index 0000000000..a2ad8e872e --- /dev/null +++ b/Ghidra/Processors/Hexagon/data/languages/hexagon.pspec @@ -0,0 +1,439 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/Ghidra/Processors/Hexagon/data/languages/hexagon.sinc b/Ghidra/Processors/Hexagon/data/languages/hexagon.sinc new file mode 100755 index 0000000000..de29be04da --- /dev/null +++ b/Ghidra/Processors/Hexagon/data/languages/hexagon.sinc @@ -0,0 +1,17384 @@ +# Qualcomm Hexagon (V73) General Instruction Set + +# +# Custom pcode-op +# +define pcodeop lock; +define pcodeop unlock; +define pcodeop lock_valid; +define pcodeop bitReverse; +define pcodeop circularAdd; +define pcodeop countTrailingZeros; +define pcodeop countTrailingOnes; +define pcodeop countLeadingBits; +define pcodeop saturate8; +define pcodeop saturate16; +define pcodeop saturate32; +define pcodeop usaturate8; +define pcodeop usaturate16; +define pcodeop usaturate32; + +# roundArithmetic(v,n) (n==0) ? (v) : round( v + 2**(n-1) )) >> n +# Arithmentic rounding of v to any bit location n (only least significant 5-bits of n are used) +# round: .5 is rounded up +define pcodeop roundArithmetic; +define pcodeop roundArithmeticSaturate; + +# roundConvergent(v,n) (n==0) ? v : convround(v + 2**(n-1)) >> n +# Convergent rounding of v to any bit location n (only least significant 5-bits of n are used) +# convround: .5 is rounded towards even +define pcodeop roundConvergent; +define pcodeop roundConvergentSaturate; + +define pcodeop reciprocal; +define pcodeop reciprocalAdjust; +define pcodeop multiplyAddScale; + +# +# Macros +# + +macro addSat16(dest, src1, src2) { + result:4 = sext(src1) + sext(src2); + dest = saturate16(result); +} + +macro adduSat16(dest, src1, src2) { + result:4 = zext(src1) + zext(src2); + dest = usaturate16(result); +} + +macro subSat16(dest, src1, src2) { + result:4 = sext(src1) - sext(src2); + dest = saturate16(result); +} + +macro subuSat16(dest, src1, src2) { + result:4 = zext(src1) - zext(src2); + dest = usaturate16(result); +} + +macro addSat32(dest, src1, src2) { + result:8 = sext(src1) + sext(src2); + dest = saturate32(result); +} + +macro adduSat32(dest, src1, src2) { + result:8 = zext(src1) + zext(src2); + dest = usaturate32(result); +} + +macro subSat32(dest, src1, src2) { + result:8 = sext(src1) - sext(src2); + dest = saturate32(result); +} + +macro subuSat32(dest, src1, src2) { + result:8 = zext(src1) - zext(src2); + dest = usaturate32(result); +} + +# +# Sub-constructors +# + +Zero: "#"^val is epsilon [ val = 0; ] { export *[const]:1 val; } +MinusOne: "#"^val is epsilon [ val = -1; ] { export *[const]:1 val; } +One: "#"^val is epsilon [ val = 1; ] { export *[const]:1 val; } +FF: "#"^val is epsilon [ val = 0xff; ] { export *[const]:1 val; } + +PCval: val is epsilon [ val = inst_start - (4 * packetOffset); ] { export *[const]:4 val; } +PacketPC: PC is PC & PCval { export PCval; } + +# Source control register (handle PC special) +Cs5: cs5 is cs5 { export cs5; } # Source use only +Cs5: PacketPC is cs5=9 & PacketPC { export PacketPC; } + +# Destination control register (PC assignment not currently handled) +Cd5: cd5 is cd5 & cd5_ { + export cd5_; + <> + cd5 = cd5_; +} +Cdd5: cdd5 is cdd5 & cdd5_ { + export cdd5_; + <> + cdd5 = cdd5_; +} + +# Destination guest register (shadow not currently supported) +Gd5: gd5 is gd5 { export gd5; } +Gdd5: gdd5 is gdd5 { export gdd5; } + +# Destination supervisor register (shadow not currently supported) +Sd6: sd6 is sd6 { export sd6; } +Sdd6: sdd6 is sdd6 { export sdd6; } + +# Destination register (displays reg but exports shadow-reg) +# NOTE: Unconditional auto-commit use only +Rdd5: rdd5 is rdd5 & rdd5_ { # facilitates Nreg use in packet + export rdd5_; + <> + rdd5 = rdd5_; +} +Rd5: rd5 is rd5 & rd5_ & SetNRegRd5 & cond=0 { # facilitates Nreg use in packet + export rd5_; + <> + rd5 = rd5_; +} +Rxx5: rxx5 is rxx5 & rxx5_ { # facilitates Nreg use in packet + export rxx5_; + <> + rxx5 = rxx5_; +} +Rx5: rx5 is rx5 & rx5_ & SetNRegRx5 { # facilitates Nreg use in packet + export rx5_; + <> + rx5 = rx5_; +} +Rd0812: rd0812 is rd0812 & rd0812_ & SetNRegRd0812 { # facilitates Nreg use in packet + export rd0812_; + <> + rd0812 = rd0812_; +} +Rdd0812: rdd0812 is rdd0812 & rdd0812_ & SetNRegRd0812 { # facilitates Nreg use in packet + export rdd0812_; + <> + rdd0812 = rdd0812_; +} +Rx5H: rx5H is rx5H & rx5H_ { # TODO: Do we need to set nreg ? + export rx5H_; + <> + rx5H = rx5H_; +} +Rx5L: rx5L is rx5L & rx5L_ { # TODO: Do we need to set nreg ? + export rx5L_; + <> + rx5L = rx5L_; +} +Rd0811: rd0811 is rd0811 & rd0811_ { # TODO: Do we need to set nreg ? + export rd0811_; + <> + rd0811 = rd0811_; +} +Rd1619: rd1619 is rd1619 & rd1619_ { # TODO: Do we need to set nreg ? + export rd1619_; + <> + rd1619 = rd1619_; +} + +Rdd3l: rdd3l is rdd3l & rdd3l_ { + export rdd3l_; + <> + rdd3l = rdd3l_; +} +Rdd3r: rdd3r is rdd3r & rdd3r_ { + export rdd3r_; + <> + rdd3r = rdd3r_; +} +Rd4l: rd4l is rd4l & rd4l_ { + export rd4l_; + <> + rd4l = rd4l_; +} +Rd4r: rd4r is rd4r & rd4r_ { + export rd4r_; + <> + rd4r = rd4r_; +} + +# Source registers + +Ru5HL21: ru5L is op21=0 & ru5L { export ru5L; } +Ru5HL21: ru5H is op21=1 & ru5H { export ru5H; } + +Rt5HL21: rt5L is op21=0 & rt5L { export rt5L; } +Rt5HL21: rt5H is op21=1 & rt5H { export rt5H; } + +Rt5HL06: rt5L is op6=0 & rt5L { export rt5L; } +Rt5HL06: rt5H is op6=1 & rt5H { export rt5H; } + +Rt5HL05: rt5L is op5=0 & rt5L { export rt5L; } +Rt5HL05: rt5H is op5=1 & rt5H { export rt5H; } + +Rs5HL06: rs5L is op6=0 & rs5L { export rs5L; } +Rs5HL06: rs5H is op6=1 & rs5H { export rs5H; } + +Rs5HL05: rs5L is op5=0 & rs5L { export rs5L; } +Rs5HL05: rs5H is op5=1 & rs5H { export rs5H; } + +OnesCompRs5: "~"^rs5 is rs5 { tmp:4 = ~rs5; export tmp; } +OnesCompRss5: "~"^rss5 is rss5 { tmp:8 = ~rss5; export tmp; } + +OnesCompRt5: "~"^rt5 is rt5 { tmp:4 = ~rt5; export tmp; } + +define pcodeop conjugate; +Rt5Conjugate: rt5^"*" is rt5 { tmp:4 = conjugate(rt5); export tmp; } +Rtt5Conjugate: rtt5^"*" is rtt5 { tmp:8 = conjugate(rtt5); export tmp; } + +# +# P0 - P3 register modes +# +# NOTE: A predicate destination register must be auto-AND'd with it previous .new state +# which is initially set to 0xff to allow for this. +# + +# Destination +# NOTE: Unconditional commit use only +Pd2: pu0001 is pu0001 & pu0001_ { + export pu0001_; + <> + pu0001 = pu0001_; +} +Pd25: pu25 is pu25 & pu25_ { + export pu25_; + <> + pu25 = pu25_; +} +Pd12: pu12 is pu12 & pu12_ { + export pu12_; + <> + pu12 = pu12_; +} +P0dest: P0 is P0 { + export P0.new; + <> + P0 = P0.new; +} + +Pd0506: pu0506 is pu0506 & pu0506_ { + export pu0506_; + <> + pu0506 = pu0506_; +} + +NotPs2: "!"^pu1617 is pu1617 { tmp:1 = !pu1617; export tmp; } + +# Relative Destination Address (relative to start of packet) +# NOTE: All relative addresses support immext (relative offset is not shifted when immext is present and first two bits always cleared) +# NOTE: Use of immext only appends 6 low-order bits to immext, although resulting bit-0 and bit-1 are cleared/ignored by hardware. +@define PKT_START "inst_start - (4 * packetOffset)" + +RelDest22x: val is s1624 & i0113 & immexted=0 [ val = (((s1624 << 13) | i0113) << 2) + $(PKT_START); ] { export *[ram]:4 val; } +RelDest22x: val is i0306 & immexted=1 [ val = ((simmext << 6) | (i0306 << 2)) + $(PKT_START); ] { export *[ram]:4 val; } + +@define r15_2_val "((s2223 << 13) | (i1620 << 8) | (i13 << 7) | i0107)" +RelDest15x: val is i0107 & i13 & i1620 & s2223 & immexted=0 [ val = ($(r15_2_val) << 2) + $(PKT_START); ] { export *[ram]:4 val; } +RelDest15x: val is i0306 & immexted=1 [ val = ((simmext << 6) | (i0306 << 2)) + $(PKT_START); ] { export *[ram]:4 val; } + +@define r13_2_val "((s21 << 12) | (op13 << 11) | i0111)" +RelDest13: val is i0111 & op13 & s21 [ val = ($(r13_2_val) << 2) + $(PKT_START); ] { export *[ram]:4 val; } + +RelDest9x: val is i0107 & s2021 & immexted=0 [ val = (((s2021 << 7) | i0107) << 2) + $(PKT_START); ] { export *[ram]:4 val; } +RelDest9x: val is i0306 & immexted=1 [ val = ((simmext << 6) | (i0306 << 2)) + $(PKT_START); ] { export *[ram]:4 val; } + +# +# Non-extended Immediates +# + +Simm8_0813: "#"^s0813 is s0813 { export *[const]:1 s0813; } +Simm8_0512: "#"^s0512 is s0512 { export *[const]:1 s0512; } +Simm8_0410: "#"^s0410 is s0410 { export *[const]:1 s0410; } +Simm8_1620_05: "#"^val is s1620 & i5 [ val = (s1620 << 1) | i5; ] { export *[const]:1 val; } +Simm8_1622_13: "#"^val is s1622 & i13 [ val = (s1622 << 1) | i13; ] { export *[const]:1 val; } + +Uimm16_21_0513: "#"^val is op21 & i0513 [ val = (op21 << 9) | i0513; ] { export *[const]:2 val; } +Uimm16_2223_0013: "#"^val is i2223 & i0013 [ val = (i2223 << 14) | i0013; ] { export *[const]:2 val; } + +Uimm10_1617_0812_0204: "#"^val is i1617 & i0812 & i0204 [ val = (i1617 << 8) | (i0812 << 3) | i0204; ] { export *[const]:2 val; } + + +Uimm8_2123_0507: "#"^val is i2123 & i0507 [ val = (i2123 << 3) | i0507; ] { export *[const]:1 val; } +Uimm8_2122_0507: "#"^val is i2122 & i0507 [ val = (i2122 << 3) | i0507; ] { export *[const]:1 val; } + +Uimm8_23_0004: "#"^val is op23 & i0004 [ val = (op23 << 5) | i0004; ] { export *[const]:1 val; } +Uimm8_21_0507: "#"^val is op21 & i0507 [ val = (op21 << 3) | i0507; ] { export *[const]:1 val; } +Uimm8_0812_0204: "#"^val is i0812 & i0204 [ val = (i0812 << 3) | i0204; ] { export *[const]:1 val; } +Uimm8_0813: "#"^i0813 is i0813 { export *[const]:1 i0813; } +Uimm8_0812: "#"^i0812 is i0812 { export *[const]:1 i0812; } +Uimm8_0811: "#"^i0811 is i0811 { export *[const]:1 i0811; } +Uimm8_0512: "#"^i0512 is i0512 { export *[const]:1 i0512; } +Uimm8_0511: "#"^i0511 is i0511 { export *[const]:1 i0511; } +Uimm8_0509: "#"^i0509 is i0509 { export *[const]:1 i0509; } +Uimm8_0507: "#"^i0507 is i0507 { export *[const]:1 i0507; } +Uimm8_0409: "#"^i0409 is i0409 { export *[const]:1 i0409; } +Uimm8_0004: "#"^i0004 is i0004 { export *[const]:1 i0004; } +Uimm8_0001: "#"^i0001 is i0001 { export *[const]:1 i0001; } + +Uimm3_0507: "#"^i0507 is i0507 { export *[const]:1 i0507; } + +Uimm2_13_07: "#"^val is op13 & op7 [ val = (op13 << 1) | op7; ] { export *[const]:1 val; } +Uimm2_13_06: "#"^val is op13 & op6 [ val = (op13 << 1) | op6; ] { export *[const]:1 val; } +Uimm2_13_05: "#"^val is op13 & op5 [ val = (op13 << 1) | op5; ] { export *[const]:1 val; } +Uimm2_1617: "#"^op1617 is op1617 { export *[const]:1 op1617; } +Uimm2_2122: "#"^op2122 is op2122 { export *[const]:1 op2122; } +Uimm2_1920: "#"^op1920 is op1920 { export *[const]:1 op1920; } +Uimm2_0304: "#"^i0304 is i0304 { export *[const]:1 i0304; } +Uimm2_0506: "#"^i0506 is i0506 { export *[const]:1 i0506; } + +Uimm1_24: "#"^i24 is i24 { export *[const]:1 i24; } +Uimm1_08: "#"^i8 is i8 { export *[const]:1 i8; } +Uimm1_05: "#"^i5 is i5 { export *[const]:1 i5; } + +# +# Non-extended Immediates with shift factor +# +Uimm8_0408_shift3: "#"^val is i0408 [ val = i0408 << 3; ] { export *[const]:1 val; } +Uimm8_0409_shift2: "#"^val is i0409 [ val = i0409 << 2; ] { export *[const]:1 val; } +Uimm16_0010_shift3: "#"^val is i0010 [ val = i0010 << 3; ] { export *[const]:2 val; } +Uimm8_2025_shift2: "#"^val is i2025 [ val = i2025 << 2; ] { export *[const]:1 val; } +Uimm32_2122_13_0507_shift2: "#"^val is i2122 & i13 & i0507 [ val = ((i2122 << 4) | (i13 << 3) | i0507) << 2; ] { export *[const]:4 val; } + + +# +# Extended Immediates (see immext) +# Double-# indicates use of extended immediate value + +Simm32_13_0006x: "#"^val is s13 & i0006 & immexted=0 [ val = (s13 << 7) | i0006; ] { export *[const]:4 val; } +Simm32_13_0006x: "##"^val is s13 & i0005 & immexted=1 [ val = (immext << 6) | i0005; ] { export *[const]:4 val; } # u32 + +Simm32_13_0004x: "#"^val is s13 & i0004 & immexted=0 [ val = (s13 << 5) | i0004; ] { export *[const]:4 val; } +Simm32_13_0004x: "##"^val is op13 & i0004 & immexted=1 [ val = (immext << 6) | (op13 << 5) | i0004; ] { export *[const]:4 val; } # u32 + +Simm32_0512x: "#"^s0512 is s0512 & immexted=0 { export *[const]:4 s0512; } +Simm32_0512x: "##"^val is i0510 & immexted=1 [ val = (immext << 6) | i0510; ] { export *[const]:4 val; } # u32 + +Simm32_2127_0513x: "#"^val is s2127 & i0513 & immexted=0 [ val = (s2127 << 9) | i0513; ] { export *[const]:4 val; } +Simm32_2127_0513x: "##"^val is i0510 & immexted=1 [ val = (simmext << 6) | i0510; ] { export *[const]:4 val; } # s32 + +Simm32_2223_1620_0513x: "#"^val is s2223 & i1620 & i0513 & immexted=0 [ val = (s2223 << 14) | (i1620 << 9) | i0513; ] { export *[const]:4 val; } +Simm32_2223_1620_0513x: "##"^val is i0510 & immexted=1 [ val = (immext << 6) | i0510; ] { export *[const]:4 val; } # u32 + +Simm32_2122_13_0507x: "#"^val is s2122 & i13 & i0507 & immexted=0 [ val = (s2122 << 4) | (i13 << 3) | i0507; ] { export *[const]:4 val; } +Simm32_2122_13_0507x: "##"^val is i2122 & i13 & i0507 & immexted=1 [ val = (immext << 6) | (i2122 << 4) | (i13 << 3) | i0507; ] { export *[const]:4 val; } # u32 + +Simm32_21_0513x: "#"^val is s21 & i0513 & immexted=0 [ val = (s21 << 9) | i0513; ] { export *[const]:4 val; } +Simm32_21_0513x: "##"^val is s21 & i0510 & immexted=1 [ val = (immext << 6) | i0510; ] { export *[const]:4 val; } # u32 + +Simm32_1619_0512x: "#"^val is s1619 & i0512 & immexted=0 [ val = (s1619 << 8) | i0512; ] { export *[const]:4 val; } +Simm32_1619_0512x: "##"^val is i0510 & immexted=1 [ val = (immext << 6) | i0510; ] { export *[const]:4 val; } # u32 + +Simm32_2026x: "#"^s2026 is s2026 & immexted=0 { export *[const]:4 s2026; } +Simm32_2026x: "##"^val is i2025 & immexted=1 [ val = (simmext << 6) | i2025; ] { export *[const]:4 val; } # s32 + +Uimm32_2123_13_0507_03x: "#"^val is i2123 & i13 & i0507 & i3 & immexted=0 [ val = (i2123 << 5) | (i13 << 4) | (i0507 << 1) | i3; ] { export *[const]:4 val; } +Uimm32_2123_13_0507_03x: "##"^val is op21 & i13 & i0507 & i3 & immexted=1 [ val = (immext << 6) | (op21 << 5) | (i13 << 4) | (i0507 << 1) | i3; ] { export *[const]:4 val; } + +Uimm32_2122_13_0507x: "#"^val is i2122 & i13 & i0507 & immexted=0 [ val = (i2122 << 4) | (i13 << 3) | i0507; ] { export *[const]:4 val; } +Uimm32_2122_13_0507x: "##"^val is i2122 & i13 & i0507 & immexted=1 [ val = (immext << 6) | (i2122 << 4) | (i13 << 3) | i0507; ] { export *[const]:4 val; } + +Uimm32_1620_13x: "#"^val is i1620 & i13 & immexted=0 [ val = (i1620 << 1) | i13; ] { export *[const]:4 val; } +Uimm32_1620_13x: "##"^val is i1620 & i13 & immexted=1 [ val = (immext << 6) | (i1620 << 1) | i13; ] { export *[const]:4 val; } + +Uimm32_1620_08x: "#"^val is i1620 & i8 & immexted=0 [ val = (i1620 << 1) | i8; ] { export *[const]:4 val; } +Uimm32_1620_08x: "##"^val is i1620 & i8 & immexted=1 [ val = (immext << 6) | (i1620 << 1) | i8; ] { export *[const]:4 val; } + +Uimm32_1617_0306x: "#"^val is i1617 & i0306 & immexted=0 [ val = (i1617 << 4) | i0306; ] { export *[const]:4 val; } +Uimm32_1617_0306x: "##"^val is i1617 & i0306 & immexted=1 [ val = (immext << 6) | (i1617 << 4) | i0306; ] { export *[const]:4 val; } + +Uimm32_0811_0506x: "#"^val is i0811 & i0506 & immexted=0 [ val = (i0811 << 2) | i0506; ] { export *[const]:4 val; } +Uimm32_0811_0506x: "##"^val is i0811 & i0506 & immexted=1 [ val = (immext << 6) | (i0811 << 2) | i0506; ] { export *[const]:4 val; } + +Uimm32_0712x: "#"^i0712 is i0712 & immexted=0 { export *[const]:4 i0712; } +Uimm32_0712x: "##"^val is i0712 & immexted=1 [ val = (simmext << 6) | i0712; ] { export *[const]:4 val; } # s32 + +Uimm32_0513x: "#"^i0513 is i0513 & immexted=0 { export *[const]:4 i0513; } +Uimm32_0513x: "##"^val is i0510 & immexted=1 [ val = (immext << 6) | i0510; ] { export *[const]:4 val; } + +Uimm32_0512x: "#"^i0512 is i0512 & immexted=0 { export *[const]:4 i0512; } +Uimm32_0512x: "##"^val is i0510 & immexted=1 [ val = (immext << 6) | i0510; ] { export *[const]:4 val; } + +Uimm32_2025x: "#"^i2025 is i2025 & immexted=0 { export *[const]:4 i2025; } +Uimm32_2025x: "##"^val is i2025 & immexted=1 [ val = (immext << 6) | i2025; ] { export *[const]:4 val; } + +Uimm32_0005x: "#"^i0005 is i0005 & immexted=0 { export *[const]:4 i0005; } +Uimm32_0005x: "##"^val is i0005 & immexted=1 [ val = (immext << 6) | i0005; ] { export *[const]:4 val; } + +# Truncated Extended Immediates +# TODO: Should we be truncating extended constant values? Maybe not +# Assembler does permit extended immediate +/- values larger than operation size: +# p0 = cmpb.gtu (r1, ##212321) + +Simm16_13_0006x: "#"^val is s13 & i0006 & immexted=0 [ val = (s13 << 7) | i0006; ] { export *[const]:2 val; } +Simm16_13_0006x: "##"^val is i0005 & immexted=1 [ val = (immext << 6) | i0005; ] { export *[const]:2 val; } # u32 + +Simm8_13_0006x: "#"^val is s13 & i0006 & immexted=0 [ val = (s13 << 7) | i0006; ] { export *[const]:1 val; } +Simm8_13_0006x: "##"^val is i0005 & immexted=1 [ val = (immext << 6) | i0005; ] { export *[const]:1 val; } # u32 + +Simm8_13_0004x: "#"^val is s13 & i0004 & immexted=0 [ val = (s13 << 5) | i0004; ] { export *[const]:1 val; } +Simm8_13_0004x: "##"^val is i13 & i0004 & immexted=1 [ val = (immext << 6) | (i13 << 5) | i0004; ] { export *[const]:1 val; } # u32 + +Simm16_13_0004x: "#"^val is s13 & i0004 & immexted=0 [ val = (s13 << 5) | i0004; ] { export *[const]:2 val; } +Simm16_13_0004x: "##"^val is i13 & i0004 & immexted=1 [ val = (immext << 6) | (i13 << 5) | i0004; ] { export *[const]:2 val; } # u32 + +Uimm8_0511x: "#"^i0511 is i0511 & immexted=0 { export *[const]:1 i0511; } +Uimm8_0511x: "##"^val is i0510 & immexted=1 [ val = (immext << 6) | i0510; ] { export *[const]:1 val; } + +Uimm16_0511x: "#"^i0511 is i0511 & immexted=0 { export *[const]:2 i0511; } +Uimm16_0511x: "##"^val is i0510 & immexted=1 [ val = (immext << 6) | i0510; ] { export *[const]:2 val; } + +Simm16_0512x: "#"^s0512 is s0512 & immexted=0 { export *[const]:2 s0512; } +Simm16_0512x: "##"^val is i0510 & immexted=1 [ val = (simmext << 6) | i0510; ] { export *[const]:2 val; } + +# Clear mask which can be and-ed with source +ClrBit_0004w: "clrbit("^Uimm8_0004^")" is Uimm8_0004 { mask:4 = ~(1 << Uimm8_0004); export mask; } +ClrBit_0004h: "clrbit("^Uimm8_0004^")" is Uimm8_0004 { mask:2 = ~(1 << Uimm8_0004); export mask; } +ClrBit_0004b: "clrbit("^Uimm8_0004^")" is Uimm8_0004 { mask:1 = ~(1 << Uimm8_0004); export mask; } + +# Set mask which can be or-ed with source +SetBit_0004w: "setbit("^Uimm8_0004^")" is Uimm8_0004 { mask:4 = 1 << Uimm8_0004; export mask; } +SetBit_0004h: "setbit("^Uimm8_0004^")" is Uimm8_0004 { mask:2 = 1 << Uimm8_0004; export mask; } +SetBit_0004b: "setbit("^Uimm8_0004^")" is Uimm8_0004 { mask:1 = 1 << Uimm8_0004; export mask; } + +# embedded shift operand (Class-13): asl(Rx32,#U5) and lsr(Rx32,#U5) +ShiftRx_D04_I0812: "asl("^rx5,Uimm8_0812^")" is op4=0 & rx5 & Uimm8_0812 { tmp:4 = rx5 << Uimm8_0812; export tmp; } +ShiftRx_D04_I0812: "lsr("^rx5,Uimm8_0812^")" is op4=1 & rx5 & Uimm8_0812 { tmp:4 = rx5 >> Uimm8_0812; export tmp; } + +# embedded predicate and/or logic operand (Class-6): and(Pt4,[!]Pu4) and or(Pt4,[!]Pu4 ) +# NOTE: Decided to implement as full byte logic instead of single-bit boolean logic +PredLogic_S23_P0607: pu0607 is op23=0 & pu0607 { export pu0607; } +PredLogic_S23_P0607: "!"^pu0607 is op23=1 & pu0607 { tmp:1 = ~pu0607; export tmp; } +PredLogic_L21_S23_P0809_P0607: "and("^pu0809,PredLogic_S23_P0607^")" is op21=0 & pu0809 & PredLogic_S23_P0607 { tmp:1 = pu0809 & PredLogic_S23_P0607; export tmp; } +PredLogic_L21_S23_P0809_P0607: "or("^pu0809,PredLogic_S23_P0607^")" is op21=1 & pu0809 & PredLogic_S23_P0607 { tmp:1 = pu0809 | PredLogic_S23_P0607; export tmp; } + + +# Taken/Not-Taken (decoration only) + +Taken13: ":t" is op13=1 { } +Taken13: ":nt" is op13=0 { } + +Taken12: ":t" is op12=1 { } +Taken12: ":nt" is op12=0 { } + +NotTaken01: ":nt" is op1=1 { } +NotTaken01: is op1=0 { } + +# Predicate Register Condition for jump/call (least significant bit only) +FlowCondUU: ".if("pu0809name")" is op21=0 & pu0809name & pu0809 { + condition:1 = (pu0809 & 1); + <> + ConditionReg = condition; +} +FlowCondUU: ".if(!"pu0809name")" is op21=1 & pu0809name & pu0809 { + condition:1 = !(pu0809 & 1); + <> + ConditionReg = condition; +} + +# .new Predicate Register Condition for jump/call (least significant bit only) +FlowCondNewUU: ".if("pu0809name".new)" is op21=0 & pu0809name & pu0809 { + <> + ConditionReg = (pu0809 & 1); # predicate will already be comitted +} +FlowCondNewUU: ".if(!"pu0809name".new)" is op21=1 & pu0809name & pu0809 { + <> + ConditionReg = !(pu0809 & 1); # predicate will already be comitted +} + +# Predicate Register Condition for dealloc_return (least significant bit only) + +FlowCond0809_N11_S13: ".if("pu0809name")" is op13=0 & op11=0 & pu0809 & pu0809name { + condition:1 = (pu0809 & 1); + <> + ConditionReg = condition; +} +FlowCond0809_N11_S13: ".if(!"pu0809name")" is op13=1 & op11=0 & pu0809 & pu0809name { + condition:1 = !(pu0809 & 1); + <> + ConditionReg = condition; +} +FlowCond0809_N11_S13: ".if("pu0809name".new)" is op13=0 & op11=1 & pu0809 & pu0809name { + <> + ConditionReg = (pu0809 & 1); # predicate will already be comitted +} +FlowCond0809_N11_S13: ".if(!"pu0809name".new)" is op13=1 & op11=1 & pu0809 & pu0809name { + <> + ConditionReg = !(pu0809 & 1); # predicate will already be comitted +} + + +# Predicate Register Condition for Right Packed EE jumpr (least significant bit only, includes .new handling) + +FlowP0Cond_N01_S00: ".if(P0)" is op0=0 & op1=0 { + condition:1 = (P0 & 1); + <> + ConditionReg = condition; +} +FlowP0Cond_N01_S00: ".if(!P0)" is op0=1 & op1=0 { + condition:1 = !(P0 & 1); + <> + ConditionReg = condition; +} +FlowP0Cond_N01_S00: ".if(P0.new)" is op0=0 & op1=1 { + <> + ConditionReg = (P0 & 1); # P0 will already be comitted +} +FlowP0Cond_N01_S00: ".if(!P0.new)" is op0=1 & op1=1 { + <> + ConditionReg = !(P0 & 1); # P0 will already be comitted +} + + +# Predicate Register Condition for Right Packed EE conditional ops (least significant bit only, includes .new handling) + +P0Cond_N05_S04: ".if(P0)" is op4=0 & op5=1 { + condition:1 = (P0 & 1); + <> + ConditionReg = condition; + <> + ConditionReg = condition; +} +P0Cond_N05_S04: ".if(!P0)" is op4=1 & op5=1 { + condition:1 = !(P0 & 1); + <> + ConditionReg = condition; + <> + ConditionReg = condition; +} +P0Cond_N05_S04: ".if(P0.new)" is op4=0 & op5=0 { + condition:1 = 0; + <> + condition = (P0.new & 1); # use new predicate + ConditionReg = condition; + <> + ConditionReg = condition; +} +P0Cond_N05_S04: ".if(!P0.new)" is op4=1 & op5=0 { + condition:1 = 0; + <> + condition = !(P0.new & 1); # use new predicate + ConditionReg = condition; + <> + ConditionReg = condition; +} + + +# Predicate Register Condition for Left Packed EE conditional ops (least significant bit only, includes .new handling) + +P0Cond_N21_S20: ".if(P0)" is op20=0 & op21=1 { + condition:1 = (P0 & 1); + <> + ConditionReg = condition; + <> + ConditionReg = condition; +} +P0Cond_N21_S20: ".if(!P0)" is op20=1 & op21=1 { + condition:1 = !(P0 & 1); + <> + ConditionReg = condition; + <> + ConditionReg = condition; +} +P0Cond_N21_S20: ".if(P0.new)" is op20=0 & op21=0 { + condition:1 = 0; + <> + condition = (P0.new & 1); # use new predicate + ConditionReg = condition; + <> + ConditionReg = condition; +} +P0Cond_N21_S20: ".if(!P0.new)" is op20=1 & op21=0 { + condition:1 = 0; + <> + condition = !(P0.new & 1); # use new predicate + ConditionReg = condition; + <> + ConditionReg = condition; +} + + +# Predicate Register Condition (least significant bit only, includes .new handling) +# Only used by memory store which must be in last slot. + +PuCond0001_N07_S02: ".if("pu0001name")" is op2=0 & op7=0 & pu0001 & pu0001name { + condition:1 = (pu0001 & 1); + <> + ConditionReg = condition; + <> + ConditionReg = condition; +} +PuCond0001_N07_S02: ".if(!"pu0001name")" is op2=1 & op7=0 & pu0001 & pu0001name { + condition:1 = !(pu0001 & 1); + <> + ConditionReg = condition; + <> + ConditionReg = condition; +} +PuCond0001_N07_S02: ".if("pu0001name".new)" is op2=0 & op7=1 & pu0001_ & pu0001name { + condition:1 = 0; + <> + condition = (pu0001_ & 1); # use new predicate + ConditionReg = condition; + <> + ConditionReg = condition; +} +PuCond0001_N07_S02: ".if(!"pu0001name".new)" is op2=1 & op7=1 & pu0001_ & pu0001name { + condition:1 = 0; + <> + condition = !(pu0001_ & 1); # use new predicate + ConditionReg = condition; + <> + ConditionReg = condition; +} + + +# Predicate Register Condition (least significant bit only, includes .new handling) +# Only used by memory store which must be in last slot. + +PuCond0001_N13_S02: ".if("pu0001name")" is op2=0 & op13=0 & pu0001 & pu0001name { + condition:1 = (pu0001 & 1); + <> + ConditionReg = condition; + <> + ConditionReg = condition; +} +PuCond0001_N13_S02: ".if(!"pu0001name")" is op2=1 & op13=0 & pu0001 & pu0001name { + condition:1 = !(pu0001 & 1); + <> + ConditionReg = condition; + <> + ConditionReg = condition; +} +PuCond0001_N13_S02: ".if("pu0001name".new)" is op2=0 & op13=1 & pu0001_ & pu0001name { + condition:1 = 0; + <> + condition = (pu0001_ & 1); # use new predicate + ConditionReg = condition; + <> + ConditionReg = condition; +} +PuCond0001_N13_S02: ".if(!"pu0001name".new)" is op2=1 & op13=1 & pu0001_ & pu0001name { + condition:1 = 0; + <> + condition = !(pu0001_ & 1); # use new predicate + ConditionReg = condition; + <> + ConditionReg = condition; +} + + +# Predicate Register Condition (least significant bit only, includes .new handling) +# Only used by memory store which must be in last slot. + +PuCond0001_N25_S26: ".if("pu0001name")" is op26=0 & op25=0 & pu0001 & pu0001name { + condition:1 = (pu0001 & 1); + <> + ConditionReg = condition; + <> + ConditionReg = condition; +} +PuCond0001_N25_S26: ".if(!"pu0001name")" is op26=1 & op25=0 & pu0001 & pu0001name { + condition:1 = !(pu0001 & 1); + <> + ConditionReg = condition; + <> + ConditionReg = condition; +} +PuCond0001_N25_S26: ".if("pu0001name".new)" is op26=0 & op25=1 & pu0001_ & pu0001name { + condition:1 = 0; + <> + condition = (pu0001_ & 1); # use new predicate + ConditionReg = condition; + <> + ConditionReg = condition; +} +PuCond0001_N25_S26: ".if(!"pu0001name".new)" is op26=1 & op25=1 & pu0001_ & pu0001name { + condition:1 = 0; + <> + condition = !(pu0001_ & 1); # use new predicate + ConditionReg = condition; + <> + ConditionReg = condition; +} + + +# Predicate Register Condition (least significant bit only, includes .new handling) + +PuCond0809_N10_S11: ".if("pu0809name")" is op11=0 & op10=0 & pu0809 & pu0809name { + condition:1 = (pu0809 & 1); + <> + ConditionReg = condition; + <> + ConditionReg = condition; +} +PuCond0809_N10_S11: ".if(!"pu0809name")" is op11=1 & op10=0 & pu0809 & pu0809name { + condition:1 = !(pu0809 & 1); + <> + ConditionReg = condition; + <> + ConditionReg = condition; +} +PuCond0809_N10_S11: ".if("pu0809name".new)" is op11=0 & op10=1 & pu0809_ & pu0809name { + condition:1 = 0; + <> + condition = (pu0809_ & 1); # use new predicate + ConditionReg = condition; + <> + ConditionReg = condition; +} +PuCond0809_N10_S11: ".if(!"pu0809name".new)" is op11=1 & op10=1 & pu0809_ & pu0809name { + condition:1 = 0; + <> + condition = !(pu0809_ & 1); # use new predicate + ConditionReg = condition; + <> + ConditionReg = condition; +} + + +# Predicate Register Condition (least significant bit only, includes .new handling) +# Only used by memory load which must be in last slot. + +PuCond0910_N12_S11: ".if("pu0910name")" is op11=0 & op12=0 & pu0910 & pu0910name { + condition:1 = (pu0910 & 1); + <> + ConditionReg = condition; + <> + ConditionReg = condition; +} +PuCond0910_N12_S11: ".if(!"pu0910name")" is op11=1 & op12=0 & pu0910 & pu0910name { + condition:1 = !(pu0910 & 1); + <> + ConditionReg = condition; + <> + ConditionReg = condition; +} +PuCond0910_N12_S11: ".if("pu0910name".new)" is op11=0 & op12=1 & pu0910_ & pu0910name { + condition:1 = 0; + <> + condition = (pu0910_ & 1); # use new predicate + ConditionReg = condition; + <> + ConditionReg = condition; +} +PuCond0910_N12_S11: ".if(!"pu0910name".new)" is op11=1 & op12=1 & pu0910_ & pu0910name { + condition:1 = 0; + <> + condition = !(pu0910_ & 1); # use new predicate + ConditionReg = condition; + <> + ConditionReg = condition; +} + + +# Predicate Register Condition (least significant bit only, includes .new handling) +# Only used by memory load which must be in last slot. + +PuCond1112_N25_S26: ".if("pu1112name")" is op26=0 & op25=0 & pu1112 & pu1112name { + condition:1 = (pu1112 & 1); + <> + ConditionReg = condition; + <> + ConditionReg = condition; +} +PuCond1112_N25_S26: ".if(!"pu1112name")" is op26=1 & op25=0 & pu1112 & pu1112name { + condition:1 = !(pu1112 & 1); + <> + ConditionReg = condition; + <> + ConditionReg = condition; +} +PuCond1112_N25_S26: ".if("pu1112name".new)" is op26=0 & op25=1 & pu1112_ & pu1112name { + condition:1 = 0; + <> + condition = (pu1112_ & 1); # use new predicate + ConditionReg = condition; + <> + ConditionReg = condition; +} +PuCond1112_N25_S26: ".if(!"pu1112name".new)" is op26=1 & op25=1 & pu1112_ & pu1112name { + condition:1 = 0; + <> + condition = !(pu1112_ & 1); # use new predicate + ConditionReg = condition; + <> + ConditionReg = condition; +} + + +# Predicate Register Condition (least significant bit only, includes .new handling) + +PuCond2122_N13_S23: ".if("pu2122name")" is op23=0 & op13=0 & pu2122 & pu2122name { + condition:1 = (pu2122 & 1); + <> + ConditionReg = condition; + <> + ConditionReg = condition; +} +PuCond2122_N13_S23: ".if(!"pu2122name")" is op23=1 & op13=0 & pu2122 & pu2122name { + condition:1 = !(pu2122 & 1); + <> + ConditionReg = condition; + <> + ConditionReg = condition; +} +PuCond2122_N13_S23: ".if("pu2122name".new)" is op23=0 & op13=1 & pu2122_ & pu2122name { + condition:1 = 0; + <> + condition = (pu2122_ & 1); # use new predicate + ConditionReg = condition; + <> + ConditionReg = condition; +} +PuCond2122_N13_S23: ".if(!"pu2122name".new)" is op23=1 & op13=1 & pu2122_ & pu2122name { + condition:1 = 0; + <> + condition = !(pu2122_ & 1); # use new predicate + ConditionReg = condition; + <> + ConditionReg = condition; +} + + +# Predicate Register Condition (least significant bit only, includes .new handling) + +PuCond0506_N13_S07: ".if("pu0506name")" is op7=0 & op13=0 & pu0506 & pu0506name { + condition:1 = (pu0506 & 1); + <> + ConditionReg = condition; + <> + ConditionReg = condition; +} +PuCond0506_N13_S07: ".if(!"pu0506name")" is op7=1 & op13=0 & pu0506 & pu0506name { + condition:1 = !(pu0506 & 1); + <> + ConditionReg = condition; + <> + ConditionReg = condition; +} +PuCond0506_N13_S07: ".if("pu0506name".new)" is op7=0 & op13=1 & pu0506_ & pu0506name { + condition:1 = 0; + <> + condition = (pu0506_ & 1); # use new predicate + ConditionReg = condition; + <> + ConditionReg = condition; +} +PuCond0506_N13_S07: ".if(!"pu0506name".new)" is op7=1 & op13=1 & pu0506_ & pu0506name { + condition:1 = 0; + <> + condition = !(pu0506_ & 1); # use new predicate + ConditionReg = condition; + <> + ConditionReg = condition; +} + +# Predicate Register Condition (least significant bit only, includes .new handling) +# Only used by memory load/store which must be in last slot. + +PuCond0506_N25_S24: ".if("pu0506name")" is op24=0 & op25=0 & pu0506 & pu0506name { + condition:1 = (pu0506 & 1); + <> + ConditionReg = condition; + <> + ConditionReg = condition; +} +PuCond0506_N25_S24: ".if(!"pu0506name")" is op24=1 & op25=0 & pu0506 & pu0506name { + condition:1 = !(pu0506 & 1); + <> + ConditionReg = condition; + <> + ConditionReg = condition; +} +PuCond0506_N25_S24: ".if("pu0506name".new)" is op24=0 & op25=1 & pu0506_ & pu0506name { + condition:1 = 0; + <> + condition = (pu0506_ & 1); # use new predicate + ConditionReg = condition; + <> + ConditionReg = condition; +} +PuCond0506_N25_S24: ".if(!"pu0506name".new)" is op24=1 & op25=1 & pu0506_ & pu0506name { + condition:1 = 0; + <> + condition = !(pu0506_ & 1); # use new predicate + ConditionReg = condition; + <> + ConditionReg = condition; +} + + +# Predicate Register Condition (least significant bit only, includes .new handling) +# Only used by memory store which must be in last slot. + +PuCond0506_N24_S23: ".if("pu0506name")" is op23=0 & op24=0 & pu0506 & pu0506name { + condition:1 = (pu0506 & 1); + <> + ConditionReg = condition; + <> + ConditionReg = condition; +} +PuCond0506_N24_S23: ".if(!"pu0506name")" is op23=1 & op24=0 & pu0506 & pu0506name { + condition:1 = !(pu0506 & 1); + <> + ConditionReg = condition; + <> + ConditionReg = condition; +} +PuCond0506_N24_S23: ".if("pu0506name".new)" is op23=0 & op24=1 & pu0506_ & pu0506name { + condition:1 = 0; + <> + condition = (pu0506_ & 1); # use new predicate + ConditionReg = condition; + <> + ConditionReg = condition; +} +PuCond0506_N24_S23: ".if(!"pu0506name".new)" is op23=1 & op24=1 & pu0506_ & pu0506name { + condition:1 = 0; + <> + condition = !(pu0506_ & 1); # use new predicate + ConditionReg = condition; + <> + ConditionReg = condition; +} + + +# +# Class-3 Memory Access +# + +# Class-3 Store Memory: Rs+#u6 - (u6 is NOT extended) +StAddrRsRelC3: "("^rs5^")" is rs5 & i0712=0 { + ptr:4 = rs5; # must use temp for delayed reference + export ptr; +} +StAddrRsRelC3: "("^rs5^"+#"^offs^")" is rs5 & i0712 [ offs = i0712 << shift; ] { + ptr:4 = rs5 + offs; + export ptr; +} +#StMemRsRelC3d: StAddrRsRelC3 is StAddrRsRelC3 [ shift = 3; ] { export *[ram]:8 StAddrRsRelC3; } +StMemRsRelC3w: StAddrRsRelC3 is StAddrRsRelC3 [ shift = 2; ] { export *[ram]:4 StAddrRsRelC3; } +StMemRsRelC3h: StAddrRsRelC3 is StAddrRsRelC3 [ shift = 1; ] { export *[ram]:2 StAddrRsRelC3; } +StMemRsRelC3b: StAddrRsRelC3 is StAddrRsRelC3 [ shift = 0; ] { export *[ram]:1 StAddrRsRelC3; } + +# Class-3 Store Memory: Rs+#u6x - (u6 is extended) +StAddrRsRelxC3: "("^rs5^")" is rs5 & i0712=0 & immexted=0 { + ptr:4 = rs5; # must use temp for delayed reference + export ptr; +} +StAddrRsRelxC3: "("^rs5^"+#"^offs^")" is rs5 & i0712 & immexted=0 [ offs = i0712 << shift; ] { + ptr:4 = rs5 + offs; + export ptr; +} +StAddrRsRelxC3: "("^rs5^"+##"^offs^")" is rs5 & i0712 & immexted=1 [ offs = (immext << 6) | i0712; ] { + ptr:4 = rs5 + offs; + export ptr; +} +#StMemRsRelxC3d: StAddrRsRelxC3 is StAddrRsRelxC3 [ shift = 3; ] { export *[ram]:8 StAddrRsRelxC3; } +StMemRsRelxC3w: StAddrRsRelxC3 is StAddrRsRelxC3 [ shift = 2; ] { export *[ram]:4 StAddrRsRelxC3; } +StMemRsRelxC3h: StAddrRsRelxC3 is StAddrRsRelxC3 [ shift = 1; ] { export *[ram]:2 StAddrRsRelxC3; } +StMemRsRelxC3b: StAddrRsRelxC3 is StAddrRsRelxC3 [ shift = 0; ] { export *[ram]:1 StAddrRsRelxC3; } + + +# Class-3 Memory: Rs+Rt<<#n2 +AddrRsRelShiftC3: "("^rs5^"+"^rt5^")" is rs5 & rt5 & op13=0 & op7=0 { + tmp:4 = rs5 + rt5; + export tmp; +} +AddrRsRelShiftC3: "("^rs5^"+"^rt5^"<<"^Uimm2_13_07^")" is rs5 & rt5 & Uimm2_13_07 { + # TODO: verify order of operation + # TODO: Is there an alignment shift? + tmp:4 = rs5 + (rt5 << Uimm2_13_07); + export tmp; +} +MemRsRelShiftC3d: AddrRsRelShiftC3 is AddrRsRelShiftC3 { export *[ram]:8 AddrRsRelShiftC3; } +MemRsRelShiftC3w: AddrRsRelShiftC3 is AddrRsRelShiftC3 { export *[ram]:4 AddrRsRelShiftC3; } +MemRsRelShiftC3h: AddrRsRelShiftC3 is AddrRsRelShiftC3 { export *[ram]:2 AddrRsRelShiftC3; } +MemRsRelShiftC3b: AddrRsRelShiftC3 is AddrRsRelShiftC3 { export *[ram]:1 AddrRsRelShiftC3; } + + +# +# Class-4 Memory Access +# + +# Class-4 Load Memory: Rs+#u6x +LdAddrRsRelxC4: "("^rs5^")" is rs5 & i0510=0 & immexted=0 { + ptr:4 = rs5; # must use temp for delayed reference + export ptr; +} +LdAddrRsRelxC4: "("^rs5^"+#"^offs^")" is rs5 & i0510 & immexted=0 [ offs = i0510 << shift; ] { + ptr:4 = rs5 + offs; + export ptr; +} +LdAddrRsRelxC4: "("^rs5^"+##"^offs^")" is rs5 & i0510 & immexted=1 [ offs = (immext << 6) | i0510; ] { + ptr:4 = rs5 + offs; + export ptr; +} +LdMemRsRelxC4d: LdAddrRsRelxC4 is LdAddrRsRelxC4 [ shift = 3; ] { export *[ram]:8 LdAddrRsRelxC4; } +LdMemRsRelxC4w: LdAddrRsRelxC4 is LdAddrRsRelxC4 [ shift = 2; ] { export *[ram]:4 LdAddrRsRelxC4; } +LdMemRsRelxC4h: LdAddrRsRelxC4 is LdAddrRsRelxC4 [ shift = 1; ] { export *[ram]:2 LdAddrRsRelxC4; } +LdMemRsRelxC4b: LdAddrRsRelxC4 is LdAddrRsRelxC4 [ shift = 0; ] { export *[ram]:1 LdAddrRsRelxC4; } + +# Class-4 Store Memory: Rs+#u6x +StAddrRsRelxC4: "("^rs5^")" is rs5 & i13=0 & i0307=0 & immexted=0 { + ptr:4 = rs5; # must use temp for delayed reference + export ptr; +} +StAddrRsRelxC4: "("^rs5^"+#"^offs^")" is rs5 & i13 & i0307 & immexted=0 [ offs = ((i13 << 5) | i0307) << shift; ] { + ptr:4 = rs5 + offs; + export ptr; +} +StAddrRsRelxC4: "("^rs5^"+##"^offs^")" is rs5 & i13 & i0307 & immexted=1 [ offs = (immext << 6) | (i13 << 5) | i0307; ] { + ptr:4 = rs5 + offs; + export ptr; +} +StMemRsRelxC4d: StAddrRsRelxC4 is StAddrRsRelxC4 [ shift = 3; ] { export *[ram]:8 StAddrRsRelxC4; } +StMemRsRelxC4w: StAddrRsRelxC4 is StAddrRsRelxC4 [ shift = 2; ] { export *[ram]:4 StAddrRsRelxC4; } +StMemRsRelxC4h: StAddrRsRelxC4 is StAddrRsRelxC4 [ shift = 1; ] { export *[ram]:2 StAddrRsRelxC4; } +StMemRsRelxC4b: StAddrRsRelxC4 is StAddrRsRelxC4 [ shift = 0; ] { export *[ram]:1 StAddrRsRelxC4; } + +# Class-4 Load Memory: GP+#u16x +LdAddrGPRelxC4: "("^GP^"+#"^offs^")" is i2526 & i1620 & i0513 & GP & immexted=0 + [ offs = ((i2526 << 14) | (i1620 << 9) | i0513) << shift; ] { + local ptr = GP + offs; + export ptr; +} +LdAddrGPRelxC4: "(##"^offs^")" is i0510 & immexted=1 [ offs = (immext << 6) | i0510; ] { + export *[const]:4 offs; +} +LdMemGPRelxC4d: LdAddrGPRelxC4 is LdAddrGPRelxC4 [ shift = 3; ] { export *[ram]:8 LdAddrGPRelxC4; } +LdMemGPRelxC4w: LdAddrGPRelxC4 is LdAddrGPRelxC4 [ shift = 2; ] { export *[ram]:4 LdAddrGPRelxC4; } +LdMemGPRelxC4h: LdAddrGPRelxC4 is LdAddrGPRelxC4 [ shift = 1; ] { export *[ram]:2 LdAddrGPRelxC4; } +LdMemGPRelxC4b: LdAddrGPRelxC4 is LdAddrGPRelxC4 [ shift = 0; ] { export *[ram]:1 LdAddrGPRelxC4; } + +# Class-4 Store Memory: GP+#u16x +StAddrGPRelxC4: "("^GP^"+#"^offs^")" is i2526 & i1620 & i13 & i0007 & GP & immexted=0 + [ offs = ((i2526 << 14) | (i1620 << 9) | (i13 << 8) | i0007) << shift; ] { + local ptr = GP + offs; + export ptr; +} +StAddrGPRelxC4: "(##"^offs^")" is i0005 & immexted=1 [ offs = (immext << 6) | i0005; ] { + export *[const]:4 offs; +} +StMemGPRelxC4d: StAddrGPRelxC4 is StAddrGPRelxC4 [ shift = 3; ] { export *[ram]:8 StAddrGPRelxC4; } +StMemGPRelxC4w: StAddrGPRelxC4 is StAddrGPRelxC4 [ shift = 2; ] { export *[ram]:4 StAddrGPRelxC4; } +StMemGPRelxC4h: StAddrGPRelxC4 is StAddrGPRelxC4 [ shift = 1; ] { export *[ram]:2 StAddrGPRelxC4; } +StMemGPRelxC4b: StAddrGPRelxC4 is StAddrGPRelxC4 [ shift = 0; ] { export *[ram]:1 StAddrGPRelxC4; } + + +# +# Class-9 Memory Access +# + +# Class-9 Load Memory: (Rs32) +LdAddrRsRelC9: "("^rs5^")" is rs5 { export rs5; } +LdMemRsRelC9d: LdAddrRsRelC9 is LdAddrRsRelC9 { export *[ram]:8 LdAddrRsRelC9; } +LdMemRsRelC9w: LdAddrRsRelC9 is LdAddrRsRelC9 { export *[ram]:4 LdAddrRsRelC9; } +#LdMemRsRelC9h: LdAddrRsRelC9 is LdAddrRsRelC9 { export *[ram]:2 LdAddrRsRelC9; } +#LdMemRsRelC9b: LdAddrRsRelC9 is LdAddrRsRelC9 { export *[ram]:1 LdAddrRsRelC9; } + +# Class-9 Load Memory: Rf=#U6x +LdAddrRsAssignxC9: "("^rf5^"="^Uimm32_0811_0506x^")" is rf5 & rf5_ & Uimm32_0811_0506x { + # TODO: Need to verify behavior !! + rf5_ = Uimm32_0811_0506x; + export Uimm32_0811_0506x; + <> + rf5 = rf5_; +} +LdMemRsAssignxC9d: LdAddrRsAssignxC9 is LdAddrRsAssignxC9 { export *[ram]:8 LdAddrRsAssignxC9; } +LdMemRsAssignxC9w: LdAddrRsAssignxC9 is LdAddrRsAssignxC9 { export *[ram]:4 LdAddrRsAssignxC9; } +LdMemRsAssignxC9h: LdAddrRsAssignxC9 is LdAddrRsAssignxC9 { export *[ram]:2 LdAddrRsAssignxC9; } +LdMemRsAssignxC9b: LdAddrRsAssignxC9 is LdAddrRsAssignxC9 { export *[ram]:1 LdAddrRsAssignxC9; } + +# Class-9 Load Memory: #u6x +LdAddrAbsU6xC9: "("^Uimm32_1620_08x^")" is Uimm32_1620_08x { export Uimm32_1620_08x; } + +LdMemAbsU6xC9d: LdAddrAbsU6xC9 is LdAddrAbsU6xC9 { export *[ram]:8 LdAddrAbsU6xC9; } +LdMemAbsU6xC9w: LdAddrAbsU6xC9 is LdAddrAbsU6xC9 { export *[ram]:4 LdAddrAbsU6xC9; } +LdMemAbsU6xC9h: LdAddrAbsU6xC9 is LdAddrAbsU6xC9 { export *[ram]:2 LdAddrAbsU6xC9; } +LdMemAbsU6xC9b: LdAddrAbsU6xC9 is LdAddrAbsU6xC9 { export *[ram]:1 LdAddrAbsU6xC9; } + + +# Class-9 Load Memory: ( Rs32 << #n2 + #U6x ) +LdAddrRsRelShiftxC9: "("^rs5^"+"^Uimm32_0811_0506x^")" is rs5 & op13=0 & op7=0 & Uimm32_0811_0506x { + tmp:4 = rs5 + Uimm32_0811_0506x; + export tmp; +} +LdAddrRsRelShiftxC9: "("^rs5^"<<"^Uimm2_13_07^"+"^Uimm32_0811_0506x^")" is rs5 & Uimm2_13_07 & Uimm32_0811_0506x { + # TODO: verify order of operation + # TODO: Is there an alignment shift? + tmp:4 = (rs5 << Uimm2_13_07) + Uimm32_0811_0506x; + export tmp; +} +LdMemRsRelShiftxC9d: LdAddrRsRelShiftxC9 is LdAddrRsRelShiftxC9 { export *[ram]:8 LdAddrRsRelShiftxC9; } +LdMemRsRelShiftxC9w: LdAddrRsRelShiftxC9 is LdAddrRsRelShiftxC9 { export *[ram]:4 LdAddrRsRelShiftxC9; } +LdMemRsRelShiftxC9h: LdAddrRsRelShiftxC9 is LdAddrRsRelShiftxC9 { export *[ram]:2 LdAddrRsRelShiftxC9; } +LdMemRsRelShiftxC9b: LdAddrRsRelShiftxC9 is LdAddrRsRelShiftxC9 { export *[ram]:1 LdAddrRsRelShiftxC9; } + + +# Class-9 Load Memory: Rs+#s11x +LdAddrRsRelxC9: "("^rs5^")" is op27=0 & rs5 & i2526=0 & i0513=0 & immexted=0 { + ptr:4 = rs5; # must use temp for delayed reference + export ptr; +} +LdAddrRsRelxC9: "("^rs5^"+#"^offs^")" is op27=0 & rs5 & s2526 & i0513 & immexted=0 + [ offs = ((s2526 << 9) | i0513) << shift; ] { + ptr:4 = rs5 + offs; + export ptr; +} +LdAddrRsRelxC9: "("^rs5^"+##"^offs^")" is op27=0 & rs5 & i0510 & immexted=1 [ offs = (immext << 6) | i0510; ] { + ptr:4 = rs5 + offs; + export ptr; +} +LdMemRsRelxC9d: LdAddrRsRelxC9 is LdAddrRsRelxC9 [ shift = 3; ] { export *[ram]:8 LdAddrRsRelxC9; } +LdMemRsRelxC9w: LdAddrRsRelxC9 is LdAddrRsRelxC9 [ shift = 2; ] { export *[ram]:4 LdAddrRsRelxC9; } +LdMemRsRelxC9h: LdAddrRsRelxC9 is LdAddrRsRelxC9 [ shift = 1; ] { export *[ram]:2 LdAddrRsRelxC9; } +LdMemRsRelxC9b0: LdAddrRsRelxC9 is LdAddrRsRelxC9 [ shift = 0; ] { export *[ram]:1 LdAddrRsRelxC9; } +LdMemRsRelxC9b1: LdAddrRsRelxC9 is LdAddrRsRelxC9 [ shift = 1; ] { export *[ram]:1 LdAddrRsRelxC9; } +LdMemRsRelxC9b2: LdAddrRsRelxC9 is LdAddrRsRelxC9 [ shift = 2; ] { export *[ram]:1 LdAddrRsRelxC9; } + +# Class-9 Load Memory: Rx++#s4 -- 'cond=1' context must be set by conditional instructions! +LdAddrAIS4C9: "("^rx5^"++#"^inc^")" is cond=0 & rx5 & rx5_ & s0508 [ inc = s0508 << shift; ] { + tmp:4 = rx5 + inc; + export rx5; + <> + rx5 = tmp; +} +LdAddrAIS4C9: "("^rx5^"++#"^inc^")" is cond=1 & rx5 & rx5_ & s0508 [ inc = s0508 << shift; ] { + tmp:4 = rx5 + inc; + export rx5; + <> + if (ConditionReg == 0) goto ; + rx5 = tmp; + +} +LdMemAIS4C9d: LdAddrAIS4C9 is LdAddrAIS4C9 [ shift = 3; ] { export *[ram]:8 LdAddrAIS4C9; } +LdMemAIS4C9w: LdAddrAIS4C9 is LdAddrAIS4C9 [ shift = 2; ] { export *[ram]:4 LdAddrAIS4C9; } +LdMemAIS4C9h: LdAddrAIS4C9 is LdAddrAIS4C9 [ shift = 1; ] { export *[ram]:2 LdAddrAIS4C9; } +LdMemAIS4C9b0: LdAddrAIS4C9 is LdAddrAIS4C9 [ shift = 0; ] { export *[ram]:1 LdAddrAIS4C9; } +LdMemAIS4C9b1: LdAddrAIS4C9 is LdAddrAIS4C9 [ shift = 1; ] { export *[ram]:1 LdAddrAIS4C9; } +LdMemAIS4C9b2: LdAddrAIS4C9 is LdAddrAIS4C9 [ shift = 2; ] { export *[ram]:1 LdAddrAIS4C9; } + +# Class-9 Load Memory: Rx++#s4:circ(Mu) -- 'cond=1' context must be set by conditional instructions! +LdAddrAIS4CircMuC9: "("^rx5^"++#"^inc^":circ("^mu^"))" is cond=0 & rx5 & rx5_ & mu & s0508 + [ inc = s0508 << shift; ] { + tmp:4 = circularAdd(rx5, inc:1, mu); + export rx5; + <> + rx5 = tmp; +} +LdAddrAIS4CircMuC9: "("^rx5^"++#"^inc^":circ("^mu^"))" is cond=1 & rx5 & rx5_ & mu & s0508 + [ inc = s0508 << shift; ] { + tmp:4 = circularAdd(rx5, inc:1, mu); + export rx5; + <> + if (ConditionReg == 0) goto ; + rx5 = tmp; + +} +LdMemAIS4CircMuC9d: LdAddrAIS4CircMuC9 is LdAddrAIS4CircMuC9 [ shift = 3; ] { export *[ram]:8 LdAddrAIS4CircMuC9; } +LdMemAIS4CircMuC9w: LdAddrAIS4CircMuC9 is LdAddrAIS4CircMuC9 [ shift = 2; ] { export *[ram]:4 LdAddrAIS4CircMuC9; } +LdMemAIS4CircMuC9h: LdAddrAIS4CircMuC9 is LdAddrAIS4CircMuC9 [ shift = 1; ] { export *[ram]:2 LdAddrAIS4CircMuC9; } +LdMemAIS4CircMuC9b0: LdAddrAIS4CircMuC9 is LdAddrAIS4CircMuC9 [ shift = 0; ] { export *[ram]:1 LdAddrAIS4CircMuC9; } +LdMemAIS4CircMuC9b1: LdAddrAIS4CircMuC9 is LdAddrAIS4CircMuC9 [ shift = 1; ] { export *[ram]:1 LdAddrAIS4CircMuC9; } +LdMemAIS4CircMuC9b2: LdAddrAIS4CircMuC9 is LdAddrAIS4CircMuC9 [ shift = 2; ] { export *[ram]:1 LdAddrAIS4CircMuC9; } + +# Class-9 Load Memory: Rx++I:circ(Mu) -- 'cond=1' context must be set by conditional instructions! +LdAddrAIICircMuC9: "("^rx5^"++I:circ("^mu^"))" is cond=0 & rx5 & rx5_ & mu { + i = (mu[28,4] << 7) | mu[17,7]; # Isolate I value from specified M0/M1 reg + tmp:4 = circularAdd(rx5, i, mu); + export rx5; + <> + rx5 = tmp; +} +LdAddrAIICircMuC9: "("^rx5^"++I:circ("^mu^"))" is cond=1 & rx5 & rx5_ & mu { + i = (mu[28,4] << 7) | mu[17,7]; # Isolate I value from specified M0/M1 reg + tmp:4 = circularAdd(rx5, i, mu); + export rx5; + <> + if (ConditionReg == 0) goto ; + rx5 = tmp; + +} +LdMemAIICircMuC9d: LdAddrAIICircMuC9 is LdAddrAIICircMuC9 { export *[ram]:8 LdAddrAIICircMuC9; } +LdMemAIICircMuC9w: LdAddrAIICircMuC9 is LdAddrAIICircMuC9 { export *[ram]:4 LdAddrAIICircMuC9; } +LdMemAIICircMuC9h: LdAddrAIICircMuC9 is LdAddrAIICircMuC9 { export *[ram]:2 LdAddrAIICircMuC9; } +LdMemAIICircMuC9b: LdAddrAIICircMuC9 is LdAddrAIICircMuC9 { export *[ram]:1 LdAddrAIICircMuC9; } + +# Class-9 Load Memory: Rx++Mu and Rx++Mu:brev - op25 selects mode -- 'cond=1' context must be set by conditional instructions! +LdAddrAIMuC9: "("^rx5^"++"^mu^")" is cond=0 & op25=0 & rx5 & rx5_ & mu { + tmp:4 = rx5 + mu; + ptr:4 = rx5; + export ptr; + <> + rx5 = tmp; +} +LdAddrAIMuC9: "("^rx5^"++"^mu^")" is cond=1 & op25=0 & rx5 & rx5_ & mu { + tmp:4 = rx5 + mu; + ptr:4 = rx5; + export ptr; + <> + if (ConditionReg == 0) goto ; + rx5 = tmp; + +} +LdAddrAIMuC9: "("^rx5^"++"^mu^":brev)" is cond=0 & op25=1 & rx5 & rx5_ & mu { + ptr:4 = (rx5 & 0xffff0000) + bitReverse(rx5 & 0x0ffff); + tmp:4 = rx5 + mu; + export ptr; + <> + rx5 = tmp; +} +LdAddrAIMuC9: "("^rx5^"++"^mu^":brev)" is cond=1 & op25=1 & rx5 & rx5_ & mu { + ptr:4 = (rx5 & 0xffff0000) + bitReverse(rx5 & 0x0ffff); + tmp:4 = rx5 + mu; + export ptr; + <> + if (ConditionReg == 0) goto ; + rx5 = tmp; + +} +LdMemAIMuC9d: LdAddrAIMuC9 is LdAddrAIMuC9 { export *[ram]:8 LdAddrAIMuC9; } +LdMemAIMuC9w: LdAddrAIMuC9 is LdAddrAIMuC9 { export *[ram]:4 LdAddrAIMuC9; } +LdMemAIMuC9h: LdAddrAIMuC9 is LdAddrAIMuC9 { export *[ram]:2 LdAddrAIMuC9; } +LdMemAIMuC9b: LdAddrAIMuC9 is LdAddrAIMuC9 { export *[ram]:1 LdAddrAIMuC9; } + + +# Class-9 Load Memory: #u6x - (no shift factor) +LdAddrU6xC9: "(#"^offs^")" is i1620 & i8 & immexted=0 [ offs = (i1620 << 1) | i8; ] { + export *[const]:4 offs; +} +LdAddrU6xC9: "(##"^offs^")" is i1620 & i8 & immexted=1 [ offs = (immext << 6) | (i1620 << 1) | i8; ] { + export *[const]:4 offs; +} +#LdMemU6xC9d: LdAddrU6xC9 is LdAddrU6xC9 { export *[ram]:8 LdAddrU6xC9; } +#LdMemU6xC9w: LdAddrU6xC9 is LdAddrU6xC9 { export *[ram]:4 LdAddrU6xC9; } +LdMemU6xC9h: LdAddrU6xC9 is LdAddrU6xC9 { export *[ram]:2 LdAddrU6xC9; } +#LdMemU6xC9b: LdAddrU6xC9 is LdAddrU6xC9 { export *[ram]:1 LdAddrU6xC9; } + + +# +# Class-10 Memory Access +# + +# Class-9 Load Memory: (Rs32, Pd4) # predicate displayed only! +StAddrRsRelPdC9: "("^rs5,pu0001^")" is rs5 & pu0001 { export rs5; } +StMemRsRelPdC9w: StAddrRsRelPdC9 is StAddrRsRelPdC9 { export *[ram]:4 StAddrRsRelPdC9; } +StMemRsRelPdC9d: StAddrRsRelPdC9 is StAddrRsRelPdC9 { export *[ram]:8 StAddrRsRelPdC9; } +#StMemRsRelPdC9h: StAddrRsRelPdC9 is StAddrRsRelPdC9 { export *[ram]:2 StAddrRsRelPdC9; } +#StMemRsRelPdC9b: StAddrRsRelPdC9 is StAddrRsRelPdC9 { export *[ram]:1 StAddrRsRelPdC9; } + +# Class-10 Store Memory: Rf=#U6x -- 'cond=1' context must be set by conditional instructions! +StAddrRsAssignxC10: "("^rf5^"="^Uimm32_0005x^")" is cond=0 & rf5 & rf5_ & Uimm32_0005x { + # TODO: Need to verify behavior !! + rf5_ = Uimm32_0005x; + export rf5_; + <> + rf5 = rf5_; +} +StAddrRsAssignxC10: "("^rf5^"="^Uimm32_0005x^")" is cond=1 & rf5 & rf5_ & Uimm32_0005x { + # TODO: Need to verify behavior !! + rf5_ = Uimm32_0005x; + export rf5_; + <> + if (ConditionReg == 0) goto ; + rf5 = rf5_; + +} +StMemRsAssignxC10d: StAddrRsAssignxC10 is StAddrRsAssignxC10 { export *[ram]:8 StAddrRsAssignxC10; } +StMemRsAssignxC10w: StAddrRsAssignxC10 is StAddrRsAssignxC10 { export *[ram]:4 StAddrRsAssignxC10; } +StMemRsAssignxC10h: StAddrRsAssignxC10 is StAddrRsAssignxC10 { export *[ram]:2 StAddrRsAssignxC10; } +StMemRsAssignxC10b: StAddrRsAssignxC10 is StAddrRsAssignxC10 { export *[ram]:1 StAddrRsAssignxC10; } + +# Class-10 Store Memory: #u6x +StAddrAbsU6xC10: "("^Uimm32_1617_0306x^")" is Uimm32_1617_0306x { export Uimm32_1617_0306x; } + +StMemAbsU6xC10d: StAddrAbsU6xC10 is StAddrAbsU6xC10 { export *[ram]:8 StAddrAbsU6xC10; } +StMemAbsU6xC10w: StAddrAbsU6xC10 is StAddrAbsU6xC10 { export *[ram]:4 StAddrAbsU6xC10; } +StMemAbsU6xC10h: StAddrAbsU6xC10 is StAddrAbsU6xC10 { export *[ram]:2 StAddrAbsU6xC10; } +StMemAbsU6xC10b: StAddrAbsU6xC10 is StAddrAbsU6xC10 { export *[ram]:1 StAddrAbsU6xC10; } + +# Class-10 Store Memory: ( Rs32 << #n2 + #U6x ) +StAddrRsRelShiftxC10: "("^rs5^"+"^Uimm32_0005x^")" is rs5 & op13=0 & op6=0 & Uimm32_0005x { + tmp:4 = rs5 + Uimm32_0005x; + export tmp; +} +StAddrRsRelShiftxC10: "("^rs5^"<<"^Uimm2_13_06^"+"^Uimm32_0005x^")" is rs5 & Uimm2_13_06 & Uimm32_0005x { + # TODO: verify order of operation + # TODO: Is there an alignment shift? + tmp:4 = (rs5 << Uimm2_13_06) + Uimm32_0005x; + export tmp; +} +StMemRsRelShiftxC10d: StAddrRsRelShiftxC10 is StAddrRsRelShiftxC10 { export *[ram]:8 StAddrRsRelShiftxC10; } +StMemRsRelShiftxC10w: StAddrRsRelShiftxC10 is StAddrRsRelShiftxC10 { export *[ram]:4 StAddrRsRelShiftxC10; } +StMemRsRelShiftxC10h: StAddrRsRelShiftxC10 is StAddrRsRelShiftxC10 { export *[ram]:2 StAddrRsRelShiftxC10; } +StMemRsRelShiftxC10b: StAddrRsRelShiftxC10 is StAddrRsRelShiftxC10 { export *[ram]:1 StAddrRsRelShiftxC10; } + +# Class-10 Store Memory: Rs+#s11x +StAddrRsRelxC10: "("^rs5^")" is op27=0 & rs5 & s2526=0 & i13=0 & i0007=0 & immexted=0 { + ptr:4 = rs5; # must use temp for delayed reference + export ptr; +} +StAddrRsRelxC10: "("^rs5^"+#"^offs^")" is op27=0 & rs5 & s2526 & i13 & i0007 & immexted=0 + [ offs = ((s2526 << 9) | (i13 << 8) | i0007) << shift; ] { + ptr:4 = rs5 + offs; + export ptr; +} +StAddrRsRelxC10: "("^rs5^"+##"^offs^")" is op27=0 & rs5 & i0005 & immexted=1 [ offs = (immext << 6) | i0005; ] { + ptr:4 = rs5 + offs; + export ptr; +} +StMemRsRelxC10d: StAddrRsRelxC10 is StAddrRsRelxC10 [ shift = 3; ] { export *[ram]:8 StAddrRsRelxC10; } +StMemRsRelxC10w: StAddrRsRelxC10 is StAddrRsRelxC10 [ shift = 2; ] { export *[ram]:4 StAddrRsRelxC10; } +StMemRsRelxC10h: StAddrRsRelxC10 is StAddrRsRelxC10 [ shift = 1; ] { export *[ram]:2 StAddrRsRelxC10; } +StMemRsRelxC10b: StAddrRsRelxC10 is StAddrRsRelxC10 [ shift = 0; ] { export *[ram]:1 StAddrRsRelxC10; } + +# Class-10 Store Memory: Rx++#s4 -- 'cond=1' context must be set by conditional instructions! +StAddrAIS4C10: "("^rx5^"++#"^inc^")" is cond=0 & op2527=5 & rx5 & rx5_ & s0306 + [ inc = s0306 << shift; ] { + tmp:4 = rx5 + inc; + ptr:4 = rx5; + export ptr; + <> + rx5 = tmp; +} +StAddrAIS4C10: "("^rx5^"++#"^inc^")" is cond=1 & op2527=5 & rx5 & rx5_ & s0306 + [ inc = s0306 << shift; ] { + tmp:4 = rx5 + inc; + ptr:4 = rx5; + export ptr; + <> + if (ConditionReg == 0) goto ; + rx5 = tmp; + +} +StMemAIS4C10d: StAddrAIS4C10 is StAddrAIS4C10 [ shift = 3; ] { export *[ram]:8 StAddrAIS4C10; } +StMemAIS4C10w: StAddrAIS4C10 is StAddrAIS4C10 [ shift = 2; ] { export *[ram]:4 StAddrAIS4C10; } +StMemAIS4C10h: StAddrAIS4C10 is StAddrAIS4C10 [ shift = 1; ] { export *[ram]:2 StAddrAIS4C10; } +StMemAIS4C10b: StAddrAIS4C10 is StAddrAIS4C10 [ shift = 0; ] { export *[ram]:1 StAddrAIS4C10; } + +# Class-10 Store Memory: Rx++#s4:circ(Mu) -- 'cond=1' context must be set by conditional instructions! +StAddrAIS4CircMuC10: "("^rx5^"++#"^inc^":circ("^mu^"))" is cond=0 & op2527=4 & rx5 & rx5_ & mu & i1=0 & s0306 + [ inc = s0306 << shift; ] { + tmp:4 = circularAdd(rx5, inc:1, mu); + ptr:4 = rx5; + export ptr; + <> + rx5 = tmp; +} +StAddrAIS4CircMuC10: "("^rx5^"++#"^inc^":circ("^mu^"))" is cond=1 & op2527=4 & rx5 & rx5_ & mu & i1=0 & s0306 + [ inc = s0306 << shift; ] { + tmp:4 = circularAdd(rx5, inc:1, mu); + ptr:4 = rx5; + export ptr; + <> + if (ConditionReg == 0) goto ; + rx5 = tmp; + +} +StMemAIS4CircMuC10d: StAddrAIS4CircMuC10 is StAddrAIS4CircMuC10 [ shift = 3; ] { export *[ram]:8 StAddrAIS4CircMuC10; } +StMemAIS4CircMuC10w: StAddrAIS4CircMuC10 is StAddrAIS4CircMuC10 [ shift = 2; ] { export *[ram]:4 StAddrAIS4CircMuC10; } +StMemAIS4CircMuC10h: StAddrAIS4CircMuC10 is StAddrAIS4CircMuC10 [ shift = 1; ] { export *[ram]:2 StAddrAIS4CircMuC10; } +StMemAIS4CircMuC10b: StAddrAIS4CircMuC10 is StAddrAIS4CircMuC10 [ shift = 0; ] { export *[ram]:1 StAddrAIS4CircMuC10; } + +# Class-10 Store Memory: Rx++I:circ(Mu) -- 'cond=1' context must be set by conditional instructions! +StAddrAIICircMuC10: "("^rx5^"++I:circ("^mu^"))" is cond=0 & op2527=4 & rx5 & rx5_ & mu & i1=1 { + i = (mu[28,4] << 7) | mu[17,7]; # Isolate I value from specified M0/M1 reg + tmp:4 = circularAdd(rx5, i, mu); + ptr:4 = rx5; + export ptr; + <> + rx5 = tmp; +} +StAddrAIICircMuC10: "("^rx5^"++I:circ("^mu^"))" is cond=1 & op2527=4 & rx5 & rx5_ & mu & i1=1 { + i = (mu[28,4] << 7) | mu[17,7]; # Isolate I value from specified M0/M1 reg + tmp:4 = circularAdd(rx5, i, mu); + ptr:4 = rx5; + export ptr; + <> + if (ConditionReg == 0) goto ; + rx5 = tmp; + +} +StMemAIICircMuC10d: StAddrAIICircMuC10 is StAddrAIICircMuC10 { export *[ram]:8 StAddrAIICircMuC10; } +StMemAIICircMuC10w: StAddrAIICircMuC10 is StAddrAIICircMuC10 { export *[ram]:4 StAddrAIICircMuC10; } +StMemAIICircMuC10h: StAddrAIICircMuC10 is StAddrAIICircMuC10 { export *[ram]:2 StAddrAIICircMuC10; } +StMemAIICircMuC10b: StAddrAIICircMuC10 is StAddrAIICircMuC10 { export *[ram]:1 StAddrAIICircMuC10; } + +# Class-10 Store Memory: Rx++Mu and Rx++Mu:brev - op25 selects mode -- 'cond=1' context must be set by conditional instructions! +StAddrAIMuC10: "("^rx5^"++"^mu^")" is cond=0 & op2527=6 & rx5 & rx5_ & mu { + tmp:4 = rx5 + mu; + ptr:4 = rx5; + export ptr; + <> + rx5 = tmp; +} +StAddrAIMuC10: "("^rx5^"++"^mu^")" is cond=1 & op2527=6 & rx5 & rx5_ & mu { + tmp:4 = rx5 + mu; + ptr:4 = rx5; + export ptr; + <> + if (ConditionReg == 0) goto ; + rx5 = tmp; + +} +StAddrAIMuC10: "("^rx5^"++"^mu^":brev)" is cond=0 & op2527=7 & rx5 & rx5_ & mu { + ptr:4 = (rx5 & 0xffff0000) + bitReverse(rx5 & 0x0ffff); + tmp:4 = rx5 + mu; + export ptr; + <> + rx5 = tmp; +} +StAddrAIMuC10: "("^rx5^"++"^mu^":brev)" is cond=1 & op2527=7 & rx5 & rx5_ & mu { + ptr:4 = (rx5 & 0xffff0000) + bitReverse(rx5 & 0x0ffff); + tmp:4 = rx5 + mu; + export ptr; + <> + if (ConditionReg == 0) goto ; + rx5 = tmp; + +} +StMemAIMuC10d: StAddrAIMuC10 is StAddrAIMuC10 { export *[ram]:8 StAddrAIMuC10; } +StMemAIMuC10w: StAddrAIMuC10 is StAddrAIMuC10 { export *[ram]:4 StAddrAIMuC10; } +StMemAIMuC10h: StAddrAIMuC10 is StAddrAIMuC10 { export *[ram]:2 StAddrAIMuC10; } +StMemAIMuC10b: StAddrAIMuC10 is StAddrAIMuC10 { export *[ram]:1 StAddrAIMuC10; } + + +# +# Left Memory Access +# + +# Left Sp-Relative Memory (Sp+#u5:2) +MemSpRelU5Lw: "("^SP^"+#"^offs^")" is SP & i2024 [ offs = i2024 << 2; ] { + ptr:4 = SP + offs; + export *[ram]:4 ptr; +} + +# Left Sp-Relative Memory (Sp+#u5:3) +MemSpRelU5Ld: "("^SP^"+#"^offs^")" is SP & i1923 [ offs = i1923 << 3; ] { + ptr:4 = SP + offs; + export *[ram]:8 ptr; +} + +# Left Sp-Relative Memory (Sp+#s6:3) +MemSpRelS6Ld: "("^SP^"+#"^offs^")" is SP & s1924 [ offs = s1924 << 3; ] { + ptr:4 = SP + offs; + export *[ram]:8 ptr; +} + + +# Left Rs-Relative Memory (Rs16+#u4:2) +MemRsRelU4Lw: "("^rs4l^")" is rs4l & i2427=0 { + ptr:4 = rs4l; + export *[ram]:4 ptr; +} +MemRsRelU4Lw: "("^rs4l^"+#"^offs^")" is rs4l & i2427 [ offs = i2427 << 2; ] { + ptr:4 = rs4l + offs; + export *[ram]:4 ptr; +} + +# Left Rs-Relative Memory (Rs16+#u4:0) +MemRsRelU4Lb: "("^rs4l^")" is rs4l & i2427=0 { + ptr:4 = rs4l; + export *[ram]:1 ptr; +} +MemRsRelU4Lb: "("^rs4l^"+#"^i2427^")" is rs4l & i2427 { + ptr:4 = rs4l + i2427; + export *[ram]:1 ptr; +} + +# Left Rs-Relative Memory (Rs16+#u3:1) +MemRsRelU3Lh: "("^rs4l^")" is rs4l & i2426=0 { + ptr:4 = rs4l; + export *[ram]:2 ptr; +} +MemRsRelU3Lh: "("^rs4l^"+#"^offs^")" is rs4l & i2426 [ offs = i2426 << 1; ] { + ptr:4 = rs4l + offs; + export *[ram]:2 ptr; +} + +# Left Rs-Relative Memory (Rs16+#u3:0) +MemRsRelU3Lb: "("^rs4l^")" is rs4l & i2426=0 { + ptr:4 = rs4l; + export *[ram]:1 ptr; +} +MemRsRelU3Lb: "("^rs4l^"+#"^i2426^")" is rs4l & i2426 { + ptr:4 = rs4l + i2426; + export *[ram]:1 ptr; +} + +# +# Class-15-Left Memory Access +# + +# Class-15 (LEFT) Store Rs-Relative Memory (Rs16+#u4:2) +StMemRsRelC15Lw: "("^rs4l^")" is rs4l & i1619=0 { + ptr:4 = rs4l; + export *[ram]:4 ptr; +} +StMemRsRelC15Lw: "("^rs4l^"+#"^offs^")" is rs4l & i1619 [ offs = i1619 << 2; ] { + ptr:4 = rs4l + offs; + export *[ram]:4 ptr; +} + +# Class-15 (LEFT) Store Rs-Relative Memory (Rs16+#u4:0) +StMemRsRelC15Lb: "("^rs4l^")" is rs4l & i1619=0 { + ptr:4 = rs4l; + export *[ram]:1 ptr; +} +StMemRsRelC15Lb: "("^rs4l^"+#"^i1619^")" is rs4l & i1619 { + ptr:4 = rs4l + i1619; + export *[ram]:1 ptr; +} + + +# +# Right Memory Access (used with both Load and Store) +# + +# Right Rs-Relative Memory (Rs16+#u4:2) +MemRsRelU4Rw: "("^rs4r^")" is rs4r & i0811=0 { + ptr:4 = rs4r; + export *[ram]:4 ptr; +} +MemRsRelU4Rw: "("^rs4r^"+#"^offs^")" is rs4r & i0811 [ offs = i0811 << 2; ] { + ptr:4 = rs4r + offs; + export *[ram]:4 ptr; +} + +# Right Rs-Relative Memory (Rs16+#u4:0) +MemRsRelU4Rb: "("^rs4r^")" is rs4r & i0811=0 { + ptr:4 = rs4r; + export *[ram]:1 ptr; +} +MemRsRelU4Rb: "("^rs4r^"+#"^i0811^")" is rs4r & i0811 { + ptr:4 = rs4r + i0811; + export *[ram]:1 ptr; +} + +# Right Rs-Relative Memory (Rs16+#u4:0) +MemRsRelU4Rnb: "("^rs4r^")" is rs4r & i0003=0 { + ptr:4 = rs4r; + export *[ram]:1 ptr; +} +MemRsRelU4Rnb: "("^rs4r^"+#"^i0003^")" is rs4r & i0003 { + ptr:4 = rs4r + i0003; + export *[ram]:1 ptr; +} + +# Right Rs-Relative Memory (Rs16+#u3:0) +MemRsRelU3Rb: "("^rs4r^")" is rs4r & i0810=0 { + ptr:4 = rs4r; + export *[ram]:1 ptr; +} +MemRsRelU3Rb: "("^rs4r^"+#"^i0810^")" is rs4r & i0810 { + ptr:4 = rs4r + i0810; + export *[ram]:1 ptr; +} + +# Right Rs-Relative Memory (Rs16+#u3:1) +MemRsRelU3Rh: "("^rs4r^")" is rs4r & i0810=0 { + ptr:4 = rs4r; + export *[ram]:2 ptr; +} +MemRsRelU3Rh: "("^rs4r^"+#"^offs^")" is rs4r & i0810 [ offs = i0810 << 1; ] { + ptr:4 = rs4r + offs; + export *[ram]:2 ptr; +} + +# Right Sp-Relative Memory (Sp+#u5:2) +MemSpRelU5Rw: "("^SP^"+#"^offs^")" is SP & i0408 [ offs = i0408 << 2; ] { + ptr:4 = SP + offs; + export *[ram]:4 ptr; +} + +# Right Sp-Relative Memory (Sp+#u5:3) +MemSpRelU5Rd: "("^SP^"+#"^offs^")" is SP & i0307 [ offs = i0307 << 3; ] { + ptr:4 = SP + offs; + export *[ram]:8 ptr; +} + +# Right Sp-Relative Memory (Sp+#s6:3) +MemSpRelS6Rd: "("^SP^"+#"^offs^")" is SP & s0308 [ offs = s0308 << 3; ] { + ptr:4 = SP + offs; + export *[ram]:8 ptr; +} + + +# +# Class-15-Right Memory Access +# + +# Class-15 (RIGHT) Store Rs-Relative Memory (Rs16+#u4:2) +StMemRsRelC15Rw: "("^rs4r^")" is rs4r & i0003=0 { + ptr:4 = rs4r; + export *[ram]:4 ptr; +} +StMemRsRelC15Rw: "("^rs4r^"+#"^offs^")" is rs4r & i0003 [ offs = i0003 << 2; ] { + ptr:4 = rs4r + offs; + export *[ram]:4 ptr; +} + +# +# ^instruction phases +# + +# Pcode Phases: +# All constructors and subconstructors must support the following named pcode +# phases which are assembled at the end of each packet: +# <> - this phase performs all conditional executions to allow for new predicate use +# <> - this phase performs all unconditional writes +# <> - this phase performs all conditional writes +# <> - this phase performs all conditional and unconditional flows + +# 'parse' bits (PP,EE) decoding (see V2 manual section 10.5 Loop packets for additional detail): +# +# '01' & '10' normal 'PP' instruction +# '11' normal 'PP' instruction when last instruction in packet +# '00' duplex/packed 'EE' instruction (v4, always last instruction in packet) +# + +# reset packetBits if this is first instruction in packet +ResetPacketBits: is packetOffset=0 [ packetBits=0; ] { } +ResetPacketBits: is epsilon { } + +# Phase-0: Update packet offset for next instruction (does not alter packetOffset) +:^instruction is phase=0 & (parse=1 | parse=2) & ResetPacketBits & instruction + [ tmpCtx2 = packetOffset; + packetOffset=packetOffset+1; + globalset(inst_next,packetOffset); + packetOffset = tmpCtx2; + phase = 1; ] { } +:^instruction is phase=0 & (parse=3 | parse=0) & ResetPacketBits & instruction [ +# Rely on default context packetOffset=0 to be used for start of next packet +# tmpCtx2 = packetOffset; +# packetOffset=0; # next instr would start new execute packet (slot-0) +# globalset(inst_next,packetOffset); +# packetOffset = tmpCtx2; + phase=1; ] { } + +# Phase-1: End of H/W Loop packet detection (update parse1 or parse2 context) +# if (start-of-packet) init shadow registers +:^instruction is phase=1 & instruction [ phase = 2; ] { } +:^instruction is phase=1 & packetOffset=1 & parse & instruction [ parse2 = parse; phase = 2; ] { } +:^instruction is phase=1 & packetOffset=0 & parse & instruction [ parse1 = parse; phase = 2; ] +{ + # NOTE: The following execution packet intitialization appears at the start + # of every execute packet. + + # Initilize Auto-AND predicates at start of execute packet. + # We rely on the hexagon compiler to enforce and predicate/auto-AND restrictions. + P0.new = 0xff; + P1.new = 0xff; + P2.new = 0xff; + P3.new = 0xff; + + build instruction; +} + +# Phase-2: Identify instruction parse phase +# 'PP' instructions parsed in Phase-3 +# 'EE' duplex/packed-instructions parsed in Phase-4 +:^instruction is phase=2 & (parse_0=1 | parse_1=1) & instruction [ phase = 3; ] { } +:^instruction is phase=2 & parse=0 & instruction [ phase = 4; ] { } + +# Phase-3: Actual instruction decode for packet-based (PP) instructions +# - instructions may use packetOffset context to obtain adjusted inst_start +# - instructions may alter other packedBits context sub-registers +# +# All packet type instructions (PP) must use the following pattern: +# Note: flow/loop instructions must also manipulate certain context +# +# : EndPacket is & $(END_PACKET) { +# +# build EndPacket; +# } +# +# End of Packet Handling ('PP' instructions only, resumes phase processing via EndPacket +# subconstructors following constructor match) +# - EndPacket subconstructor must be included with all non-packed instructions as +# the last operand and 'build EndPacket' must appear at end of pcode. +# - END_PACKET Can't specify [ ] since this may be specified by instruction +# +@define END_PACKET "phase=3 & EndPacket " + +# Phase-4: Parse Left subinstruction within duplex/packed 'EE' instruction +# This phase relies on instruction constructors to match the first/left-side +# subinstruction. All such instructions must employ the following pattern: +# +# : EndPackedLeft is & $(END_PACKED_LEFT) { +# +# build EndPackedLeft; +# } +# +# Sample: +# +# :assign Rdd3l,Uimm2_2122 EndPackedLeft is iclass3031=1 & iclass28=1 & op2327=0x18 & op1920=0 & Uimm2_2122 & Rdd3l & $(END_PACKED_LEFT) { +# Rdd3l = zext(Uimm2_2122); +# build EndPackedLeft; +# } +# +# - END_PACKET_LEFT Can't specify [ ] since this may be specified by instruction +# +@define END_PACKED_LEFT "phase=4 & EndPackedLeft " + +# Phase-5: Parse Right subinstruction within duplex/packed 'EE' instruction +# This phase relies on instruction constructors to match the second/right-side +# subinstruction. All such instructions must employ the following pattern: +# +# : EndPackedRight is & $(END_PACKED_RIGHT) { +# +# build EndPackedRight; +# } +# +# Sample: +# +# :deallocframe EndPackedRight is op0612=0x7c & op2=0 & $(END_PACKED_RIGHT) { +# deallocframe(); +# build EndPackedRight; +# } +# +# - END_PACKET_RIGHT Can't specify [ ] since this may be specified by instruction +# +@define END_PACKED_RIGHT "phase=5 & EndPackedRight " + +# +PropogateLoopCfg: is useLoopCfg=1 [ globalset(inst_next,useLoopCfg); ] { } +PropogateLoopCfg: is useLoopCfg=0 { } + +# Check for pipelined loop count and inject pcode if needed +CheckLpcfg: is useLoopCfg=0 { } +CheckLpcfg: is useLoopCfg=1 [ useLoopCfg=0; ] { + lpcfg:1 = $(LPCFG); + if (lpcfg == 0) goto ; + lpcfg = lpcfg - 1; + $(LPCFG) = lpcfg; + P3 = (lpcfg == 0); # set P3 once pipeline count (1-3) has lapsed + # NOTE: may be incorrect to clear P3 if not done yet + +} + +# EndPacket: End of HW Loop handling (uses parse1 and parse2) + +EndOfLoop: is PropogateLoopCfg { } # not end-of-loop - propogate useLoopCfg if active +EndOfLoop: " :endloop0" is parse1=2 & CheckLpcfg { # Last in HW Loop 0 + # :endloop0 - TODO: not sure how to display + build CheckLpcfg; + if (LC0 <= 1) goto inst_next; + LC0 = LC0 - 1; + goto [SA0]; +} +EndOfLoop: " :endloop1" is parse1=1 & parse2=2 & PropogateLoopCfg { # Last in HW Loop 1 - propogate useLoopCfg if active + # :endloop1 - TODO: not sure how to display + if (LC1 <= 1) goto inst_next; + LC1 = LC1 - 1; + goto [SA1]; +} +EndOfLoop: " :endloop0 :endloop1" is parse1=2 & parse2=2 & CheckLpcfg { # Last in HW Loop 0 & 1 + # :endloop0:endloop1 - TODO: not sure how to display + build CheckLpcfg; + if (LC0 <= 1) goto inst_next; + LC0 = LC0 - 1; + goto [SA0]; + if (LC1 <= 1) goto inst_next; + LC1 = LC1 - 1; + goto [SA1]; +} + +# CrossBuild: +# - include <> <> and <> pcode for all instructions in packet + +CrossBuildAddr0: loc is epsilon [ loc = inst_start; ] { export *:4 loc; } +CrossBuildAddr1: loc is epsilon [ loc = inst_start - 4; ] { export *:4 loc; } +CrossBuildAddr2: loc is epsilon [ loc = inst_start - 8; ] { export *:4 loc; } +CrossBuildAddr3: loc is epsilon [ loc = inst_start - 12; ] { export *:4 loc; } + +CrossBuild: is packetOffset=0 & CrossBuildAddr0 [ phase=8; ] { + crossbuild CrossBuildAddr0,EXEC_COND; + crossbuild CrossBuildAddr0,COMMIT; + crossbuild CrossBuildAddr0,COMMIT_COND; + ReturnAddr = inst_next; + crossbuild CrossBuildAddr0,FLOW; +} +CrossBuild: is packetOffset=1 & CrossBuildAddr0 & CrossBuildAddr1 [ phase=8; ] { + crossbuild CrossBuildAddr1,EXEC_COND; + crossbuild CrossBuildAddr0,EXEC_COND; + crossbuild CrossBuildAddr1,COMMIT; + crossbuild CrossBuildAddr0,COMMIT; + crossbuild CrossBuildAddr1,COMMIT_COND; + crossbuild CrossBuildAddr0,COMMIT_COND; + ReturnAddr = inst_next; + crossbuild CrossBuildAddr1,FLOW; + crossbuild CrossBuildAddr0,FLOW; +} +CrossBuild: is packetOffset=2 & CrossBuildAddr0 & CrossBuildAddr1 & CrossBuildAddr2 [ phase=8; ] { + crossbuild CrossBuildAddr2,EXEC_COND; + crossbuild CrossBuildAddr1,EXEC_COND; + crossbuild CrossBuildAddr0,EXEC_COND; + crossbuild CrossBuildAddr2,COMMIT; + crossbuild CrossBuildAddr1,COMMIT; + crossbuild CrossBuildAddr0,COMMIT; + crossbuild CrossBuildAddr2,COMMIT_COND; + crossbuild CrossBuildAddr1,COMMIT_COND; + crossbuild CrossBuildAddr0,COMMIT_COND; + ReturnAddr = inst_next; + crossbuild CrossBuildAddr2,FLOW; + crossbuild CrossBuildAddr1,FLOW; + crossbuild CrossBuildAddr0,FLOW; +} +CrossBuild: is packetOffset=3 & CrossBuildAddr0 & CrossBuildAddr1 & CrossBuildAddr2 & CrossBuildAddr3 [ phase=8; ] { + crossbuild CrossBuildAddr3,EXEC_COND; + crossbuild CrossBuildAddr2,EXEC_COND; + crossbuild CrossBuildAddr1,EXEC_COND; + crossbuild CrossBuildAddr0,EXEC_COND; + crossbuild CrossBuildAddr3,COMMIT; + crossbuild CrossBuildAddr2,COMMIT; + crossbuild CrossBuildAddr1,COMMIT; + crossbuild CrossBuildAddr0,COMMIT; + crossbuild CrossBuildAddr3,COMMIT_COND; + crossbuild CrossBuildAddr2,COMMIT_COND; + crossbuild CrossBuildAddr1,COMMIT_COND; + crossbuild CrossBuildAddr0,COMMIT_COND; + ReturnAddr = inst_next; + crossbuild CrossBuildAddr3,FLOW; + crossbuild CrossBuildAddr2,FLOW; + crossbuild CrossBuildAddr1,FLOW; + crossbuild CrossBuildAddr0,FLOW; +} + +# End of Packet pcode +# - if NOT end-of-packet propogate packet context bits and skip further checks +# - if end-of-packet include CrossBuild and EndOfLoop pcode +EndPacket: is (parse=1 | parse=2) & PropogateLoopCfg [ globalset(inst_next,packetBits); ] { } # this is not end-of-packet - propogate packetBits and useLoopCfg if needed +EndPacket: EndOfLoop is (parse=0 | parse=3) & CrossBuild & EndOfLoop { # EndOfLoop will propogate useLoopCfg if needed + build CrossBuild; + build EndOfLoop; +} + +# End of First/Left packed 'EE' instruction helper +EndPackedLeft: "; "^instruction is instruction [ phase = 5; ] { build instruction; } + +# End of Second/Left packed 'EE' instruction helper +EndPackedRight: is EndPacket [ phase = 6; ] { build EndPacket; } # resume EndPacket processing + + +# +# MACROS +# + +# +# frame layout +# +# +-----------+ +# | | <- SP.new +# | local | +# | | +# | | +# +-----------+ +# | saved FP | <- FP.new +# +-----------+ +# | saved LR | +# +-----------+ +# | | (initial SP) +# + +# NOTE: allocframe and dealloc_frame macro should be invoked from the +# <>, <> or <> pcode section only + +macro deallocframe(reg) { + ptr:4 = reg; + FP = *[ram]:4 ptr; + ptr = ptr + 4; + LR = (*[ram]:4 ptr) ^ FRAMEKEY; + SP = ptr + 4; +} + +macro allocframe(reg,sze) { + ptr:4 = reg - 4; + *[ram]:4 ptr = (LR ^ FRAMEKEY); + ptr = ptr - 4; + *[ram]:4 ptr = FP; + FP = ptr; + reg = ptr - zext(sze); +} + +# +# INSTRUCTIONS +# +# Pattern convention: +# '-' indicates don't-care bit (bit should not be constrained) +# '+' indicates don't care bit (bit should be constrained as '0') +# + + +# (v2,8) abs -- "Rd32 = abs ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 1 0 0 1 0 0 s s s s s P P + + + + + + 1 0 0 d d d d d + +:abs Rd5,rs5 EndPacket is iclass=8 & op2127=0x64 & op0513=0x04 & Rd5 & rs5 & $(END_PACKET) { + neg:1 = (rs5 s< 0); + Rd5 = (zext(neg) * -rs5) + (zext(!neg) * rs5); + build EndPacket; +} + +# (v2,8) abs -- "Rd32 = abs ( Rs32 ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 1 0 0 1 0 0 s s s s s P P + + + + + + 1 0 1 d d d d d + +define pcodeop absSat; + +:abs":sat" Rd5,rs5 EndPacket is iclass=8 & op2127=0x64 & op0513=0x05 & Rd5 & rs5 & $(END_PACKET) { + + pos:1 = (rs5 s>= 0); + toobig:1 = (rs5 == 0x80000000); # Only one saturation case + Rd5 = (zext(pos) * rs5) + (zext(!pos) * ((zext(toobig) * 0x7fffffff) + (zext(!toobig) * -rs5))); + build EndPacket; + <> + $(OVF) = $(OVF) | toobig; +} + +# (v2,8) abs -- "Rdd32 = abs ( Rss32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 0 0 0 1 0 + s s s s s P P + + + + + + 1 1 0 d d d d d + +:abs Rdd5,rss5 EndPacket is iclass=0x8 & op2127=0x04 & op0513=0x06 & Rdd5 & rss5 & $(END_PACKET) +{ + neg:1 = (rss5 s< 0); + Rdd5 = (zext(neg) * -rss5) + (zext(!neg) * rss5); + build EndPacket; +} + +# (v2,11) add -- "Rd32 = add ( Rs32 , #s16x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 1 i i i i i i i s s s s s P P i i i i i i i i i d d d d d + +:add Rd5,rs5,Simm32_2127_0513x EndPacket is iclass=0xb & Rd5 & rs5 & Simm32_2127_0513x & $(END_PACKET) { + Rd5 = rs5 + Simm32_2127_0513x; + build EndPacket; +} + +# (v2,15) add -- "Rd32 = add ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 1 0 0 1 1 0 0 0 s s s s s P P + t t t t t + + + d d d d d + +:add Rd5,rs5,rt5 EndPacket is iclass=0xf & op2127=0x18 & op13=0 & op0507=0 & Rd5 & rs5 & rt5 & $(END_PACKET) { + Rd5 = rs5 + rt5; + build EndPacket; +} + +# (v4,15) add -- "Rd32 = add ( Rs32 , Rt32 ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 1 0 1 1 0 0 1 0 s s s s s P P + t t t t t + + + d d d d d + +:add^":sat" Rd5,rs5,rt5 EndPacket is iclass=0xf & op2127=0x32 & rs5 & op13=0 & rt5 & op0507=0x0 & Rd5 & $(END_PACKET) +{ + sat:1 = scarry(rs5, rt5); + addSat32(Rd5, rs5, rt5); + build EndPacket; + <> + $(OVF) = $(OVF) | sat; +} + +# (v2,13) add -- "Rd32 = add ( Rs32 , Rt32 ) :sat :deprecated" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 1 0 1 1 0 0 s s s s s P P + t t t t t 0 + + d d d d d + +:add^":sat:deprecated" Rd5,rs5,rt5 EndPacket is iclass=0xd & op2127=0x2c & rs5 & op13=0 & rt5 & op0507=0x0 & Rd5 & $(END_PACKET) +{ + sat:1 = scarry(rs5, rt5); + addSat32(Rd5, rs5, rt5); + build EndPacket; + <> + $(OVF) = $(OVF) | sat; +} + +# (v4,13) add -- "Rd32 = add ( Rs32 , add ( Ru32 , #s6x ) )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 1 0 1 1 0 i i s s s s s P P i d d d d d i i i u u u u u +# +# (v4,13) add -- "Rd32 = add ( Rs32 , sub ( #s6x , Ru32 ) )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 1 0 1 1 1 i i s s s s s P P i d d d d d i i i u u u u u + +AddSubOp23: "add("ru5,Simm32_2122_13_0507x")" is op23=0 & ru5 & Simm32_2122_13_0507x { + tmp:4 = ru5 + Simm32_2122_13_0507x; + export tmp; +} +AddSubOp23: "sub("Simm32_2122_13_0507x,ru5")" is op23=1 & ru5 & Simm32_2122_13_0507x { + tmp:4 = Simm32_2122_13_0507x - ru5; + export tmp; +} + +:add Rd0812,rs5,AddSubOp23 EndPacket is iclass=13 & op2427=11 & Rd0812 & rs5 & AddSubOp23 & $(END_PACKET) { + Rd0812 = rs5 + AddSubOp23; + build EndPacket; +} + +# (v4,13) add -- "Rd32 = add ( Ru32 , mpyi ( #u6:2 , Rs32 ) )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 1 1 1 1 0 i i s s s s s P P i d d d d d i i i u u u u u +# +# (v4,13) add -- "Rd32 = add ( Ru32 , mpyi ( Rs32 , #u6x ) )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 1 1 1 1 1 i i s s s s s P P i d d d d d i i i u u u u u + +MpyiOp23: "mpyi("Uimm32_2122_13_0507_shift2,rs5")" is op23=0 & rs5 & Uimm32_2122_13_0507_shift2 { + tmp:4 = rs5 * Uimm32_2122_13_0507_shift2; + export tmp; +} +MpyiOp23: "mpyi("Uimm32_2122_13_0507x,rs5")" is op23=1 & rs5 & Uimm32_2122_13_0507x { + tmp:4 = rs5 * Uimm32_2122_13_0507x; + export tmp; +} + +:add Rd0812,ru5,MpyiOp23 EndPacket is iclass=13 & op2427=15 & Rd0812 & ru5 & MpyiOp23 & $(END_PACKET) { + Rd0812 = ru5 + MpyiOp23; + build EndPacket; +} + +# (v4,13) add -- "Rd32 = add ( #u6x , mpyi ( Rs32 , #U6 ) )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 1 0 0 0 I i i s s s s s P P i d d d d d i i i I I I I I + +MpyiRs32U6: "mpyi("rs5,Uimm8_23_0004")" is rs5 & Uimm8_23_0004 { + tmp:4 = rs5 * zext(Uimm8_23_0004); + export tmp; +} + +:add Rd0812,Uimm32_2122_13_0507x,MpyiRs32U6 EndPacket is iclass=13 & op2427=8 & Rd0812 & Uimm32_2122_13_0507x & MpyiRs32U6 & $(END_PACKET) { + Rd0812 = Uimm32_2122_13_0507x + MpyiRs32U6; + build EndPacket; +} + +# (v4,13) add -- "Rd32 = add ( #u6x , mpyi ( Rs32 , Rt32 ) )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 1 1 1 0 i i s s s s s P P i t t t t t i i i d d d d d + +MpyiRs32Rt32: "mpyi("rs5,rt5")" is rs5 & rt5 { + tmp:4 = rs5 * rt5; + export tmp; +} + +:add Rd5,Uimm32_2122_13_0507x,MpyiRs32Rt32 EndPacket is iclass=13 & op2327=0x0e & Rd5 & Uimm32_2122_13_0507x & MpyiRs32Rt32 & $(END_PACKET) { + Rd5 = Uimm32_2122_13_0507x + MpyiRs32Rt32; + build EndPacket; +} + +# (v2,13) add -- "Rd32 = add ( Rt32.l , Rs32.h )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 1 0 1 0 0 0 s s s s s P P + t t t t t 0 1 + d d d d d +# +# (v2,13) add -- "Rd32 = add ( Rt32.l , Rs32.l )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 1 0 1 0 0 0 s s s s s P P + t t t t t 0 0 + d d d d d + +:add Rd5,rt5L,Rs5HL06 EndPacket is iclass=0xd & op2127=0x28 & op13=0 & op7=0 & op5=0 & rt5L & Rs5HL06 & Rd5 & $(END_PACKET) +{ + Rd5 = sext(rt5L + Rs5HL06); + build EndPacket; +} + +# (v2,13) add -- "Rd32 = add ( Rt32.h , Rs32.h ) :<<16" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 1 0 1 0 1 0 s s s s s P P + t t t t t 0 1 1 d d d d d +# +# (v2,13) add -- "Rd32 = add ( Rt32.h , Rs32.l ) :<<16" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 1 0 1 0 1 0 s s s s s P P + t t t t t 0 1 0 d d d d d +# +# (v2,13) add -- "Rd32 = add ( Rt32.l , Rs32.h ) :<<16" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 1 0 1 0 1 0 s s s s s P P + t t t t t 0 0 1 d d d d d +# +# (v2,13) add -- "Rd32 = add ( Rt32.l , Rs32.l ) :<<16" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 1 0 1 0 1 0 s s s s s P P + t t t t t 0 0 0 d d d d d + +:add^":<<16" Rd5,Rt5HL06,Rs5HL05 EndPacket is iclass=0xd & op2127=0x2a & op13=0 & op7=0 & Rs5HL05 & Rt5HL06 & Rd5 & $(END_PACKET) +{ + Rd5 = zext(Rs5HL05 + Rt5HL06) << 16; + build EndPacket; +} + +# (v2,13) add -- "Rd32 = add ( Rt32.h , Rs32.h ) :sat :<<16" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 1 0 1 0 1 0 s s s s s P P + t t t t t 1 1 1 d d d d d +# +# (v2,13) add -- "Rd32 = add ( Rt32.h , Rs32.l ) :sat :<<16" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 1 0 1 0 1 0 s s s s s P P + t t t t t 1 1 0 d d d d d +# +# (v2,13) add -- "Rd32 = add ( Rt32.l , Rs32.h ) :sat :<<16" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 1 0 1 0 1 0 s s s s s P P + t t t t t 1 0 1 d d d d d +# +# (v2,13) add -- "Rd32 = add ( Rt32.l , Rs32.l ) :sat :<<16" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 1 0 1 0 1 0 s s s s s P P + t t t t t 1 0 0 d d d d d + +:add^":sat:<<16" Rd5,Rt5HL06,Rs5HL05 EndPacket is iclass=0xd & op2127=0x2a & op13=0 & op7=1 & Rs5HL05 & Rt5HL06 & Rd5 & $(END_PACKET) +{ + temp:2 = 0; + addSat16(temp, Rs5HL05, Rt5HL06); + Rd5 = zext(temp) << 16; + sat:1 = scarry(Rt5HL06, Rs5HL05); + build EndPacket; + <> + $(OVF) = $(OVF) | sat; +} + +# (v2,13) add -- "Rd32 = add ( Rt32.l , Rs32.h ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 1 0 1 0 0 0 s s s s s P P + t t t t t 1 1 + d d d d d +# +# (v2,13) add -- "Rd32 = add ( Rt32.l , Rs32.l ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 1 0 1 0 0 0 s s s s s P P + t t t t t 1 0 + d d d d d + +:add^":sat" Rd5,rt5L,Rs5HL06 EndPacket is iclass=0xd & op2127=0x28 & op13=0 & op7=1 & op5=0 & Rs5HL06 & rt5L & Rd5 & $(END_PACKET) +{ + temp:2 = 0; + addSat16(temp, Rs5HL06, rt5L); + Rd5 = zext(temp); + sat:1 = scarry(Rs5HL06, rt5L); + build EndPacket; + <> + $(OVF) = $(OVF) | sat; +} + +# (v4,8) add -- "Rd32 = add ( clb ( Rs32 ) , #s6 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 1 0 0 0 0 1 s s s s s P P i i i i i i 0 0 0 d d d d d + +ClbRs: "clb("^rs5")" is rs5 { cnt:4 = countLeadingBits(rs5); export cnt; } + +:add Rd5,ClbRs,Simm8_0813 EndPacket is iclass=8 & op2127=0x61 & op0507=0 & Rd5 & ClbRs & Simm8_0813 & $(END_PACKET) +{ + Rd5 = ClbRs + sext(Simm8_0813); + build EndPacket; +} + +# (v4,8) add -- "Rd32 = add ( clb ( Rss32 ) , #s6 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 0 0 0 0 1 1 s s s s s P P i i i i i i 0 1 + d d d d d + +ClbRss: "clb("^rss5")" is rss5 { cnt:4 = countLeadingBits(rss5); export cnt; } + +:add Rd5,ClbRss,Simm8_0813 EndPacket is iclass=8 & op2127=0x43 & op0507=2 & Rd5 & ClbRss & Simm8_0813 & $(END_PACKET) +{ + Rd5 = ClbRss + sext(Simm8_0813); + build EndPacket; +} + +# (v4,6) add -- "Rd32 = add ( pc , #u6x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 1 0 1 0 0 1 0 0 1 0 0 1 P P + i i i i i i + + d d d d d + +:assign Rd5,PacketPC EndPacket is iclass=6 & op2127=0x52 & op1620=0x9 & op13=0 & op0506=0 & i0712=0 & immext=0 & Rd5 & PacketPC & $(END_PACKET) +{ + Rd5 = PacketPC; + build EndPacket; +} + +:add Rd5,PacketPC,Uimm32_0712x EndPacket is iclass=6 & op2127=0x52 & op1620=0x9 & op13=0 & op0506=0 & Rd5 & PacketPC & Uimm32_0712x & $(END_PACKET) +{ + Rd5 = PacketPC + Uimm32_0712x; + build EndPacket; +} + +# (v2,13) add -- "Rdd32 = add ( Rss32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 1 0 0 0 s s s s s P P + t t t t t 1 1 1 d d d d d + +:add Rdd5,rss5,rtt5 EndPacket is iclass=0xd & op2127=0x18 & rss5 & op13=0 & rtt5 & op0507=0x7 & Rdd5 & $(END_PACKET) +{ + Rdd5 = rss5 + rtt5; + build EndPacket; +} + +# (v4,13) add -- "Rdd32 = add ( Rss32 , Rtt32 ) :raw :hi" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 1 0 1 1 s s s s s P P + t t t t t 1 1 1 d d d d d + +define pcodeop addRawHi; + +:add":raw:hi" Rdd5,rss5,rtt5 EndPacket is iclass=0xd & op2127=0x1b & rss5 & op13=0 & rtt5 & op0507=0x7 & Rdd5 & $(END_PACKET) +{ + Rdd5 = rtt5 + sext(rss5[32,32]); + build EndPacket; +} + +# (v4,13) add -- "Rdd32 = add ( Rss32 , Rtt32 ) :raw :lo" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 1 0 1 1 s s s s s P P + t t t t t 1 1 0 d d d d d + +define pcodeop addRawLo; + +:add":raw:lo" Rdd5,rss5,rtt5 EndPacket is iclass=0xd & op2127=0x1b & rss5 & op13=0 & rtt5 & op0507=0x6 & Rdd5 & $(END_PACKET) +{ + Rdd5 = rtt5 + sext(rss5[0,32]); + build EndPacket; +} + +# (v4,13) add -- "Rdd32 = add ( Rss32 , Rtt32 ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 1 0 1 1 s s s s s P P + t t t t t 1 0 1 d d d d d + +define pcodeop addSat; + +:add":sat" Rdd5,rss5,rtt5 EndPacket is iclass=0xd & op2127=0x1b & rss5 & op13=0 & rtt5 & op0507=0x5 & Rdd5 & $(END_PACKET) +{ + Rdd5 = addSat(rss5, rtt5); + build EndPacket; +} + +# (v4,12) add -- "Rdd32 = add ( Rss32 , Rtt32 , Px4 ) :carry" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 0 1 0 1 1 0 s s s s s P P + t t t t t + x x d d d d d + +:add":carry" Rdd5,rss5,rtt5,pu0506 EndPacket is iclass=0xc & op2127=0x16 & rss5 & op13=0 & rtt5 & op7=0 & Rdd5 & pu0506 & pu0506_ & $(END_PACKET) +unimpl + +# (v2,14) add -- "Rx32 += add ( Rs32 , #s8x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 0 1 0 0 + + s s s s s P P + i i i i i i i i x x x x x + +:add+= Rd5,rs5,Simm32_0512x EndPacket is iclass=0xe & op2127=0x10 & rs5 & op13=0 & Simm32_0512x & rd5 & Rd5 & $(END_PACKET) +{ + Rd5 = rd5 + rs5 + Simm32_0512x; + build EndPacket; +} + +# (v2,14) add -- "Rx32 += add ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 1 0 0 0 s s s s s P P + t t t t t + 0 1 x x x x x + +:add+= Rd5,rs5,rt5 EndPacket is iclass=0xe & op2127=0x78 & rs5 & op13=0 & op0507=0x1 & rt5 & rd5 & Rd5 & $(END_PACKET) +{ + Rd5 = rd5 + rs5 + rt5; + build EndPacket; +} + +# (v2,14) add -- "Rx32 -= add ( Rs32 , #s8x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 0 1 0 1 + + s s s s s P P + i i i i i i i i x x x x x + +:add-= Rd5,rs5,Simm32_0512x EndPacket is iclass=0xe & op2127=0x14 & op13=0 & rs5 & Simm32_0512x & rd5 & Rd5 & $(END_PACKET) +{ + Rd5 = rd5 - rs5 + Simm32_0512x; + build EndPacket; +} + +# (v2,14) add -- "Rx32 -= add ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 1 1 0 0 s s s s s P P + t t t t t + 0 1 x x x x x + +:add-= Rd5,rs5,rt5 EndPacket is iclass=0xe & op2127=0x7c & rs5 & op13=0 & rt5 & op0507=0x1 & rd5 & Rd5 & $(END_PACKET) +{ + Rd5 = rd5 - ( rs5 + rt5 ); + build EndPacket; +} + +# (v4,13) add -- "Rx32 = add ( #u8x , asl ( Rx32 , #U5 ) )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 1 1 1 0 i i i x x x x x P P i I I I I I i i i 0 i 1 0 + +# +# (v4,13) add -- "Rx32 = add ( #u8x , lsr ( Rx32 , #U5 ) )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 1 1 1 0 i i i x x x x x P P i I I I I I i i i 1 i 1 0 + + +:add Rx5,Uimm32_2123_13_0507_03x,ShiftRx_D04_I0812 EndPacket is iclass=13 & op2427=14 & op0002=4 & Uimm32_2123_13_0507_03x & ShiftRx_D04_I0812 & Rx5 & $(END_PACKET) +{ + Rx5 = Uimm32_2123_13_0507_03x + ShiftRx_D04_I0812; + build EndPacket; +} + +# (v4,14) add -- "Rx32 = add ( Ru32 , mpyi ( Rx32 , Rs32 ) )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 0 1 1 0 0 0 s s s s s P P + x x x x x + + + u u u u u + +MpyiRx32Rs32: "mpyi("rt5,rs5")" is rs5 & rt5 { + tmp:4 = rs5 * rt5; + export tmp; +} + +:add Rd0812,ru5,MpyiRx32Rs32 EndPacket is iclass=14 & op2127=0x18 & op13=0 & op0507=0 & Rd0812 & MpyiRx32Rs32 & ru5 & $(END_PACKET) +{ + Rd0812 = ru5 + MpyiRx32Rs32; + build EndPacket; +} + +# (v2,7) add -- "if ( Pu4 ) Rd32 = add ( Rs32 , #s8x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 1 0 1 0 0 0 u u s s s s s P P 0 i i i i i i i i d d d d d +# +# (v2,7) add -- "if ( ! Pu4 ) Rd32 = add ( Rs32 , #s8x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 1 0 1 0 0 1 u u s s s s s P P 0 i i i i i i i i d d d d d +# +# (v2,7) add -- "if ( Pu4 .new ) Rd32 = add ( Rs32 , #s8x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 1 0 1 0 0 0 u u s s s s s P P 1 i i i i i i i i d d d d d +# +# (v2,7) add -- "if ( ! Pu4 .new ) Rd32 = add ( Rs32 , #s8x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 1 0 1 0 0 1 u u s s s s s P P 1 i i i i i i i i d d d d d + +:add^PuCond2122_N13_S23 rd5,rs5,Simm32_0512x EndPacket is iclass=7 & op2427=4 & PuCond2122_N13_S23 & rs5 & Simm32_0512x & rd5 & rd5_ & SetNRegRd5 & $(END_PACKET) { + build PuCond2122_N13_S23; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + rd5_ = rs5 + Simm32_0512x; + + <> + if (ConditionReg == 0) goto ; + rd5 = rd5_; + +} + +# if ([!]Pu4[.new]) Rd32 = Rs32 ( simplification of if ([!]Pu4[.new]) Rd32 = add(Rs32,#0) +:assign^PuCond2122_N13_S23 rd5,rs5 EndPacket is iclass=7 & op2427=4 & PuCond2122_N13_S23 & rs5 & op0512=0 & immexted=0 & rd5 & rd5_ & SetNRegRd5 & $(END_PACKET) { + build PuCond2122_N13_S23; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + rd5_ = rs5; + + <> + if (ConditionReg == 0) goto ; + rd5 = rd5_; + +} + +# (v2,15) add -- "if ( Pu4 ) Rd32 = add ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 1 1 0 1 1 0 - 0 s s s s s P P 0 t t t t t 0 u u d d d d d +# +# (v2,15) add -- "if ( ! Pu4 ) Rd32 = add ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 1 1 0 1 1 0 - 0 s s s s s P P 0 t t t t t 1 u u d d d d d +# +# (v2,15) add -- "if ( Pu4 .new ) Rd32 = add ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 1 1 0 1 1 0 - 0 s s s s s P P 1 t t t t t 0 u u d d d d d +# +# (v2,15) add -- "if ( ! Pu4 .new ) Rd32 = add ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 1 1 0 1 1 0 - 0 s s s s s P P 1 t t t t t 1 u u d d d d d + +:add^PuCond0506_N13_S07 rd5,rs5,rt5 EndPacket is iclass=15 & op2327=0x16 & op22=0 & op21=0 & PuCond0506_N13_S07 & rs5 & rt5 & rd5 & rd5_ & SetNRegRd5 & $(END_PACKET) { + build PuCond0506_N13_S07; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + rd5_ = rs5 + rt5; + + <> + if (ConditionReg == 0) goto ; + rd5 = rd5_; + +} + +# (v2,12) addasl -- "Rd32 = addasl ( Rt32 , Rs32 , #u3 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 1 0 0 0 0 0 s s s s s P P 0 t t t t t i i i d d d d d + +:addasl Rd5,rt5,rs5,Uimm3_0507 EndPacket is iclass=12 & op2127=0x20 & op13=0 & Rd5 & rt5 & rs5 & Uimm3_0507 & $(END_PACKET) +{ + Rd5 = rt5 + (rs5 << Uimm3_0507); + build EndPacket; +} + +# (v2,6) all8 -- "Pd4 = all8 ( Ps4 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 1 0 1 1 1 0 1 0 - - s s P P 0 - - - - - - - - - - - d d + +:all8 Pd2,pu1617 EndPacket is iclass=6 & op2127=0x5d & op1820=0 & op0213=0 & pu1617 & Pd2 & $(END_PACKET) { + Pd2 = Pd2 & ((pu1617 == 0xff) * 0xff); + build EndPacket; +} + +# (v2,10) allocframe -- "allocframe ( #u11:3 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 0 0 0 0 1 0 0 1 1 1 0 1 P P 0 0 0 i i i i i i i i i i i + +:allocframe Uimm16_0010_shift3 EndPacket is iclass=10 & op2527=0 & op2224=2 & op21=0 & op1620=0x1d & op1113=0 & Uimm16_0010_shift3 & $(END_PACKET) { + allocframe(SP, Uimm16_0010_shift3); + build EndPacket; +} + +# (v2,10) allocframe -- "allocframe ( Rx32, #u11:3 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 0 0 0 0 1 0 0 x x x x x P P 0 0 0 i i i i i i i i i i i + +:allocframe rx5, Uimm16_0010_shift3 EndPacket is iclass=10 & op2527=0 & op2224=2 & op21=0 & rx5 & op1113=0 & Uimm16_0010_shift3 & $(END_PACKET) { + allocframe(rx5, Uimm16_0010_shift3); + build EndPacket; +} + +# (v4,6) and -- "Pd4 = and ( Ps4 , and ( Pt4 , Pu4 ) )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 1 0 1 1 0 0 0 1 + + s s P P 0 - - - t t u u - - - - d d +# +# (v4,6) and -- "Pd4 = and ( Ps4 , and ( Pt4 , ! Pu4 ) )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 1 0 1 1 1 0 0 1 + + s s P P 0 - - - t t u u - - - - d d +# +# (v4,6) and -- "Pd4 = and ( Ps4 , or ( Pt4 , Pu4 ) )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 1 0 1 1 0 0 1 1 + + s s P P 0 - - - t t u u - - - - d d +# +# (v4,6) and -- "Pd4 = and ( Ps4 , or ( Pt4 , ! Pu4 ) )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 1 0 1 1 1 0 1 1 + + s s P P 0 - - - t t u u - - - - d d + +:and Pd2,pu1617,PredLogic_L21_S23_P0809_P0607 EndPacket is iclass=6 & op2427=0xb & op22=0 & op1820=4 & pu1617 & Pd2 & PredLogic_L21_S23_P0809_P0607 & $(END_PACKET) { + Pd2 = Pd2 & (pu1617 & PredLogic_L21_S23_P0809_P0607); + build EndPacket; +} + +# (v2,6) and -- "Pd4 = and ( Pt4 , Ps4 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 1 0 1 1 0 0 0 0 - - s s P P 0 - - - t t - - - - - - d d + +:and Pd2,pu0809,pu1617 EndPacket is iclass=6 & op2127=0x58 & op1820=0 & op1013=0 & op0207=0 & pu0809 & pu1617 & Pd2 & $(END_PACKET) { + Pd2 = Pd2 & (pu1617 & pu0809); + build EndPacket; +} + +# (v2,6) and -- "Pd4 = and ( Pt4 , ! Ps4 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 1 0 1 1 0 1 1 0 - - s s P P 0 - - - t t - - - - - - d d + +:and Pd2,pu0809,NotPs2 EndPacket is iclass=6 & op2127=0x5b & op1820=0 & op1013=0 & op0207=0 & pu0809 & NotPs2 & Pd2 & $(END_PACKET) { + Pd2 = Pd2 & (NotPs2 & pu0809); + build EndPacket; +} + +# (v2,7) and -- "Rd32 = and ( Rs32 , #s10x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 1 0 1 1 0 0 0 i s s s s s P P i i i i i i i i i d d d d d + +:and Rd5,rs5,Simm32_21_0513x EndPacket is iclass=7 & op2227=0x18 & Rd5 & rs5 & Simm32_21_0513x & $(END_PACKET) { + Rd5 = rs5 & Simm32_21_0513x; + build EndPacket; +} + +# (v2,15) and -- "Rd32 = and ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 1 0 0 0 1 0 0 0 s s s s s P P - t t t t t - - - d d d d d + +:and Rd5,rs5,rt5 EndPacket is iclass=15 & op2127=0x08 & Rd5 & rs5 & rt5 & $(END_PACKET) { + Rd5 = rs5 & rt5; + build EndPacket; +} + +# (v4,15) and -- "Rd32 = and ( Rt32 , ~ Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 1 0 0 0 1 1 0 0 s s s s s P P - t t t t t - - - d d d d d + +:and Rd5,rt5,OnesCompRs5 EndPacket is iclass=15 & op2127=0x0c & Rd5 & OnesCompRs5 & rt5 & $(END_PACKET) { + Rd5 = rt5 & OnesCompRs5; + build EndPacket; +} + +# (v2,13) and -- "Rdd32 = and ( Rss32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 1 1 1 1 s s s s s P P - t t t t t 0 0 0 d d d d d + +:and Rdd5,rss5,rtt5 EndPacket is iclass=13 & op2127=0x1f & op0507=0 & Rdd5 & rss5 & rtt5 & $(END_PACKET) { + Rdd5 = rss5 & rtt5; + build EndPacket; +} + +# (v4,13) and -- "Rdd32 = and ( Rtt32 , ~ Rss32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 1 1 1 1 s s s s s P P - t t t t t 0 0 1 d d d d d + +:and Rdd5,rtt5,OnesCompRss5 EndPacket is iclass=13 & op2127=0x1f & op0507=1 & Rdd5 & OnesCompRss5 & rtt5 & $(END_PACKET) { + Rdd5 = rtt5 & OnesCompRss5; + build EndPacket; +} + +# (v4,14) and -- "Rx32 &= and ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 1 0 1 0 s s s s s P P + t t t t t + 0 0 x x x x x + +:and&= Rd5,rs5,rt5 EndPacket is iclass=0xe & op2127=0x7a & op13=0 & op0507=0 & rs5 & rt5 & rd5 & Rd5 & $(END_PACKET) +{ + Rd5 = rd5 & rs5 & rt5; + build EndPacket; +} + +# (v4,14) and -- "Rx32 &= and ( Rs32 , ~ Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 1 0 0 1 s s s s s P P + t t t t t + 0 1 x x x x x + +:and&= Rd5,rs5,OnesCompRt5 EndPacket is iclass=0xe & op2127=0x79 & op13=0 & op0507=1 & rs5 & OnesCompRt5 & rd5 & Rd5 & $(END_PACKET) +{ + Rd5 = rd5 & rs5 & OnesCompRt5; + build EndPacket; +} + +# (v4,13) and -- "Rx32 = and ( #u8x , asl ( Rx32 , #U5 ) )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 1 1 1 0 i i i x x x x x P P i I I I I I i i i 0 i 0 0 - +# +# (v4,13) and -- "Rx32 = and ( #u8x , lsr ( Rx32 , #U5 ) )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 1 1 1 0 i i i x x x x x P P i I I I I I i i i 1 i 0 0 + + +:and Rx5,Uimm32_2123_13_0507_03x,ShiftRx_D04_I0812 EndPacket is iclass=13 & op2427=14 & op0002=0 & Uimm32_2123_13_0507_03x & ShiftRx_D04_I0812 & Rx5 & $(END_PACKET) +{ + Rx5 = Uimm32_2123_13_0507_03x & ShiftRx_D04_I0812; + build EndPacket; +} + +# (v4,14) and -- "Rx32 ^= and ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 1 1 1 0 s s s s s P P + t t t t t + 1 0 x x x x x + +:and"^=" Rd5,rs5,rt5 EndPacket is iclass=0xe & op2127=0x7e & op13=0 & op0507=2 & rs5 & rt5 & rd5 & Rd5 & $(END_PACKET) +{ + Rd5 = rd5 ^ (rs5 & rt5); + build EndPacket; +} + +# (v4,14) and -- "Rx32 ^= and ( Rs32 , ~ Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 1 0 0 1 s s s s s P P + t t t t t + 1 0 x x x x x + +:and"^=" Rd5,rs5,OnesCompRt5 EndPacket is iclass=0xe & op2127=0x79 & op13=0 & op0507=2 & rs5 & OnesCompRt5 & rd5 & Rd5 & $(END_PACKET) +{ + Rd5 = rd5 ^ (rs5 & OnesCompRt5); + build EndPacket; +} + +# (v4,13) and -- "Rx32 |= and ( Rs32 , #s10x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 1 0 1 0 0 0 i s s s s s P P i i i i i i i i i x x x x x + +:and|= Rd5,rs5,Simm32_21_0513x EndPacket is iclass=13 & op2227=0x28 & Rd5 & rd5 & Simm32_21_0513x & rs5 & $(END_PACKET) { + Rd5 = rd5 | (rs5 & Simm32_21_0513x); + build EndPacket; +} + +# (v4,14) and -- "Rx32 |= and ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 1 0 1 0 s s s s s P P + t t t t t + 1 1 x x x x x + +:and|= Rd5,rs5,rt5 EndPacket is iclass=0xe & op2127=0x7a & op13=0 & op0507=3 & rs5 & rt5 & rd5 & Rd5 & $(END_PACKET) +{ + Rd5 = rd5 | (rs5 & rt5); + build EndPacket; +} + +# (v4,14) and -- "Rx32 |= and ( Rs32 , ~ Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 1 0 0 1 s s s s s P P + t t t t t + 0 0 x x x x x + +:and|= Rd5,rs5,OnesCompRt5 EndPacket is iclass=0xe & op2127=0x79 & op13=0 & op0507=0 & rs5 & OnesCompRt5 & rd5 & Rd5 & $(END_PACKET) +{ + Rd5 = rd5 | (rs5 & OnesCompRt5); + build EndPacket; +} + +# (v2,15) and -- "if ( Pu4 ) Rd32 = and ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 1 1 0 0 1 + 0 0 s s s s s P P 0 t t t t t 0 u u d d d d d +# +# (v2,15) and -- "if ( ! Pu4 ) Rd32 = and ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 1 1 0 0 1 + 0 0 s s s s s P P 0 t t t t t 1 u u d d d d d +# +# (v2,15) and -- "if ( Pu4 .new ) Rd32 = and ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 1 1 0 0 1 + 0 0 s s s s s P P 1 t t t t t 0 u u d d d d d +# +# (v2,15) and -- "if ( ! Pu4 .new ) Rd32 = and ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 1 1 0 0 1 + 0 0 s s s s s P P 1 t t t t t 1 u u d d d d d + +:and^PuCond0506_N13_S07 rd5,rs5,rt5 EndPacket is iclass=15 & op2327=0x12 & op22=0 & op21=0 & PuCond0506_N13_S07 & rs5 & rt5 & rd5 & rd5_ & SetNRegRd5 & $(END_PACKET) { + build PuCond0506_N13_S07; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + rd5_ = rs5 & rt5; + + <> + if (ConditionReg == 0) goto ; + rd5 = rd5_; + +} + +# (v2,6) any8 -- "Pd4 = any8 ( Ps4 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 1 0 1 1 1 0 0 0 + + s s P P 0 + + + + + + + + + + + d d + +:any8 Pd2,pu1617 EndPacket is iclass=6 & op2127=0x5c & op1820=0 & op0213=0 & pu1617 & Pd2 & $(END_PACKET) { + Pd2 = Pd2 & ((pu1617 != 0) * 0xff); + build EndPacket; +} + +# any8 -- "Pd4 = any8 ( vcmpb.eq ( Rss32 , Rtt32 ) )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 0 0 + + s s s s s P P 1 t t t t t 0 0 0 + + + d d + +define pcodeop vcmpb.eq; + +VcmpbEq: "vcmpb.eq("^rss5,rtt5^")" is rss5 & rtt5 { tmp:1 = vcmpb.eq(rss5,rtt5); export tmp; } + +:any8 Pd2,VcmpbEq EndPacket is iclass=13 & op2127=0x10 & op13=1 & op0207=0 & rss5 & rtt5 & Pd2 & VcmpbEq & $(END_PACKET) { + Pd2 = Pd2 & ((VcmpbEq != 0) * 0xff); + build EndPacket; +} + +# (v4,13) any8 -- "Pd4 = !any8 ( vcmpb.eq ( Rss32 , Rtt32 ) )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 0 0 - - s s s s s P P 1 t t t t t 0 0 1 - - - d d + +:any8! Pd2,VcmpbEq EndPacket is iclass=13 & op2127=0x10 & op13=1 & op0207=8 & rss5 & rtt5 & Pd2 & VcmpbEq & $(END_PACKET) { + Pd2 = Pd2 & ~((VcmpbEq != 0) * 0xff); + build EndPacket; +} + + +# (v2,8) rol -- "Rd32 = rol ( Rs32 , #u5 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 1 0 0 0 0 0 s s s s s P P 0 i i i i i 0 1 1 d d d d d + +:rol Rd5,rs5,Uimm8_0812 EndPacket is iclass=8 & op2127=0x60 & op13=0 & op0507=3 & Rd5 & rs5 & Uimm8_0812 & $(END_PACKET) { + Rd5 = (rs5 << Uimm8_0812) | zext((rs5 s< 0) * 1); + build EndPacket; +} + +# (v2,8) asl -- "Rd32 = asl ( Rs32 , #u5 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 1 0 0 0 0 0 s s s s s P P 0 i i i i i 0 1 0 d d d d d + +:asl Rd5,rs5,Uimm8_0812 EndPacket is iclass=8 & op2127=0x60 & op13=0 & op0507=2 & Rd5 & rs5 & Uimm8_0812 & $(END_PACKET) { + Rd5 = rs5 << Uimm8_0812; + build EndPacket; +} + +# (v2,8) asl -- "Rd32 = asl ( Rs32 , #u5 ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 1 0 0 0 1 0 s s s s s P P 0 i i i i i 0 1 0 d d d d d + +define pcodeop aslSat; + +:asl":sat" Rd5,rs5,Uimm8_0812 EndPacket is iclass=8 & op2127=0x62 & op13=0 & op0507=2 & Rd5 & rs5 & Uimm8_0812 & $(END_PACKET) { + Rd5 = aslSat(rs5, Uimm8_0812); + build EndPacket; +} + +# (v2,12) asl -- "Rd32 = asl ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 1 1 0 0 1 + s s s s s P P + t t t t t 1 0 + d d d d d + +:asl Rd5,rs5,rt5 EndPacket is iclass=12 & op2127=0x32 & op13=0 & op0507=4 & Rd5 & rs5 & rt5 & $(END_PACKET) { + right:1 = rt5 s< 0; + Rd5 = (zext(right) * (rs5 s>> -rt5)) + (zext(!right) * (rs5 << rt5)); + build EndPacket; +} + +# (v2,12) asl -- "Rd32 = asl ( Rs32 , Rt32 ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 1 1 0 0 0 + s s s s s P P + t t t t t 1 0 + d d d d d + +:asl":sat" Rd5,rs5,rt5 EndPacket is iclass=12 & op2127=0x30 & op13=0 & op0507=4 & Rd5 & rs5 & rt5 & $(END_PACKET) { + Rd5 = aslSat(rs5, rt5); + build EndPacket; +} + +# (v2,8) asl -- "Rdd32 = asl ( Rss32 , #u6 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 0 0 0 0 0 + s s s s s P P i i i i i i 0 1 0 d d d d d + +:asl Rdd5,rss5,Uimm8_0813 EndPacket is iclass=8 & op2127=0x00 & op0507=2 & Rdd5 & rss5 & Uimm8_0813 & $(END_PACKET) { + Rdd5 = rss5 << Uimm8_0813; + build EndPacket; +} + +# (v2,8) rol -- "Rdd32 = rol ( Rss32 , #u6 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 0 0 0 0 0 + s s s s s P P i i i i i i 0 1 1 d d d d d + +:rol Rdd5,rss5,Uimm8_0813 EndPacket is iclass=8 & op2127=0x00 & op0507=3 & Rdd5 & rss5 & Uimm8_0813 & $(END_PACKET) { + Rdd5 = (rss5 << Uimm8_0813) | zext((rss5 s< 0) * 1); + build EndPacket; +} + +# (v2,12) asl -- "Rdd32 = asl ( Rss32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 0 1 1 1 0 + s s s s s P P + t t t t t 1 0 + d d d d d + +:asl Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x1c & op13=0 & op0507=4 & Rdd5 & rss5 & rt5 & $(END_PACKET) { + right:1 = rt5 s< 0; + Rdd5 = (zext(right) * (rss5 s>> -rt5)) + (zext(!right) * (rss5 << rt5)); + build EndPacket; +} + +# (v2,8) asl -- "Rx32 &= asl ( Rs32 , #u5 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 1 1 0 0 1 + s s s s s P P 0 i i i i i 0 1 0 x x x x x + +:asl&= Rd5,rs5,Uimm8_0812 EndPacket is iclass=8 & op2127=0x72 & op13=0 & op0507=2 & Rd5 & rd5 & rs5 & Uimm8_0812 & $(END_PACKET) { + Rd5 = rd5 & (rs5 << Uimm8_0812); + build EndPacket; +} + +# (v2,8) rol -- "Rx32 &= rol ( Rs32 , #u5 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 1 1 0 0 1 + s s s s s P P 0 i i i i i 0 1 1 x x x x x + +:rol&= Rd5,rs5,Uimm8_0812 EndPacket is iclass=8 & op2127=0x72 & op13=0 & op0507=3 & Rd5 & rd5 & rs5 & Uimm8_0812 & $(END_PACKET) { + Rd5 = rd5 & ((rs5 << Uimm8_0812) | zext((rs5 s<0) * 1)); + build EndPacket; +} + +# (v2,12) asl -- "Rx32 &= asl ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 1 1 0 0 0 1 + s s s s s P P + t t t t t 1 0 + x x x x x + +:asl&= Rd5,rs5,rt5 EndPacket is iclass=12 & op2127=0x62 & op13=0 & op0507=4 & Rd5 & rd5 & rs5 & rt5 & $(END_PACKET) { + right:1 = rt5 s< 0; + result:4 = (zext(right) * (rs5 s>> -rt5)) + (zext(!right) * (rs5 << rt5)); + Rd5 = rd5 & result; + build EndPacket; +} + +# (v2,8) asl -- "Rx32 += asl ( Rs32 , #u5 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 1 1 0 0 0 + s s s s s P P 0 i i i i i 1 1 0 x x x x x + +:asl+= Rd5,rs5,Uimm8_0812 EndPacket is iclass=8 & op2127=0x70 & op13=0 & op0507=6 & Rd5 & rd5 & rs5 & Uimm8_0812 & $(END_PACKET) { + Rd5 = rd5 + (rs5 << Uimm8_0812); + build EndPacket; +} + +# (v2,8) rol -- "Rx32 += rol ( Rs32 , #u5 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 1 1 0 0 0 + s s s s s P P 0 i i i i i 1 1 1 x x x x x + +:rol+= Rd5,rs5,Uimm8_0812 EndPacket is iclass=8 & op2127=0x70 & op13=0 & op0507=7 & Rd5 & rd5 & rs5 & Uimm8_0812 & $(END_PACKET) { + Rd5 = rd5 + ((rs5 << Uimm8_0812) | zext((rs5 s< 0) * 1)); + build EndPacket; +} + +# (v2,12) asl -- "Rx32 += asl ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 1 1 0 0 1 1 + s s s s s P P + t t t t t 1 0 + x x x x x + +:asl+= Rd5,rs5,rt5 EndPacket is iclass=12 & op2127=0x66 & op13=0 & op0507=4 & Rd5 & rd5 & rs5 & rt5 & $(END_PACKET) { + right:1 = rt5 s< 0; + result:4 = (zext(right) * (rs5 s>> -rt5)) + (zext(!right) * (rs5 << rt5)); + Rd5 = rd5 + result; + build EndPacket; +} + +# (v2,8) asl -- "Rx32 -= asl ( Rs32 , #u5 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 1 1 0 0 0 + s s s s s P P 0 i i i i i 0 1 0 x x x x x + +:asl-= Rd5,rs5,Uimm8_0812 EndPacket is iclass=8 & op2127=0x70 & op13=0 & op0507=2 & Rd5 & rd5 & rs5 & Uimm8_0812 & $(END_PACKET) { + Rd5 = rd5 - (rs5 << Uimm8_0812); + build EndPacket; +} + +# (v2,8) rol -- "Rx32 -= rol ( Rs32 , #u5 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 1 1 0 0 0 + s s s s s P P 0 i i i i i 0 1 1 x x x x x + +:rol-= Rd5,rs5,Uimm8_0812 EndPacket is iclass=8 & op2127=0x70 & op13=0 & op0507=3 & Rd5 & rd5 & rs5 & Uimm8_0812 & $(END_PACKET) { + Rd5 = rd5 - ((rs5 << Uimm8_0812) | zext((rs5 s< 0) * 1)); + build EndPacket; +} + +# (v2,12) asl -- "Rx32 -= asl ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 1 1 0 0 1 0 + s s s s s P P + t t t t t 1 0 + x x x x x + +:asl-= Rd5,rs5,rt5 EndPacket is iclass=12 & op2127=0x64 & op13=0 & op0507=4 & Rd5 & rd5 & rs5 & rt5 & $(END_PACKET) { + right:1 = rt5 s< 0; + result:4 = (zext(right) * (rs5 s>> -rt5)) + (zext(!right) * (rs5 << rt5)); + Rd5 = rd5 - result; + build EndPacket; +} + +# (v2,8) asl -- "Rx32 ^= asl ( Rs32 , #u5 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 1 1 0 1 0 + s s s s s P P 0 i i i i i 0 1 0 x x x x x + +:asl"^=" Rd5,rs5,Uimm8_0812 EndPacket is iclass=8 & op2127=0x74 & op13=0 & op0507=2 & Rd5 & rd5 & rs5 & Uimm8_0812 & $(END_PACKET) { + Rd5 = rd5 ^ (rs5 << Uimm8_0812); + build EndPacket; +} + +# (v2,8) rol -- "Rx32 ^= rol ( Rs32 , #u5 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 1 1 0 1 0 + s s s s s P P 0 i i i i i 0 1 1 x x x x x + +:rol"^=" Rd5,rs5,Uimm8_0812 EndPacket is iclass=8 & op2127=0x74 & op13=0 & op0507=3 & Rd5 & rd5 & rs5 & Uimm8_0812 & $(END_PACKET) { + Rd5 = rd5 ^ ((rs5 << Uimm8_0812) | zext((rs5 s< 0) * 1)); + build EndPacket; +} + +# (v2,8) asl -- "Rx32 |= asl ( Rs32 , #u5 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 1 1 0 0 1 + s s s s s P P 0 i i i i i 1 1 0 x x x x x + +:asl|= Rd5,rs5,Uimm8_0812 EndPacket is iclass=8 & op2127=0x72 & op13=0 & op0507=6 & Rd5 & rd5 & rs5 & Uimm8_0812 & $(END_PACKET) { + Rd5 = rd5 | (rs5 << Uimm8_0812); + build EndPacket; +} + +# (v2,8) rol -- "Rx32 |= rol ( Rs32 , #u5 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 1 1 0 0 1 + s s s s s P P 0 i i i i i 1 1 1 x x x x x + +:rol|= Rd5,rs5,Uimm8_0812 EndPacket is iclass=8 & op2127=0x72 & op13=0 & op0507=7 & Rd5 & rd5 & rs5 & Uimm8_0812 & $(END_PACKET) { + Rd5 = rd5 | ((rs5 << Uimm8_0812) | zext((rs5 s< 0) * 1)); + build EndPacket; +} + +# (v2,12) asl -- "Rx32 |= asl ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 1 1 0 0 0 0 + s s s s s P P + t t t t t 1 0 + x x x x x + +:asl|= Rd5,rs5,rt5 EndPacket is iclass=12 & op2127=0x60 & op13=0 & op0507=4 & Rd5 & rd5 & rs5 & rt5 & $(END_PACKET) { + right:1 = rt5 s< 0; + result:4 = (zext(right) * (rs5 s>> -rt5)) + (zext(!right) * (rs5 << rt5)); + Rd5 = rd5 | result; + build EndPacket; +} + +# (v2,8) asl -- "Rxx32 &= asl ( Rss32 , #u6 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 0 1 0 0 1 + s s s s s P P i i i i i i 0 1 0 x x x x x + +:asl&= Rdd5,rss5,Uimm8_0813 EndPacket is iclass=8 & op2127=0x12 & op0507=2 & Rdd5 & rdd5 & rss5 & Uimm8_0813 & $(END_PACKET) { + Rdd5 = rdd5 & (rss5 << Uimm8_0813); + build EndPacket; +} + +# (v2,8) rol -- "Rxx32 &= rol ( Rss32 , #u6 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 0 1 0 0 1 + s s s s s P P i i i i i i 0 1 1 x x x x x + +:rol&= Rdd5,rss5,Uimm8_0813 EndPacket is iclass=8 & op2127=0x12 & op0507=3 & Rdd5 & rdd5 & rss5 & Uimm8_0813 & $(END_PACKET) { + Rdd5 = rdd5 & ((rss5 << Uimm8_0813) | zext((rss5 s< 0) * 1)); + build EndPacket; +} + +# (v2,12) asl -- "Rxx32 &= asl ( Rss32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 1 0 1 1 0 1 0 s s s s s P P + t t t t t 1 0 + x x x x x + +:asl&= Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x5a & op13=0 & op0507=4 & Rdd5 & rdd5 & rss5 & rt5 & $(END_PACKET) { + right:1 = rt5 s< 0; + result:8 = (zext(right) * (rss5 s>> -rt5)) + (zext(!right) * (rss5 << rt5)); + Rdd5 = rdd5 & result; + build EndPacket; +} + +# (v2,8) asl -- "Rxx32 += asl ( Rss32 , #u6 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 0 1 0 0 0 + s s s s s P P i i i i i i 1 1 0 x x x x x + +:asl+= Rdd5,rss5,Uimm8_0813 EndPacket is iclass=8 & op2127=0x10 & op0507=6 & Rdd5 & rdd5 & rss5 & Uimm8_0813 & $(END_PACKET) { + Rdd5 = rdd5 + (rss5 << Uimm8_0813); + build EndPacket; +} + +# (v2,8) rol -- "Rxx32 += rol ( Rss32 , #u6 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 0 1 0 0 0 + s s s s s P P i i i i i i 1 1 1 x x x x x + +:rol+= Rdd5,rss5,Uimm8_0813 EndPacket is iclass=8 & op2127=0x10 & op0507=7 & Rdd5 & rdd5 & rss5 & Uimm8_0813 & $(END_PACKET) { + Rdd5 = rdd5 + ((rss5 << Uimm8_0813) | zext((rss5 s< 0) * 1)); + build EndPacket; +} + +# (v2,12) asl -- "Rxx32 += asl ( Rss32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 1 0 1 1 1 1 0 s s s s s P P + t t t t t 1 0 + x x x x x + +:asl+= Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x5e & op13=0 & op0507=4 & Rdd5 & rdd5 & rss5 & rt5 & $(END_PACKET) { + right:1 = rt5 s< 0; + result:8 = (zext(right) * (rss5 s>> -rt5)) + (zext(!right) * (rss5 << rt5)); + Rdd5 = rdd5 + result; + build EndPacket; +} + +# (v2,8) asl -- "Rxx32 -= asl ( Rss32 , #u6 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 0 1 0 0 0 + s s s s s P P i i i i i i 0 1 0 x x x x x + +:asl-= Rdd5,rss5,Uimm8_0813 EndPacket is iclass=8 & op2127=0x10 & op0507=2 & Rdd5 & rdd5 & rss5 & Uimm8_0813 & $(END_PACKET) { + Rdd5 = rdd5 - (rss5 << Uimm8_0813); + build EndPacket; +} + +# (v2,8) rol -- "Rxx32 -= rol ( Rss32 , #u6 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 0 1 0 0 0 + s s s s s P P i i i i i i 0 1 1 x x x x x + +:rol-= Rdd5,rss5,Uimm8_0813 EndPacket is iclass=8 & op2127=0x10 & op0507=3 & Rdd5 & rdd5 & rss5 & Uimm8_0813 & $(END_PACKET) { + Rdd5 = rdd5 - ((rss5 << Uimm8_0813) | zext((rss5 s< 0) * 1)); + build EndPacket; +} + +# (v2,12) asl -- "Rxx32 -= asl ( Rss32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 1 0 1 1 1 0 0 s s s s s P P + t t t t t 1 0 + x x x x x + +:asl-= Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x5c & op13=0 & op0507=4 & Rdd5 & rdd5 & rss5 & rt5 & $(END_PACKET) { + right:1 = rt5 s< 0; + result:8 = (zext(right) * (rss5 s>> -rt5)) + (zext(!right) * (rss5 << rt5)); + Rdd5 = rdd5 - result; + build EndPacket; +} + +# (v2,8) asl -- "Rxx32 ^= asl ( Rss32 , #u6 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 0 1 0 1 0 + s s s s s P P i i i i i i 0 1 0 x x x x x + +:asl"^=" Rdd5,rss5,Uimm8_0813 EndPacket is iclass=8 & op2127=0x14 & op0507=2 & Rdd5 & rdd5 & rss5 & Uimm8_0813 & $(END_PACKET) { + Rdd5 = rdd5 ^ (rss5 << Uimm8_0813); + build EndPacket; +} + +# (v2,8) rol -- "Rxx32 ^= rol ( Rss32 , #u6 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 0 1 0 1 0 + s s s s s P P i i i i i i 0 1 1 x x x x x + +:rol"^=" Rdd5,rss5,Uimm8_0813 EndPacket is iclass=8 & op2127=0x14 & op0507=3 & Rdd5 & rdd5 & rss5 & Uimm8_0813 & $(END_PACKET) { + Rdd5 = rdd5 ^ ((rss5 << Uimm8_0813) | zext((rss5 s< 0) * 1)); + build EndPacket; +} + +# (v4,12) asl -- "Rxx32 ^= asl ( Rss32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 1 0 1 1 0 1 1 s s s s s P P + t t t t t 1 0 + x x x x x + +:asl"^=" Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x5b & op13=0 & op0507=4 & Rdd5 & rdd5 & rss5 & rt5 & $(END_PACKET) { + right:1 = rt5 s< 0; + result:8 = (zext(right) * (rss5 s>> -rt5)) + (zext(!right) * (rss5 << rt5)); + Rdd5 = rdd5 ^ result; + build EndPacket; +} + +# (v2,8) asl -- "Rxx32 |= asl ( Rss32 , #u6 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 0 1 0 0 1 + s s s s s P P i i i i i i 1 1 0 x x x x x + +:asl|= Rdd5,rss5,Uimm8_0813 EndPacket is iclass=8 & op2127=0x12 & op0507=6 & Rdd5 & rdd5 & rss5 & Uimm8_0813 & $(END_PACKET) { + Rdd5 = rdd5 | (rss5 << Uimm8_0813); + build EndPacket; +} + +# (v2,8) rol -- "Rxx32 |= rol ( Rss32 , #u6 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 0 1 0 0 1 + s s s s s P P i i i i i i 1 1 1 x x x x x + +:rol|= Rdd5,rss5,Uimm8_0813 EndPacket is iclass=8 & op2127=0x12 & op0507=7 & Rdd5 & rdd5 & rss5 & Uimm8_0813 & $(END_PACKET) { + Rdd5 = rdd5 | ((rss5 << Uimm8_0813) | zext((rss5 s< 0) * 1)); + build EndPacket; +} + +# (v2,12) asl -- "Rxx32 |= asl ( Rss32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 1 0 1 1 0 0 0 s s s s s P P + t t t t t 1 0 + x x x x x + +:asl|= Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x58 & op13=0 & op0507=4 & Rdd5 & rdd5 & rss5 & rt5 & $(END_PACKET) { + right:1 = rt5 s< 0; + result:8 = (zext(right) * (rss5 s>> -rt5)) + (zext(!right) * (rss5 << rt5)); + Rdd5 = rdd5 | result; + build EndPacket; +} + +# (v2,7) aslh -- "Rd32 = aslh ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 1 0 0 0 0 0 0 0 s s s s s P P 0 + + + + + + + + d d d d d + +:aslh Rd5,rs5 EndPacket is iclass=7 & op2127=0 & op13=0 & op0512=0 & Rd5 & rs5 & $(END_PACKET) { + Rd5 = rs5 << 16; + build EndPacket; +} + +# (v4,7) aslh -- "if ( Pu4 ) Rd32 = aslh ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 1 0 0 0 0 0 0 0 s s s s s P P 1 - 0 0 u u - - - d d d d d +# +# (v4,7) aslh -- "if ( ! Pu4 ) Rd32 = aslh ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 1 0 0 0 0 0 0 0 s s s s s P P 1 - 1 0 u u - - - d d d d d +# +# (v4,7) aslh -- "if ( Pu4 .new ) Rd32 = aslh ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 1 0 0 0 0 0 0 0 s s s s s P P 1 - 0 1 u u - - - d d d d d +# +# (v4,7) aslh -- "if ( ! Pu4 .new ) Rd32 = aslh ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 1 0 0 0 0 0 0 0 s s s s s P P 1 - 1 1 u u - - - d d d d d + +:aslh^PuCond0809_N10_S11 rd5,rs5 EndPacket is iclass=7 & op2127=0 & op13=1 & rd5 & rd5_ & SetNRegRd5 & rs5 & PuCond0809_N10_S11 & $(END_PACKET) { + build PuCond0809_N10_S11; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + rd5_ = rs5 << 16; + + <> + if (ConditionReg == 0) goto ; + rd5 = rd5_; + +} + +# (v2,8) asr -- "Rd32 = asr ( Rs32 , #u5 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 1 0 0 0 0 0 s s s s s P P 0 i i i i i 0 0 0 d d d d d + +:asr Rd5,rs5,Uimm8_0812 EndPacket is iclass=8 & op2127=0x60 & op13=0 & op0507=0 & Rd5 & rs5 & Uimm8_0812 & $(END_PACKET) { + Rd5 = rs5 s>> Uimm8_0812; + build EndPacket; +} + +# (v2,8) asr -- "Rd32 = asr ( Rs32 , #u5 ) :rnd" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 1 0 0 0 1 0 s s s s s P P 0 i i i i i 0 0 0 d d d d d + +:asr":rnd" Rd5,rs5,Uimm8_0812 EndPacket is iclass=8 & op2127=0x62 & op13=0 & op0507=0 & Rd5 & rs5 & Uimm8_0812 & $(END_PACKET) { + Rd5 = roundArithmetic(rs5 s>> Uimm8_0812, 1:1); + build EndPacket; +} + +# (v5,8) asr -- "Rdd32 = asr ( Rss32 , #u6 ) :rnd" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 0 0 0 1 1 0 s s s s s P P i i i i i i 1 1 1 d d d d d + +:asr":rnd" Rdd5,rss5,Uimm8_0813 EndPacket is iclass=8 & op2127=0x06 & op0507=7 & Rdd5 & rss5 & Uimm8_0813 & $(END_PACKET) { + Rdd5 = roundArithmetic(rss5 s>> Uimm8_0813, 1:1); + build EndPacket; +} + +# (v2,12) asr -- "Rd32 = asr ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 1 1 0 0 1 + s s s s s P P + t t t t t 0 0 + d d d d d + +:asr Rd5,rs5,rt5 EndPacket is iclass=12 & op2127=0x32 & op13=0 & op0507=0 & Rd5 & rs5 & rt5 & $(END_PACKET) { + left:1 = rt5 s< 0; + Rd5 = (zext(!left) * (rs5 s>> rt5)) + (zext(left) * (rs5 << -rt5)); + build EndPacket; +} + +# (v2,12) asr -- "Rd32 = asr ( Rs32 , Rt32 ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 1 1 0 0 0 + s s s s s P P + t t t t t 0 0 + d d d d d + +define pcodeop asrSat; + +:asr":sat" Rd5,rs5,rt5 EndPacket is iclass=12 & op2127=0x30 & op13=0 & op0507=0 & Rd5 & rs5 & rt5 & $(END_PACKET) { + Rd5 = asrSat(rs5, rt5); + build EndPacket; +} + +# (v2,8) asr -- "Rdd32 = asr ( Rss32 , #u6 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 0 0 0 0 0 + s s s s s P P i i i i i i 0 0 0 d d d d d + +:asr Rdd5,rss5,Uimm8_0813 EndPacket is iclass=8 & op2127=0x00 & op0507=0 & Rdd5 & rss5 & Uimm8_0813 & $(END_PACKET) { + Rdd5 = rss5 s>> Uimm8_0813; + build EndPacket; +} + +# (v2,12) asr -- "Rdd32 = asr ( Rss32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 0 1 1 1 0 + s s s s s P P + t t t t t 0 0 + d d d d d + +:asr Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x1c & op13=0 & op0507=0 & Rdd5 & rss5 & rt5 & $(END_PACKET) { + left:1 = rt5 s< 0; + Rdd5 = (zext(!left) * (rss5 s>> rt5)) + (zext(left) * (rss5 << -rt5)); + build EndPacket; +} + +# (v2,8) asr -- "Rx32 &= asr ( Rs32 , #u5 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 1 1 0 0 1 + s s s s s P P 0 i i i i i 0 0 0 x x x x x + +:asr&= Rd5,rs5,Uimm8_0812 EndPacket is iclass=8 & op2127=0x72 & op13=0 & op0507=0 & Rd5 & rd5 & rs5 & Uimm8_0812 & $(END_PACKET) { + Rd5 = rd5 & (rs5 s>> Uimm8_0812); + build EndPacket; +} + +# (v2,12) asr -- "Rx32 &= asr ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 1 1 0 0 0 1 + s s s s s P P + t t t t t 0 0 + x x x x x + +:asr&= Rd5,rs5,rt5 EndPacket is iclass=12 & op2127=0x62 & op13=0 & op0507=0 & Rd5 & rd5 & rs5 & rt5 & $(END_PACKET) { + left:1 = rt5 s< 0; + result:4 = (zext(!left) * (rs5 s>> rt5)) + (zext(left) * (rs5 << -rt5)); + Rd5 = rd5 & result; + build EndPacket; +} + +# (v2,8) asr -- "Rx32 += asr ( Rs32 , #u5 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 1 1 0 0 0 + s s s s s P P 0 i i i i i 1 0 0 x x x x x + +:asr+= Rd5,rs5,Uimm8_0812 EndPacket is iclass=8 & op2127=0x70 & op13=0 & op0507=4 & Rd5 & rd5 & rs5 & Uimm8_0812 & $(END_PACKET) { + Rd5 = rd5 + (rs5 s>> Uimm8_0812); + build EndPacket; +} + +# (v2,12) asr -- "Rx32 += asr ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 1 1 0 0 1 1 + s s s s s P P + t t t t t 0 0 + x x x x x + +:asr+= Rd5,rs5,rt5 EndPacket is iclass=12 & op2127=0x66 & op13=0 & op0507=0 & Rd5 & rd5 & rs5 & rt5 & $(END_PACKET) { + left:1 = rt5 s< 0; + result:4 = (zext(!left) * (rs5 s>> rt5)) + (zext(left) * (rs5 << -rt5)); + Rd5 = rd5 + result; + build EndPacket; +} + +# (v2,8) asr -- "Rx32 -= asr ( Rs32 , #u5 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 1 1 0 0 0 + s s s s s P P 0 i i i i i 0 0 0 x x x x x + +:asr-= Rd5,rs5,Uimm8_0812 EndPacket is iclass=8 & op2127=0x70 & op13=0 & op0507=0 & Rd5 & rd5 & rs5 & Uimm8_0812 & $(END_PACKET) { + Rd5 = rd5 - (rs5 s>> Uimm8_0812); + build EndPacket; +} + +# (v2,12) asr -- "Rx32 -= asr ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 1 1 0 0 1 0 + s s s s s P P + t t t t t 0 0 + x x x x x + +:asr-= Rd5,rs5,rt5 EndPacket is iclass=12 & op2127=0x64 & op13=0 & op0507=0 & Rd5 & rd5 & rs5 & rt5 & $(END_PACKET) { + left:1 = rt5 s< 0; + result:4 = (zext(!left) * (rs5 s>> rt5)) + (zext(left) * (rs5 << -rt5)); + Rd5 = rd5 - result; + build EndPacket; +} + +# (v2,8) asr -- "Rx32 |= asr ( Rs32 , #u5 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 1 1 0 0 1 + s s s s s P P 0 i i i i i 1 0 0 x x x x x + +:asr|= Rd5,rs5,Uimm8_0812 EndPacket is iclass=8 & op2127=0x72 & op13=0 & op0507=4 & Rd5 & rd5 & rs5 & Uimm8_0812 & $(END_PACKET) { + Rd5 = rd5 | (rs5 s>> Uimm8_0812); + build EndPacket; +} + +# (v2,12) asr -- "Rx32 |= asr ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 1 1 0 0 0 0 + s s s s s P P + t t t t t 0 0 + x x x x x + +:asr|= Rd5,rs5,rt5 EndPacket is iclass=12 & op2127=0x60 & op13=0 & op0507=0 & Rd5 & rd5 & rs5 & rt5 & $(END_PACKET) { + left:1 = rt5 s< 0; + result:4 = (zext(!left) * (rs5 s>> rt5)) + (zext(left) * (rs5 << -rt5)); + Rd5 = rd5 | result; + build EndPacket; +} + +# (v2,8) asr -- "Rxx32 &= asr ( Rss32 , #u6 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 0 1 0 0 1 + s s s s s P P i i i i i i 0 0 0 x x x x x + +:asr&= Rdd5,rss5,Uimm8_0813 EndPacket is iclass=8 & op2127=0x12 & op0507=0 & Rdd5 & rdd5 & rss5 & Uimm8_0813 & $(END_PACKET) { + Rdd5 = rdd5 & (rss5 s>> Uimm8_0813); + build EndPacket; +} + +# (v2,12) asr -- "Rxx32 &= asr ( Rss32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 1 0 1 1 0 1 0 s s s s s P P + t t t t t 0 0 + x x x x x + +:asr&= Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x5a & op13=0 & op0507=0 & Rdd5 & rdd5 & rss5 & rt5 & $(END_PACKET) { + left:1 = rt5 s< 0; + result:8 = (zext(!left) * (rss5 s>> rt5)) + (zext(left) * (rss5 << -rt5)); + Rdd5 = rdd5 & result; + build EndPacket; +} + +# (v2,8) asr -- "Rxx32 += asr ( Rss32 , #u6 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 0 1 0 0 0 + s s s s s P P i i i i i i 1 0 0 x x x x x + +:asr+= Rdd5,rss5,Uimm8_0813 EndPacket is iclass=8 & op2127=0x10 & op0507=4 & Rdd5 & rdd5 & rss5 & Uimm8_0813 & $(END_PACKET) { + Rdd5 = rdd5 + (rss5 s>> Uimm8_0813); + build EndPacket; +} + +# (v2,12) asr -- "Rxx32 += asr ( Rss32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 1 0 1 1 1 1 0 s s s s s P P + t t t t t 0 0 + x x x x x + +:asr+= Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x5e & op13=0 & op0507=0 & Rdd5 & rdd5 & rss5 & rt5 & $(END_PACKET) { + left:1 = rt5 s< 0; + result:8 = (zext(!left) * (rss5 s>> rt5)) + (zext(left) * (rss5 << -rt5)); + Rdd5 = rdd5 + result; + build EndPacket; +} + +# (v2,8) asr -- "Rxx32 -= asr ( Rss32 , #u6 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 0 1 0 0 0 + s s s s s P P i i i i i i 0 0 0 x x x x x + +:asr-= Rdd5,rss5,Uimm8_0813 EndPacket is iclass=8 & op2127=0x10 & op0507=0 & Rdd5 & rdd5 & rss5 & Uimm8_0813 & $(END_PACKET) { + Rdd5 = rdd5 - (rss5 s>> Uimm8_0813); + build EndPacket; +} + +# (v2,12) asr -- "Rxx32 -= asr ( Rss32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 1 0 1 1 1 0 0 s s s s s P P + t t t t t 0 0 + x x x x x + +:asr-= Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x5c & op13=0 & op0507=0 & Rdd5 & rdd5 & rss5 & rt5 & $(END_PACKET) { + left:1 = rt5 s< 0; + result:8 = (zext(!left) * (rss5 s>> rt5)) + (zext(left) * (rss5 << -rt5)); + Rdd5 = rdd5 - result; + build EndPacket; +} + +# (v4,12) asr -- "Rxx32 ^= asr ( Rss32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 1 0 1 1 0 1 1 s s s s s P P + t t t t t 0 0 + x x x x x + +:asr"^=" Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x5b & op13=0 & op0507=0 & Rdd5 & rdd5 & rss5 & rt5 & $(END_PACKET) { + left:1 = rt5 s< 0; + result:8 = (zext(!left) * (rss5 s>> rt5)) + (zext(left) * (rss5 << -rt5)); + Rdd5 = rdd5 ^ result; + build EndPacket; +} + +# (v2,8) asr -- "Rxx32 |= asr ( Rss32 , #u6 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 0 1 0 0 1 + s s s s s P P i i i i i i 1 0 0 x x x x x + +:asr|= Rdd5,rss5,Uimm8_0813 EndPacket is iclass=8 & op2127=0x12 & op0507=4 & Rdd5 & rdd5 & rss5 & Uimm8_0813 & $(END_PACKET) { + Rdd5 = rdd5 | (rss5 s>> Uimm8_0813); + build EndPacket; +} + +# (v2,12) asr -- "Rxx32 |= asr ( Rss32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 1 0 1 1 0 0 0 s s s s s P P + t t t t t 0 0 + x x x x x + +:asr|= Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x58 & op13=0 & op0507=0 & Rdd5 & rdd5 & rss5 & rt5 & $(END_PACKET) { + left:1 = rt5 s< 0; + result:8 = (zext(!left) * (rss5 s>> rt5)) + (zext(left) * (rss5 << -rt5)); + Rdd5 = rdd5 | result; + build EndPacket; +} + +# (v2,7) asrh -- "Rd32 = asrh ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 1 0 0 0 0 0 0 1 s s s s s P P 0 + + + + + + + + d d d d d + +:asrh Rd5,rs5 EndPacket is iclass=7 & op2127=1 & op13=0 & op0512=0 & Rd5 & rs5 & $(END_PACKET) { + Rd5 = rs5 s>> 16; + build EndPacket; +} + +# (v4,7) asrh -- "if ( Pu4 ) Rd32 = asrh ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 1 0 0 0 0 0 0 1 s s s s s P P 1 - 0 0 u u - - - d d d d d +# +# (v4,7) asrh -- "if ( ! Pu4 ) Rd32 = asrh ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 1 0 0 0 0 0 0 1 s s s s s P P 1 - 1 0 u u - - - d d d d d +# +# (v4,7) asrh -- "if ( Pu4 .new ) Rd32 = asrh ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 1 0 0 0 0 0 0 1 s s s s s P P 1 - 0 1 u u - - - d d d d d +# +# (v4,7) asrh -- "if ( ! Pu4 .new ) Rd32 = asrh ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 1 0 0 0 0 0 0 1 s s s s s P P 1 - 1 1 u u - - - d d d d d + +:asrh^PuCond0809_N10_S11 rd5,rs5 EndPacket is iclass=7 & op2127=1 & op13=1 & rd5 & rd5_ & SetNRegRd5 & rs5 & PuCond0809_N10_S11 & $(END_PACKET) { + build PuCond0809_N10_S11; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + rd5_ = rs5 s>> 16; + + <> + if (ConditionReg == 0) goto ; + rd5 = rd5_; + +} + +# (v2,6) assign -- "Cd32 = Rs32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 0 0 1 0 0 0 1 s s s s s P P + + + + + + + + + d d d d d + +:assign Cd5,rs5 EndPacket is iclass=6 & op2127=0x11 & op0513=0 & Cd5 & rs5 & $(END_PACKET) { + # NOTE: Assuming that PC will not be directly assigned + Cd5 = rs5; + build EndPacket; +} + +# (v4,6) assign -- "Cdd32 = Rss32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 0 0 1 1 0 0 1 s s s s s P P + + + + + + + + + d d d d d + +:assign Cdd5,rss5 EndPacket is iclass=6 & op2127=0x19 & op0513=0 & Cdd5 & rss5 & $(END_PACKET) { + # NOTE: Assuming that PC will not be directly assigned + Cdd5 = rss5; + build EndPacket; +} + +# (v4,6) assign -- "Gd32 = Rs32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 0 0 1 0 0 0 0 s s s s s P P + + + + + + + + + d d d d d + +:assign Gd5,rs5 EndPacket is iclass=6 & op2127=0x10 & op0513=0 & Gd5 & rs5 & $(END_PACKET) { + Gd5 = rs5; + build EndPacket; +} + +# (v4,6) assign -- "Gdd32 = Rss32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 0 0 1 1 0 0 0 s s s s s P P + + + + + + + + + d d d d d + +:assign Gdd5,rss5 EndPacket is iclass=6 & op2127=0x18 & op0513=0 & Gdd5 & rss5 & $(END_PACKET) { + Gdd5 = rss5; + build EndPacket; +} + +# (v2,8) assign -- "Pd4 = Rs32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 1 0 1 0 1 + s s s s s P P + + + + + + + + + + + + d d + +:assign Pd2,rs5 EndPacket is iclass=8 & op2127=0x2a & rs5 & op0213=0 & Pd2 & $(END_PACKET) { + Pd2 = Pd2 & rs5:1; + build EndPacket; +} + +# (v2,7) assign -- "Rd32 = #s16x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 1 1 0 0 0 i i - i i i i i P P i i i i i i i i i d d d d d + +:assign Rd5,Simm32_2223_1620_0513x EndPacket is iclass=7 & op2427=8 & op21=0 & Rd5 & Simm32_2223_1620_0513x & $(END_PACKET) { + Rd5 = Simm32_2223_1620_0513x; + build EndPacket; +} + +# (v2,6) assign -- "Rd32 = Cs32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 1 0 1 0 0 0 0 s s s s s P P + + + + + + + + + d d d d d + +:assign Rd5,Cs5 EndPacket is iclass=6 & op2127=0x50 & op0513=0 & Rd5 & Cs5 & $(END_PACKET) { + Rd5 = Cs5; + build EndPacket; +} + +# (v4,6) assign -- "Rd32 = Gs32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 1 0 1 0 0 0 1 s s s s s P P + + + + + + + + + d d d d d + +:assign Rd5,gs5 EndPacket is iclass=6 & op2127=0x51 & op0513=0 & Rd5 & gs5 & $(END_PACKET) { + Rd5 = gs5; + build EndPacket; +} + +# (v2,8) assign -- "Rd32 = Ps4" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 0 0 1 + 1 + + + + s s P P + + + + + + + + + d d d d d + +:assign Rd5,pu1617 EndPacket is iclass=8 & op1827=0x250 & pu1617 & op0513=0 & Rd5 & $(END_PACKET) { + Rd5 = zext( pu1617 ); + build EndPacket; +} + +# (v2,7) assign -- "Rd32 = Rs32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 1 0 0 0 0 0 1 1 s s s s s P P 0 - - - - - - - - d d d d d + +:assign Rd5,rs5 EndPacket is iclass=7 & op2127=0x03 & op0513=0 & Rd5 & rs5 & $(END_PACKET) { + Rd5 = rs5; + build EndPacket; +} + +# (v2,6) assign -- "Rd32 = Ss64" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 1 1 1 0 1 + s s s s s s P P + + + + + + + + + d d d d d + +:assign Rd5,ss6 EndPacket is iclass=6 & op2227=0x3a & op0513=0 & Rd5 & ss6 & $(END_PACKET) { + Rd5 = ss6; + build EndPacket; +} + +# (v4,6) assign -- "Rdd32 = Css32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 1 0 0 0 0 0 0 s s s s s P P + + + + + + + + + d d d d d + +:assign Rdd5,css5 EndPacket is iclass=6 & op2127=0x40 & op0513=0 & Rdd5 & css5 & $(END_PACKET) { + Rdd5 = css5; + build EndPacket; +} + +# (v4,6) assign -- "Rdd32 = Gss32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 1 0 0 0 0 0 1 s s s s s P P + + + + + + + + + d d d d d + +:assign Rdd5,gss5 EndPacket is iclass=6 & op2127=0x41 & op0513=0 & Rdd5 & gss5 & $(END_PACKET) { + Rdd5 = gss5; + build EndPacket; +} + +# (v4,6) assign -- "Rdd32 = Sss64" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 1 1 1 1 + + s s s s s s P P + + + + + + + + + d d d d d + +:assign Rdd5,sss6 EndPacket is iclass=6 & op2227=0x3c & op0513=0 & Rdd5 & sss6 & $(END_PACKET) { + Rdd5 = sss6; + build EndPacket; +} + +# (v2,7) assign -- "Rx32.h = #u16" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 1 0 0 1 0 i i 1 x x x x x P P i i i i i i i i i i i i i i + +:assign Rx5H,Uimm16_2223_0013 EndPacket is iclass=7 & op2427=2 & op21=1 & Rx5H & Uimm16_2223_0013 & $(END_PACKET) { + Rx5H = Uimm16_2223_0013; + build EndPacket; +} + +# (v2,7) assign -- "Rx32.l = #u16" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 1 0 0 0 1 i i 1 x x x x x P P i i i i i i i i i i i i i i + +:assign Rx5L,Uimm16_2223_0013 EndPacket is iclass=7 & op2427=1 & op21=1 & Rx5L & Uimm16_2223_0013 & $(END_PACKET) { + Rx5L = Uimm16_2223_0013; + build EndPacket; +} + +# (v2,6) assign -- "Sd64 = Rs32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 0 1 1 1 0 0 + s s s s s P P + + + + + + + + d d d d d d + +:assign Sd6,rs5 EndPacket is iclass=6 & op2127=0x38 & op0613=0 & Sd6 & rs5 & $(END_PACKET) { + Sd6 = rs5; + build EndPacket; +} + +# (v4,6) assign -- "Sdd64 = Rss32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 1 1 0 1 0 + + s s s s s P P + + + + + + + + d d d d d d + +:assign Sdd6,rss5 EndPacket is iclass=6 & op2127=0x68 & op0613=0 & Sdd6 & rss5 & $(END_PACKET) { + Sdd6 = rss5; + build EndPacket; +} + +# (v2,7) assign -- "if ( Pu4 ) Rd32 = #s12x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 1 1 1 1 0 0 u u 0 i i i i P P 0 i i i i i i i i d d d d d +# +# (v2,7) assign -- "if ( ! Pu4 ) Rd32 = #s12x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 1 1 1 1 0 1 u u 0 i i i i P P 0 i i i i i i i i d d d d d +# +# (v2,7) assign -- "if ( Pu4 .new ) Rd32 = #s12x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 1 1 1 1 0 0 u u 0 i i i i P P 1 i i i i i i i i d d d d d +# +# (v2,7) assign -- "if ( ! Pu4 .new ) Rd32 = #s12x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 1 1 1 1 0 1 u u 0 i i i i P P 1 i i i i i i i i d d d d d + +:assign^PuCond2122_N13_S23 rd5,Simm32_1619_0512x EndPacket is iclass=7 & op2427=0xe & op20=0 & PuCond2122_N13_S23 & rd5 & rd5_ & SetNRegRd5 & Simm32_1619_0512x & $(END_PACKET) { + build PuCond2122_N13_S23; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + rd5_ = Simm32_1619_0512x; + + <> + if (ConditionReg == 0) goto ; + rd5 = rd5_; + +} + +# (v2,10) barrier -- "barrier" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 0 0 0 0 0 + + + + + P P + + + + + + + + + + + + + + + +define pcodeop barrier; + +:barrier EndPacket is iclass=10 & op2127=0x40 & op1620=0 & op0013=0 & $(END_PACKET) { + barrier(); + build EndPacket; +} + +# (v2,8) bitsclr -- "Pd4 = bitsclr ( Rs32 , #u6 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 1 0 1 1 0 0 s s s s s P P i i i i i i + + + + + + d d + +:bitsclr Pd2,rs5,Uimm8_0813 EndPacket is iclass=8 & op2127=0x2c & op0207=0 & rs5 & Uimm8_0813 & Pd2 & $(END_PACKET) { + isClr:1 = (rs5 & zext(Uimm8_0813)) == 0; + Pd2 = Pd2 & (isClr * 0xff); + build EndPacket; +} + +# (v4,8) bitsclr -- "Pd4 = ! bitsclr ( Rs32 , #u6 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 1 0 1 1 0 1 s s s s s P P i i i i i i + + + + + + d d + +:bitsclr! Pd2,rs5,Uimm8_0813 EndPacket is iclass=8 & op2127=0x2d & op0207=0 & rs5 & Uimm8_0813 & Pd2 & $(END_PACKET) { + notClr:1 = (rs5 & zext(Uimm8_0813)) != 0; + Pd2 = Pd2 & (notClr * 0xff); + build EndPacket; +} + +# (v2,12) bitsclr -- "Pd4 = bitsclr ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 1 1 1 1 0 0 s s s s s P P + t t t t t + + + + + + d d + +:bitsclr Pd2,rs5,rt5 EndPacket is iclass=12 & op2127=0x3c & op13=0 & op0207=0 & rs5 & rt5 & Pd2 & $(END_PACKET) { + isClr:1 = (rs5 & rt5) == 0; + Pd2 = Pd2 & (isClr * 0xff); + build EndPacket; +} + +# (v4,12) bitsclr -- "Pd4 = ! bitsclr ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 1 1 1 1 0 1 s s s s s P P + t t t t t + + + + + + d d + +:bitsclr! Pd2,rs5,rt5 EndPacket is iclass=12 & op2127=0x3d & op13=0 & op0207=0 & rs5 & rt5 & Pd2 & $(END_PACKET) { + notClr:1 = (rs5 & rt5) != 0; + Pd2 = Pd2 & (notClr * 0xff); + build EndPacket; +} + +# (v4,8) bitsplit -- "Rdd32 = bitsplit ( Rs32 , #u5 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 0 0 0 1 1 0 s s s s s P P 0 i i i i i 1 0 + d d d d d + +:bitsplit Rdd5,rs5,Uimm8_0812 EndPacket is iclass=8 & op2127=0x46 & op13=0 & op0507=4 & Rdd5 & rdd5h_ & rd5_ & rs5 & Uimm8_0812 & $(END_PACKET) { + build Rdd5; # build Rdd5 and assign hi/lo words separately to aid analysis + rdd5h_ = rs5 >> Uimm8_0812; + mask:4 = ~(-1 << Uimm8_0812); + rd5_ = rs5 & mask; + build EndPacket; +} + +# (v4,13) bitsplit -- "Rdd32 = bitsplit ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 1 0 0 + + 1 s s s s s P P + t t t t t + + + d d d d d + +:bitsplit Rdd5,rs5,rt5 EndPacket is iclass=13 & op2127=0x21 & op13=0 & op0507=0 & Rdd5 & rdd5h_ & rd5_ & rs5 & rt5 & $(END_PACKET) { + build Rdd5; # build Rdd5 and assign hi/lo words separately to aid analysis + cnt:4 = rt5 & 0x1f; + rdd5h_ = rs5 >> cnt; + mask:4 = ~(-1 << cnt); + rd5_ = rs5 & mask; + build EndPacket; +} + +# (v2,12) bitsset -- "Pd4 = bitsset ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 1 1 1 0 1 0 s s s s s P P + t t t t t + + + + + + d d + +:bitsset Pd2,rs5,rt5 EndPacket is iclass=12 & op2127=0x3a & op13=0 & op0207=0 & rs5 & rt5 & Pd2 & $(END_PACKET) { + isSet:1 = (rs5 & rt5) == rt5; + Pd2 = Pd2 & (isSet * 0xff); + build EndPacket; +} + +# (v4,12) bitsset -- "Pd4 = ! bitsset ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 1 1 1 0 1 1 s s s s s P P + t t t t t + + + + + + d d + +:bitsset! Pd2,rs5,rt5 EndPacket is iclass=12 & op2127=0x3b & op13=0 & op0207=0 & rs5 & rt5 & Pd2 & $(END_PACKET) { + notSet:1 = (rs5 & rt5) != rt5; + Pd2 = Pd2 & (notSet * 0xff); + build EndPacket; +} + +# (v4,13) boundscheck -- "Pd4 = boundscheck ( Rss32 , Rtt32 ) :raw :hi" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 0 0 + + s s s s s P P 1 t t t t t 1 0 1 + + + d d + +:boundscheck":raw:hi" Pd2,rss5,rtt5 EndPacket is iclass=13 & op2127=0x10 & op13=1 & op0207=0x28 & rss5 & rtt5 & Pd2 & $(END_PACKET) { + upper:4 = rtt5(4); + lower:4 = rtt5:4; + src:4 = rss5(4); + # TODO: unclear if comparison should be signed or unsigned + bool:1 = (src >= lower) && (src < upper); + Pd2 = Pd2 & (bool * 0xff); + build EndPacket; +} + +# (v4,13) boundscheck -- "Pd4 = boundscheck ( Rss32 , Rtt32 ) :raw :lo" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 0 0 + + s s s s s P P 1 t t t t t 1 0 0 + + + d d + +:boundscheck":raw:lo" Pd2,rss5,rtt5 EndPacket is iclass=13 & op2127=0x10 & op13=1 & op0207=0x20 & rss5 & rtt5 & Pd2 & $(END_PACKET) { + upper:4 = rtt5(4); + lower:4 = rtt5:4; + src:4 = rss5:4; + # TODO: unclear if comparison should be signed or unsigned + bool:1 = (src >= lower) && (src < upper); + Pd2 = Pd2 & (bool * 0xff); + build EndPacket; +} + +# (v2,8) brev -- "Rd32 = brev ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 1 0 0 0 1 0 s s s s s P P + + + + + + 1 1 0 d d d d d + +:brev Rd5,rs5 EndPacket is iclass=8 & op2127=0x62 & op0513=0x06 & Rd5 & rs5 & $(END_PACKET) { + Rd5 = bitReverse(rs5); + build EndPacket; +} + +# (v4,8) brev -- "Rdd32 = brev ( Rss32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 0 0 0 1 1 + s s s s s P P + + + + + + 1 1 0 d d d d d + +:brev Rdd5,rss5 EndPacket is iclass=8 & op2127=0x06 & op0513=0x06 & Rdd5 & rss5 & $(END_PACKET) { + Rdd5 = bitReverse(rss5); + build EndPacket; +} + +# (v2,6) brkpt -- "brkpt" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 1 1 0 0 0 0 1 - - - - - P P - - - - - - 0 0 0 - - - - - + +define pcodeop brkpt; + +:brkpt EndPacket is iclass=6 & op2127=0x61 & op0507=0 & $(END_PACKET) { + brkpt(); + build EndPacket; +} + +# (v2,5) call -- "call #r22:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 1 1 0 1 i i i i i i i i i P P i i i i i i i i i i i i i 0 + +:call RelDest22x EndPacket is iclass=5 & op2527=5 & op0=0 & RelDest22x & $(END_PACKET) { + build EndPacket; + <> + LR = ReturnAddr; + call RelDest22x; +} + +# (v2,5) call -- "if ( Pu4 ) call #r15:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 1 1 1 0 1 i i 0 i i i i i P P i 0 0 + u u i i i i i i i + +# +# (v2,5) call -- "if ( ! Pu4 ) call #r15:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 1 1 1 0 1 i i 1 i i i i i P P i 0 0 + u u i i i i i i i + + +:call^FlowCondUU RelDest15x EndPacket is iclass=5 & op2427=0xd & op1112=0 & op10=0 & op0=0 & FlowCondUU & RelDest15x & $(END_PACKET) { + build FlowCondUU; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + LR = ReturnAddr; + call RelDest15x; + +} + +# (v2,5) callr -- "callr Rs32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 1 0 0 0 0 1 0 1 s s s s s P P + + + + + + + + + + + + + + + +:callr rs5 EndPacket is iclass=5 & op2127=0x05 & op0013=0 & rs5 & $(END_PACKET) { + dest:4 = rs5; + build EndPacket; + <> + LR = ReturnAddr; + call [dest]; +} + +# callrh -- "callrh Rs32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 1 0 0 0 0 1 1 0 s s s s s P P + + + + + + + + + + + + + + + +:callrh rs5 EndPacket is iclass=5 & op2127=0x06 & op0013=0 & rs5 & $(END_PACKET) { + dest:4 = rs5; + build EndPacket; + <> + LR = ReturnAddr; + call [dest]; +} + +# (v2,5) callr -- "if ( Pu4 ) callr Rs32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 1 0 0 0 1 0 0 0 s s s s s P P + + + + u u + + + + + + + + +# +# (v2,5) callr -- "if ( ! Pu4 ) callr Rs32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 1 0 0 0 1 0 0 1 s s s s s P P + + + + u u + + + + + + + + + +:callr^FlowCondUU rs5 EndPacket is iclass=5 & op2227=0x04 & op1013=0 & op0007=0 & rs5 & FlowCondUU & $(END_PACKET) { + dest:4 = rs5; + build FlowCondUU; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + LR = ReturnAddr; + call [dest]; + +} + +# (v2,6) ciad -- "ciad ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 0 1 0 0 0 0 0 s s s s s P P + + + + + + 0 1 1 + + + + + + +:ciad rs5 EndPacket is iclass=6 & op2127=0x20 & op0507=3 & rs5 & $(END_PACKET) { + S22 = S22 & ~(rs5); + build EndPacket; +} + +# (v2,8) cl0 -- "Rd32 = cl0 ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 1 0 0 0 0 0 s s s s s P P + + + + + + 1 0 1 d d d d d + +:cl0 Rd5,rs5 EndPacket is iclass=8 & op2127=0x60 & op0507=5 & rs5 & Rd5 & $(END_PACKET) { + Rd5 = lzcount(rs5); + build EndPacket; +} + +# (v2,8) cl0 -- "Rd32 = cl0 ( Rss32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 0 0 0 0 1 0 s s s s s P P + + + + + + 0 1 0 d d d d d + +:cl0 Rd5,rss5 EndPacket is iclass=8 & op2127=0x42 & op0507=2 & rss5 & Rd5 & $(END_PACKET) { + Rd5 = lzcount(rss5); + build EndPacket; +} + +# (v2,8) cl1 -- "Rd32 = cl1 ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 1 0 0 0 0 0 s s s s s P P + + + + + + 1 1 0 d d d d d + +:cl1 Rd5,rs5 EndPacket is iclass=8 & op2127=0x60 & op0507=6 & rs5 & Rd5 & $(END_PACKET) { + Rd5 = lzcount(~rs5); + build EndPacket; +} + +# (v2,8) cl1 -- "Rd32 = cl1 ( Rss32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 0 0 0 0 1 0 s s s s s P P + + + + + + 1 0 0 d d d d d + +:cl1 Rd5,rss5 EndPacket is iclass=8 & op2127=0x42 & op0507=4 & rss5 & Rd5 & $(END_PACKET) { + Rd5 = lzcount(~rss5); + build EndPacket; +} + +# (v2,8) clb -- "Rd32 = clb ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 1 0 0 0 0 0 s s s s s P P + + + + + + 1 0 0 d d d d d + +:clb Rd5,rs5 EndPacket is iclass=8 & op2127=0x60 & op0507=4 & rs5 & Rd5 & $(END_PACKET) { + Rd5 = countLeadingBits(rs5); + build EndPacket; +} + +# (v2,8) clb -- "Rd32 = clb ( Rss32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 0 0 0 0 1 0 s s s s s P P + + + + + + 0 0 0 d d d d d + +:clb Rd5,rss5 EndPacket is iclass=8 & op2127=0x42 & op0507=0 & rss5 & Rd5 & $(END_PACKET) { + Rd5 = countLeadingBits(rss5); + build EndPacket; +} + +# (v66,8) clip -- "Rd32 = clip ( Rs32 , #u5 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 0 0 0 1 1 0 s s s s s P P 0 + + + + + 1 0 1 d d d d d + +define pcodeop clip; +:clip Rd5,rs5,Uimm8_0812 EndPacket is iclass=8 & op2127=0x46 & op13=0 & op0507=5 & rs5 & Rd5 & Uimm8_0812 & $(END_PACKET) { + Rd5 = clip(rs5, Uimm8_0812); + build EndPacket; +} + +# (v2,8) clrbit -- "Rd32 = clrbit ( Rs32 , #u5 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 1 0 0 1 1 0 s s s s s P P 0 i i i i i 0 0 1 d d d d d + +:clrbit Rd5,rs5,Uimm8_0812 EndPacket is iclass=8 & op2127=0x66 & op13=0 & op0507=1 & Rd5 & rs5 & Uimm8_0812 & $(END_PACKET) { + mask:4 = 1 << Uimm8_0812; + Rd5 = rs5 & ~mask; + build EndPacket; +} + +# (v2,12) clrbit -- "Rd32 = clrbit ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 1 1 0 1 0 + s s s s s P P + t t t t t 0 1 + d d d d d + +:clrbit Rd5,rs5,rt5 EndPacket is iclass=12 & op2127=0x34 & op13=0 & op0507=2 & Rd5 & rs5 & rt5 & $(END_PACKET) { + mask:4 = 1 << rt5; + Rd5 = rs5 & ~mask; + build EndPacket; +} + +# (v2,7) cmp.eq -- "Pd4 = cmp.eq ( Rs32 , #s10x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 1 0 1 0 1 0 0 i s s s s s P P i i i i i i i i i 0 0 0 d d + +:cmp.eq Pd2,rs5,Simm32_21_0513x EndPacket is iclass=7 & op2227=0x14 & op0204=0 & rs5 & Simm32_21_0513x & Pd2 & $(END_PACKET) { + bool:1 = (rs5 == Simm32_21_0513x); + Pd2 = Pd2 & (bool * 0xff); + build EndPacket; +} + +# (v4,7) cmp.eq -- "Pd4 = ! cmp.eq ( Rs32 , #s10x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 1 0 1 0 1 0 0 i s s s s s P P i i i i i i i i i 1 0 0 d d + +:cmp.eq! Pd2,rs5,Simm32_21_0513x EndPacket is iclass=7 & op2227=0x14 & op0204=4 & rs5 & Simm32_21_0513x & Pd2 & $(END_PACKET) { + bool:1 = (rs5 != Simm32_21_0513x); + Pd2 = Pd2 & (bool * 0xff); + build EndPacket; +} + +# (v2,15) cmp.eq -- "Pd4 = cmp.eq ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 1 0 0 1 0 + 0 0 s s s s s P P + t t t t t + + + 0 0 0 d d + +:cmp.eq Pd2,rs5,rt5 EndPacket is iclass=15 & op2127=0x10 & op13=0 & op0207=0 & rs5 & rt5 & Pd2 & $(END_PACKET) { + bool:1 = (rs5 == rt5); + Pd2 = Pd2 & (bool * 0xff); + build EndPacket; +} + +# (v4,15) cmp.eq -- "Pd4 = ! cmp.eq ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 1 0 0 1 0 + 0 0 s s s s s P P + t t t t t + + + 1 0 0 d d + +:cmp.eq! Pd2,rs5,rt5 EndPacket is iclass=15 & op2127=0x10 & op13=0 & op0207=4 & rs5 & rt5 & Pd2 & $(END_PACKET) { + bool:1 = (rs5 != rt5); + Pd2 = Pd2 & (bool * 0xff); + build EndPacket; +} + +# (v2,13) cmp.eq -- "Pd4 = cmp.eq ( Rss32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 0 1 + + s s s s s P P + t t t t t 0 0 + + + + d d + +:cmp.eq Pd2,rss5,rtt5 EndPacket is iclass=13 & op2127=0x14 & op13=0 & op0207=0 & rss5 & rtt5 & Pd2 & $(END_PACKET) { + bool:1 = (rss5 == rtt5); + Pd2 = Pd2 & (bool * 0xff); + build EndPacket; +} + +# (v2,7) cmp.gt -- "Pd4 = cmp.gt ( Rs32 , #s10x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 1 0 1 0 1 0 1 i s s s s s P P i i i i i i i i i 0 0 0 d d + +:cmp.gt Pd2,rs5,Simm32_21_0513x EndPacket is iclass=7 & op2227=0x15 & op0204=0 & rs5 & Simm32_21_0513x & Pd2 & $(END_PACKET) { + bool:1 = (rs5 s> Simm32_21_0513x); + Pd2 = Pd2 & (bool * 0xff); + build EndPacket; +} + +# (v4,7) cmp.gt -- "Pd4 = ! cmp.gt ( Rs32 , #s10x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 1 0 1 0 1 0 1 i s s s s s P P i i i i i i i i i 1 0 0 d d + +:cmp.gt! Pd2,rs5,Simm32_21_0513x EndPacket is iclass=7 & op2227=0x15 & op0204=4 & rs5 & Simm32_21_0513x & Pd2 & $(END_PACKET) { + bool:1 = (rs5 s<= Simm32_21_0513x); + Pd2 = Pd2 & (bool * 0xff); + build EndPacket; +} + +# (v2,15) cmp.gt -- "Pd4 = cmp.gt ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 1 0 0 1 0 + 1 0 s s s s s P P + t t t t t + + + 0 0 0 d d + +:cmp.gt Pd2,rs5,rt5 EndPacket is iclass=15 & op2127=0x12 & op13=0 & op0207=0 & rs5 & rt5 & Pd2 & $(END_PACKET) { + bool:1 = (rs5 s> rt5); + Pd2 = Pd2 & (bool * 0xff); + build EndPacket; +} + +# (v4,15) cmp.gt -- "Pd4 = ! cmp.gt ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 1 0 0 1 0 + 1 0 s s s s s P P + t t t t t + + + 1 0 0 d d + +:cmp.gt! Pd2,rs5,rt5 EndPacket is iclass=15 & op2127=0x12 & op13=0 & op0207=4 & rs5 & rt5 & Pd2 & $(END_PACKET) { + bool:1 = (rs5 s<= rt5); + Pd2 = Pd2 & (bool * 0xff); + build EndPacket; +} + +# (v2,13) cmp.gt -- "Pd4 = cmp.gt ( Rss32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 0 1 + + s s s s s P P + t t t t t 0 1 + + + + d d + +:cmp.gt Pd2,rss5,rtt5 EndPacket is iclass=13 & op2127=0x14 & op13=0 & op0207=0x10 & rss5 & rtt5 & Pd2 & $(END_PACKET) { + bool:1 = (rss5 s> rtt5); + Pd2 = Pd2 & (bool * 0xff); + build EndPacket; +} + +# (v2,7) cmp.gtu -- "Pd4 = cmp.gtu ( Rs32 , #u9x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 1 0 1 0 1 1 0 0 s s s s s P P i i i i i i i i i 0 0 0 d d + +:cmp.gtu Pd2,rs5,Uimm32_0513x EndPacket is iclass=7 & op2127=0x2c & op0204=0 & rs5 & Uimm32_0513x & Pd2 & $(END_PACKET) { + bool:1 = (rs5 > Uimm32_0513x); + Pd2 = Pd2 & (bool * 0xff); + build EndPacket; +} + +# (v4,7) cmp.gtu -- "Pd4 = ! cmp.gtu ( Rs32 , #u9x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 1 0 1 0 1 1 0 0 s s s s s P P i i i i i i i i i 1 0 0 d d + +:cmp.gtu! Pd2,rs5,Uimm32_0513x EndPacket is iclass=7 & op2127=0x2c & op0204=4 & rs5 & Uimm32_0513x & Pd2 & $(END_PACKET) { + bool:1 = (rs5 <= Uimm32_0513x); + Pd2 = Pd2 & (bool * 0xff); + build EndPacket; +} + +# (v2,15) cmp.gtu -- "Pd4 = cmp.gtu ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 1 0 0 1 0 + 1 1 s s s s s P P + t t t t t + + + 0 0 0 d d + +:cmp.gtu Pd2,rs5,rt5 EndPacket is iclass=15 & op2127=0x13 & op0207=0 & rs5 & rt5 & Pd2 & $(END_PACKET) { + bool:1 = (rs5 > rt5); + Pd2 = Pd2 & (bool * 0xff); + build EndPacket; +} + +# (v4,15) cmp.gtu -- "Pd4 = ! cmp.gtu ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 1 0 0 1 0 + 1 1 s s s s s P P + t t t t t + + + 1 0 0 d d + +:cmp.gtu! Pd2,rs5,rt5 EndPacket is iclass=15 & op2127=0x13 & op0207=4 & rs5 & rt5 & Pd2 & $(END_PACKET) { + bool:1 = (rs5 <= rt5); + Pd2 = Pd2 & (bool * 0xff); + build EndPacket; +} + +# (v2,13) cmp.gtu -- "Pd4 = cmp.gtu ( Rss32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 0 1 + + s s s s s P P + t t t t t 1 0 + + + + d d + +:cmp.gtu Pd2,rss5,rtt5 EndPacket is iclass=13 & op2127=0x14 & op13=0 & op0207=0x20 & rss5 & rtt5 & Pd2 & $(END_PACKET) { + bool:1 = (rss5 > rtt5); + Pd2 = Pd2 & (bool * 0xff); + build EndPacket; +} + +# (v4,7) cmp.eq -- "Rd32 = cmp.eq ( Rs32 , #s8x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 1 0 0 1 1 + 1 0 s s s s s P P 1 i i i i i i i i d d d d d + +:cmp.eq Rd5,rs5,Simm32_0512x EndPacket is iclass=7 & op2127=0x1a & op13=1 & rs5 & Rd5 & Simm32_0512x & $(END_PACKET) { + # TODO: Verify output value - assuming 0/1 boolean + Rd5 = zext(rs5 == Simm32_0512x); + build EndPacket; +} + +# (v4,7) cmp.eq -- "Rd32 = ! cmp.eq ( Rs32 , #s8x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 1 0 0 1 1 + 1 1 s s s s s P P 1 i i i i i i i i d d d d d + +:cmp.eq! Rd5,rs5,Simm32_0512x EndPacket is iclass=7 & op2127=0x1b & op13=1 & rs5 & Rd5 & Simm32_0512x & $(END_PACKET) { + # TODO: Verify output value - assuming 0/1 boolean + Rd5 = zext(rs5 != Simm32_0512x); + build EndPacket; +} + +# (v4,15) cmp.eq -- "Rd32 = cmp.eq ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 1 0 0 1 1 0 1 0 s s s s s P P + t t t t t + + + d d d d d + +:cmp.eq Rd5,rs5,rt5 EndPacket is iclass=15 & op2127=0x1a & op13=0 & op0507=0 & rs5 & rt5 & Rd5 & $(END_PACKET) { + Rd5 = zext(rs5 == rt5); + build EndPacket; +} + +# (v4,15) cmp.eq -- "Rd32 = ! cmp.eq ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 1 0 0 1 1 0 1 1 s s s s s P P + t t t t t + + + d d d d d + +:cmp.eq! Rd5,rs5,rt5 EndPacket is iclass=15 & op2127=0x1b & op13=0 & op0507=0 & rs5 & rt5 & Rd5 & $(END_PACKET) { + Rd5 = zext(rs5 != rt5); + build EndPacket; +} + +# (v4,13) cmpb.eq -- "Pd4 = cmpb.eq ( Rs32 , #u8 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 1 1 0 1 + 0 0 s s s s s P P + i i i i i i i i 0 0 + d d + +:cmpb.eq Pd2,rs5,Uimm8_0512 EndPacket is iclass=13 & op2127=0x68 & op13=0 & op0204=0 & rs5 & Uimm8_0512 & Pd2 & $(END_PACKET) { + bool:1 = (rs5:1 == Uimm8_0512); + Pd2 = Pd2 & (bool * 0xff); + build EndPacket; +} + +# (v4,12) cmpb.eq -- "Pd4 = cmpb.eq ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 1 1 1 1 1 + s s s s s P P + t t t t t 1 1 0 + + + d d + +:cmpb.eq Pd2,rs5,rt5 EndPacket is iclass=12 & op2127=0x3e & op13=0 & op0207=0x30 & rs5 & rt5 & Pd2 & $(END_PACKET) { + bool:1 = (rs5:1 == rt5:1); + Pd2 = Pd2 & (bool * 0xff); + build EndPacket; +} + +# (v4,13) cmpb.gt -- "Pd4 = cmpb.gt ( Rs32 , #s8 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 1 1 0 1 + 0 1 s s s s s P P + i i i i i i i i 0 0 + d d + +:cmpb.gt Pd2,rs5,Simm8_0512 EndPacket is iclass=13 & op2127=0x69 & op13=0 & op0204=0 & rs5 & Simm8_0512 & Pd2 & $(END_PACKET) { + bool:1 = (rs5:1 s> Simm8_0512); + Pd2 = Pd2 & (bool * 0xff); + build EndPacket; +} + +# (v4,12) cmpb.gt -- "Pd4 = cmpb.gt ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 1 1 1 1 1 + s s s s s P P + t t t t t 0 1 0 + + + d d + +:cmpb.gt Pd2,rs5,rt5 EndPacket is iclass=12 & op2127=0x3e & op13=0 & op0207=0x10 & rs5 & rt5 & Pd2 & $(END_PACKET) { + bool:1 = (rs5:1 s> rt5:1); + Pd2 = Pd2 & (bool * 0xff); + build EndPacket; +} + +# (v4,13) cmpb.gtu -- "Pd4 = cmpb.gtu ( Rs32 , #u7x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 1 1 0 1 + 1 0 s s s s s P P + 0 i i i i i i i 0 0 + d d + +:cmpb.gtu Pd2,rs5,Uimm8_0511x EndPacket is iclass=13 & op2127=0x6a & op1213=0 & op0204=0 & rs5 & Uimm8_0511x & Pd2 & $(END_PACKET) { + bool:1 = (rs5:1 > Uimm8_0511x); + Pd2 = Pd2 & (bool * 0xff); + build EndPacket; +} + +# (v4,12) cmpb.gtu -- "Pd4 = cmpb.gtu ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 1 1 1 1 1 + s s s s s P P + t t t t t 1 1 1 + + + d d + +:cmpb.gtu Pd2,rs5,rt5 EndPacket is iclass=12 & op2127=0x3e & op13=0 & op0207=0x38 & rs5 & rt5 & Pd2 & $(END_PACKET) { + bool:1 = (rs5:1 > rt5:1); + Pd2 = Pd2 & (bool * 0xff); + build EndPacket; +} + +# (v4,13) cmph.eq -- "Pd4 = cmph.eq ( Rs32 , #s8x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 1 1 0 1 + 0 0 s s s s s P P + i i i i i i i i 0 1 + d d + +:cmph.eq Pd2,rs5,Simm16_0512x EndPacket is iclass=13 & op2127=0x68 & op13=0 & op0204=2 & rs5 & Simm16_0512x & Pd2 & $(END_PACKET) { + bool:1 = (rs5:2 == Simm16_0512x); + Pd2 = Pd2 & (bool * 0xff); + build EndPacket; +} + +# (v4,12) cmph.eq -- "Pd4 = cmph.eq ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 1 1 1 1 1 + s s s s s P P + t t t t t 0 1 1 + + + d d + +:cmph.eq Pd2,rs5,rt5 EndPacket is iclass=12 & op2127=0x3e & op13=0 & op0207=0x18 & rs5 & rt5 & Pd2 & $(END_PACKET) { + bool:1 = (rs5:2 == rt5:2); + Pd2 = Pd2 & (bool * 0xff); + build EndPacket; +} + +# (v4,13) cmph.gt -- "Pd4 = cmph.gt ( Rs32 , #s8x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 1 1 0 1 + 0 1 s s s s s P P + i i i i i i i i 0 1 + d d + +:cmph.gt Pd2,rs5,Simm16_0512x EndPacket is iclass=13 & op2127=0x69 & op13=0 & op0204=2 & rs5 & Simm16_0512x & Pd2 & $(END_PACKET) { + bool:1 = (rs5:2 s> Simm16_0512x); + Pd2 = Pd2 & (bool * 0xff); + build EndPacket; +} + +# (v4,12) cmph.gt -- "Pd4 = cmph.gt ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 1 1 1 1 1 + s s s s s P P + t t t t t 1 0 0 + + + d d + +:cmph.gt Pd2,rs5,rt5 EndPacket is iclass=12 & op2127=0x3e & op13=0 & op0207=0x20 & rs5 & rt5 & Pd2 & $(END_PACKET) { + bool:1 = (rs5:2 s> rt5:2); + Pd2 = Pd2 & (bool * 0xff); + build EndPacket; +} + +# (v4,13) cmph.gtu -- "Pd4 = cmph.gtu ( Rs32 , #u7x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 1 1 0 1 + 1 0 s s s s s P P + 0 i i i i i i i 0 1 + d d + +:cmph.gtu Pd2,rs5,Uimm16_0511x EndPacket is iclass=13 & op2127=0x6a & op1213=0 & op0204=2 & rs5 & Uimm16_0511x & Pd2 & $(END_PACKET) { + bool:1 = (rs5:2 > Uimm16_0511x); + Pd2 = Pd2 & (bool * 0xff); + build EndPacket; +} + +# (v4,12) cmph.gtu -- "Pd4 = cmph.gtu ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 1 1 1 1 1 + s s s s s P P + t t t t t 1 0 1 + + + d d + +:cmph.gtu Pd2,rs5,rt5 EndPacket is iclass=12 & op2127=0x3e & op13=0 & op0207=0x28 & rs5 & rt5 & Pd2 & $(END_PACKET) { + bool:1 = (rs5:2 > rt5:2); + Pd2 = Pd2 & (bool * 0xff); + build EndPacket; +} + +# (v2,14) cmpy -- "Rd32 = cmpy ( Rs32 , Rt32 ) :<<1 :rnd :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 0 1 1 0 1 s s s s s P P + t t t t t 1 1 0 d d d d d + +define pcodeop cmpyX2RndSat; + +:cmpy":<<1:rnd:sat" Rd5,rs5,rt5 EndPacket is iclass=14 & op2127=0x6d & op13=0 & op0507=6 & rs5 & rt5 & Rd5 & $(END_PACKET) { + Rd5 = cmpyX2RndSat(rs5,rt5); + build EndPacket; +} + +# (v2,14) cmpy -- "Rd32 = cmpy ( Rs32 , Rt32 ) :rnd :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 0 1 0 0 1 s s s s s P P + t t t t t 1 1 0 d d d d d + +define pcodeop cmpyRndSat; + +:cmpy":rnd:sat" Rd5,rs5,rt5 EndPacket is iclass=14 & op2127=0x69 & op13=0 & op0507=6 & rs5 & rt5 & Rd5 & $(END_PACKET) { + Rd5 = cmpyRndSat(rs5,rt5); + build EndPacket; +} + +# (v2,14) cmpy -- "Rd32 = cmpy ( Rs32 , Rt32 * ) :<<1 :rnd :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 0 1 1 1 1 s s s s s P P + t t t t t 1 1 0 d d d d d + +:cmpy":<<1:rnd:sat" Rd5,rs5,Rt5Conjugate EndPacket is iclass=14 & op2127=0x6f & op13=0 & op0507=6 & rs5 & Rt5Conjugate & Rd5 & $(END_PACKET) { + Rd5 = cmpyX2RndSat(rs5,Rt5Conjugate); + build EndPacket; +} + +# (v2,14) cmpy -- "Rd32 = cmpy ( Rs32 , Rt32 * ) :rnd :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 0 1 0 1 1 s s s s s P P + t t t t t 1 1 0 d d d d d + +:cmpy":rnd:sat" Rd5,rs5,Rt5Conjugate EndPacket is iclass=14 & op2127=0x6b & op13=0 & op0507=6 & rs5 & Rt5Conjugate & Rd5 & $(END_PACKET) { + Rd5 = cmpyRndSat(rs5,Rt5Conjugate); + build EndPacket; +} + +# (v2,14) cmpy -- "Rdd32 = cmpy ( Rs32 , Rt32 ) :<<1 :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 0 1 1 0 0 s s s s s P P + t t t t t 1 1 0 d d d d d + +define pcodeop cmpyX2Sat; + +:cmpy":<<1:sat" Rdd5,rs5,rt5 EndPacket is iclass=14 & op2127=0x2c & op13=0 & op0507=6 & rs5 & rt5 & Rdd5 & $(END_PACKET) { + Rdd5 = cmpyX2Sat(rs5,rt5); + build EndPacket; +} + +# (v2,14) cmpy -- "Rdd32 = cmpy ( Rs32 , Rt32 ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 0 1 0 0 0 s s s s s P P + t t t t t 1 1 0 d d d d d + +define pcodeop cmpySat; + +:cmpy":sat" Rdd5,rs5,rt5 EndPacket is iclass=14 & op2127=0x28 & op13=0 & op0507=6 & rs5 & rt5 & Rdd5 & $(END_PACKET) { + Rdd5 = cmpySat(rs5,rt5); + build EndPacket; +} + +# (v2,14) cmpy -- "Rdd32 = cmpy ( Rs32 , Rt32 * ) :<<1 :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 0 1 1 1 0 s s s s s P P + t t t t t 1 1 0 d d d d d + +:cmpy":<<1:sat" Rdd5,rs5,Rt5Conjugate EndPacket is iclass=14 & op2127=0x2e & op13=0 & op0507=6 & rs5 & Rt5Conjugate & Rdd5 & $(END_PACKET) { + Rdd5 = cmpyX2Sat(rs5,Rt5Conjugate); + build EndPacket; +} + +# (v2,14) cmpy -- "Rdd32 = cmpy ( Rs32 , Rt32 * ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 0 1 0 1 0 s s s s s P P + t t t t t 1 1 0 d d d d d + +:cmpy":sat" Rdd5,rs5,Rt5Conjugate EndPacket is iclass=14 & op2127=0x2a & op13=0 & op0507=6 & rs5 & Rt5Conjugate & Rdd5 & $(END_PACKET) { + Rdd5 = cmpySat(rs5,Rt5Conjugate); + build EndPacket; +} + +# (v2,14) cmpy -- "Rxx32 += cmpy ( Rs32 , Rt32 ) :<<1 :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 1 1 1 0 0 s s s s s P P + t t t t t 1 1 0 x x x x x + +define pcodeop cmpyX2SatAdd; + +:cmpy+=":<<1:sat" Rdd5,rs5,rt5 EndPacket is iclass=14 & op2127=0x3c & op13=0 & op0507=6 & rs5 & rt5 & rdd5 & Rdd5 & $(END_PACKET) { + Rdd5 = cmpyX2SatAdd(rs5,rt5,rdd5); + build EndPacket; +} + +# (v2,14) cmpy -- "Rxx32 += cmpy ( Rs32 , Rt32 ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 1 1 0 0 0 s s s s s P P + t t t t t 1 1 0 x x x x x + +define pcodeop cmpySatAdd; + +:cmpy+=":sat" Rdd5,rs5,rt5 EndPacket is iclass=14 & op2127=0x38 & op13=0 & op0507=6 & rs5 & rt5 & rdd5 & Rdd5 & $(END_PACKET) { + Rdd5 = cmpySatAdd(rs5,rt5,rdd5); + build EndPacket; +} + +# (v2,14) cmpy -- "Rxx32 += cmpy ( Rs32 , Rt32 * ) :<<1 :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 1 1 1 1 0 s s s s s P P + t t t t t 1 1 0 x x x x x + +:cmpy+=":<<1:sat" Rdd5,rs5,Rt5Conjugate EndPacket is iclass=14 & op2127=0x3e & op13=0 & op0507=6 & rs5 & Rt5Conjugate & rdd5 & Rdd5 & $(END_PACKET) { + Rdd5 = cmpyX2SatAdd(rs5,Rt5Conjugate,rdd5); + build EndPacket; +} + +# (v2,14) cmpy -- "Rxx32 += cmpy ( Rs32 , Rt32 * ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 1 1 0 1 0 s s s s s P P + t t t t t 1 1 0 x x x x x + +:cmpy+=":sat" Rdd5,rs5,Rt5Conjugate EndPacket is iclass=14 & op2127=0x3a & op13=0 & op0507=6 & rs5 & Rt5Conjugate & rdd5 & Rdd5 & $(END_PACKET) { + Rdd5 = cmpySatAdd(rs5,Rt5Conjugate,rdd5); + build EndPacket; +} + +# (v2,14) cmpy -- "Rxx32 -= cmpy ( Rs32 , Rt32 ) :<<1 :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 1 1 1 0 0 s s s s s P P + t t t t t 1 1 1 x x x x x + +define pcodeop cmpyX2SatSub; + +:cmpy-=":<<1:sat" Rdd5,rs5,rt5 EndPacket is iclass=14 & op2127=0x3c & op13=0 & op0507=7 & rs5 & rt5 & rdd5 & Rdd5 & $(END_PACKET) { + Rdd5 = cmpyX2SatSub(rs5,rt5,rdd5); + build EndPacket; +} + +# (v2,14) cmpy -- "Rxx32 -= cmpy ( Rs32 , Rt32 ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 1 1 0 0 0 s s s s s P P + t t t t t 1 1 1 x x x x x + +define pcodeop cmpySatSub; + +:cmpy-=":sat" Rdd5,rs5,rt5 EndPacket is iclass=14 & op2127=0x38 & op13=0 & op0507=7 & rs5 & rt5 & rdd5 & Rdd5 & $(END_PACKET) { + Rdd5 = cmpySatSub(rs5,rt5,rdd5); + build EndPacket; +} + +# (v2,14) cmpy -- "Rxx32 -= cmpy ( Rs32 , Rt32 * ) :<<1 :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 1 1 1 1 0 s s s s s P P + t t t t t 1 1 1 x x x x x + +:cmpy-=":<<1:sat" Rdd5,rs5,Rt5Conjugate EndPacket is iclass=14 & op2127=0x3e & op13=0 & op0507=7 & rs5 & Rt5Conjugate & rdd5 & Rdd5 & $(END_PACKET) { + Rdd5 = cmpyX2SatSub(rs5,Rt5Conjugate,rdd5); + build EndPacket; +} + +# (v2,14) cmpy -- "Rxx32 -= cmpy ( Rs32 , Rt32 * ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 1 1 0 1 0 s s s s s P P + t t t t t 1 1 1 x x x x x + +:cmpy-=":sat" Rdd5,rs5,Rt5Conjugate EndPacket is iclass=14 & op2127=0x3a & op13=0 & op0507=7 & rs5 & Rt5Conjugate & rdd5 & Rdd5 & $(END_PACKET) { + Rdd5 = cmpySatSub(rs5,Rt5Conjugate,rdd5); + build EndPacket; +} + +# (v2,14) cmpyi -- "Rdd32 = cmpyi ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 0 1 0 0 0 s s s s s P P + t t t t t 0 0 1 d d d d d + +:cmpyi Rdd5,rs5,rt5 EndPacket is iclass=14 & op2127=0x28 & op13=0 & op0507=1 & rs5 & rt5 & Rdd5 & $(END_PACKET) { + # Rdd = (Rs.h[1] * Rt.h[0]) - (Rs.h[0] * Rt.h[1]); + rsR:2 = rs5[0,16]; + rtR:2 = rt5[0,16]; + rsI:2 = rs5[16,16]; + rtI:2 = rt5[16,16]; + p1:4 = sext(rsI) * sext(rtR); # (Rs.h[1] * Rt.h[0]) + p2:4 = sext(rsR) * sext(rtI); # (Rs.h[0] * Rt.h[1]) + Rdd5 = sext(p1) + sext(p2); + build EndPacket; +} + +# (v2,14) cmpyi -- "Rxx32 += cmpyi ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 1 1 0 0 0 s s s s s P P + t t t t t 0 0 1 x x x x x + +:cmpyi+= Rdd5,rs5,rt5 EndPacket is iclass=14 & op2127=0x38 & op13=0 & op0507=1 & rs5 & rt5 & Rdd5 & rdd5 & $(END_PACKET) { + # Rdd = (Rs.h[1] * Rt.h[0]) - (Rs.h[0] * Rt.h[1]); + rsR:2 = rs5[0,16]; + rtR:2 = rt5[0,16]; + rsI:2 = rs5[16,16]; + rtI:2 = rt5[16,16]; + p1:4 = sext(rsI) * sext(rtR); # (Rs.h[1] * Rt.h[0]) + p2:4 = sext(rsR) * sext(rtI); # (Rs.h[0] * Rt.h[1]) + Rdd5 = rdd5 + (sext(p1) + sext(p2)); + build EndPacket; +} + +# (v4,12) cmpyiw -- "Rdd32 = cmpyiw ( Rss32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 0 0 1 1 s s s s s P P 0 t t t t t 0 1 0 d d d d d +define pcodeop cmpyiw; + +:cmpyiw Rdd5,rss5,rtt5 EndPacket is iclass=0xe & op2127=0x43 & op13=0 & op0507=2 & rss5 & rtt5 & Rdd5 & $(END_PACKET) { + Rdd5 = cmpyiw(rss5,rtt5); + build EndPacket; +} + +# (v4,12) cmpyiw -- "Rdd32 = cmpyiw ( Rss32 , Rtt32* )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 0 1 1 1 s s s s s P P 0 t t t t t 0 1 0 d d d d d + +:cmpyiw Rdd5,rss5,Rtt5Conjugate^"*" EndPacket is iclass=0xe & op2127=0x47 & op13=0 & op0507=2 & rss5 & Rtt5Conjugate & Rdd5 & $(END_PACKET) { + Rdd5 = cmpyiw(rss5,Rtt5Conjugate); + build EndPacket; +} + +# (v4,12) cmpyiw -- "Rdd32 = cmpyiw ( Rss32 , Rtt32 ) :<<1 :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 1 0 0 1 s s s s s P P 0 t t t t t 0 0 0 d d d d d +define pcodeop cmpyiwX2Sat; + +:cmpyiw":<<1:sat" Rdd5,rss5,rtt5 EndPacket is iclass=0xe & op2127=0x49 & op13=0 & op0507=0 & rss5 & rtt5 & Rdd5 & $(END_PACKET) { + Rdd5 = cmpyiwX2Sat(rss5,rtt5); + build EndPacket; +} + +# (v4,12) cmpyiw -- "Rdd32 = cmpyiw ( Rss32 , Rtt32* ) :<<1 :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 1 0 0 0 s s s s s P P 0 t t t t t 1 0 0 d d d d d + +:cmpyiw":<<1:sat" Rdd5,rss5,Rtt5Conjugate^"*" EndPacket is iclass=0xe & op2127=0x48 & op13=0 & op0507=4 & rss5 & Rtt5Conjugate & Rdd5 & $(END_PACKET) { + Rdd5 = cmpyiwX2Sat(rss5,Rtt5Conjugate); + build EndPacket; +} + +# (v4,12) cmpyiw -- "Rdd32 = cmpyiw ( Rss32 , Rtt32 ) :<<1 :rnd :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 1 1 0 0 s s s s s P P 0 t t t t t 1 0 0 d d d d d +define pcodeop cmpyiwX2RndSat; + +:cmpyiw":<<1:rnd:sat" Rdd5,rss5,rtt5 EndPacket is iclass=0xe & op2127=0x4c & op13=0 & op0507=4 & rss5 & rtt5 & Rdd5 & $(END_PACKET) { + Rdd5 = cmpyiwX2RndSat(rss5,rtt5); + build EndPacket; +} + +# (v4,12) cmpyiw -- "Rdd32 = cmpyiw ( Rss32 , Rtt32* ) :<<1 :rnd :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 1 1 0 1 s s s s s P P 0 t t t t t 0 0 0 d d d d d + +:cmpyiw":<<1:rnd:sat" Rdd5,rss5,Rtt5Conjugate^"*" EndPacket is iclass=0xe & op2127=0x4d & op13=0 & op0507=0 & rss5 & Rtt5Conjugate & Rdd5 & $(END_PACKET) { + Rdd5 = cmpyiwX2RndSat(rss5,Rtt5Conjugate); + build EndPacket; +} + +define pcodeop cmpyiwAdd; +# (v4,12) cmpyiw -- "Rxx32 += cmpyiw ( Rss32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 1 0 0 1 1 s s s s s P P 0 t t t t t 0 1 0 x x x x x +:cmpyiw Rdd5,rss5,rtt5 EndPacket is iclass=0xe & op2127=0x53 & op13=0 & op0507=2 & rss5 & rtt5 & Rdd5 & rdd5 & $(END_PACKET) { + Rdd5 = cmpyiwAdd(rdd5,rss5,rtt5); + build EndPacket; +} + +# (v4,12) cmpyiw -- "Rxx32 += cmpyiw ( Rss32 , Rtt32* )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 1 0 0 1 0 s s s s s P P 0 t t t t t 1 1 0 x x x x x + +:cmpyiw Rdd5,rss5,Rtt5Conjugate^"*" EndPacket is iclass=0xe & op2127=0x52 & op13=0 & op0507=6 & rss5 & Rtt5Conjugate & Rdd5 & rdd5 & $(END_PACKET) { + Rdd5 = cmpyiwAdd(rdd5,rss5,Rtt5Conjugate); + build EndPacket; +} + +# (v5,12) cmpyiwh -- "Rd32 = cmpyiwh ( Rss32 , Rt32 ) :<<1 :rnd :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 1 0 1 - - - s s s s s P P - t t t t t 1 0 0 d d d d d + +define pcodeop cmpyiwhX2RndSat; + +:cmpyiwh":<<1:rnd:sat" Rd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x28 & op13=0 & op0507=4 & rss5 & rt5 & Rd5 & rd5 & $(END_PACKET) { + Rd5 = cmpyiwhX2RndSat(rd5,rss5,rt5); + build EndPacket; +} + +# (v5,12) cmpyiwh -- "Rd32 = cmpyiwh ( Rss32 , Rt32 * ) :<<1 :rnd :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 1 0 1 + + + s s s s s P P + t t t t t 1 0 1 d d d d d + +:cmpyiwh":<<1:rnd:sat" Rd5,rss5,Rt5Conjugate EndPacket is iclass=12 & op2127=0x28 & op13=0 & op0507=5 & rss5 & Rt5Conjugate & Rd5 & rd5 & $(END_PACKET) { + Rd5 = cmpyiwhX2RndSat(rd5,rss5,Rt5Conjugate); + build EndPacket; +} + +# (v2,14) cmpyr -- "Rdd32 = cmpyr ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 0 1 0 0 0 s s s s s P P + t t t t t 0 1 0 d d d d d + +:cmpyr Rdd5,rs5,rt5 EndPacket is iclass=14 & op2127=0x28 & op13=0 & op0507=2 & rs5 & rt5 & Rdd5 & $(END_PACKET) { + # Rdd = (Rs.h[0] * Rt.h[0]) - (Rs.h[1] * Rt.h[1]); + rsR:2 = rs5[0,16]; + rtR:2 = rt5[0,16]; + rsI:2 = rs5[16,16]; + rtI:2 = rt5[16,16]; + p1:4 = sext(rsR) * sext(rtR); # (Rs.h[0] * Rt.h[0]) + p2:4 = sext(rsI) * sext(rtI); # (Rs.h[1] * Rt.h[1]) + Rdd5 = sext(p1) - sext(p2); + build EndPacket; +} + +# (v2,14) cmpyr -- "Rxx32 += cmpyr ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 1 1 0 0 0 s s s s s P P + t t t t t 0 1 0 x x x x x + +:cmpyr+= Rdd5,rs5,rt5 EndPacket is iclass=14 & op2127=0x38 & op13=0 & op0507=2 & rs5 & rt5 & rdd5 & Rdd5 & $(END_PACKET) { + # Rdd += (Rs.h[0] * Rt.h[0]) - (Rs.h[1] * Rt.h[1]); + rsR:2 = rs5[0,16]; + rtR:2 = rt5[0,16]; + rsI:2 = rs5[16,16]; + rtI:2 = rt5[16,16]; + p1:4 = sext(rsR) * sext(rtR); # (Rs.h[0] * Rt.h[0]) + p2:4 = sext(rsI) * sext(rtI); # (Rs.h[1] * Rt.h[1]) + Rdd5 = rdd5 + (sext(p1) - sext(p2)); + build EndPacket; +} + +define pcodeop cmpyrw; +# cmpyrw -- "Rdd32 = cmpyrw ( Rss32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 0 1 0 0 s s s s s P P 0 t t t t t 0 1 0 d d d d d + +:cmpyrw Rdd5,rss5,rtt5 EndPacket is iclass=0xe & op2127=0x44 & op13=0 & op0507=2 & rss5 & rtt5 & Rdd5 & $(END_PACKET) { + Rdd5 = cmpyrw(rss5,rtt5); + build EndPacket; +} + +# cmpyrw -- "Rdd32 = cmpyrw ( Rss32 , Rtt32* )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 0 1 1 0 s s s s s P P 0 t t t t t 0 1 0 d d d d d + +:cmpyrw Rdd5,rss5,Rtt5Conjugate^"*" EndPacket is iclass=0xe & op2127=0x46 & op13=0 & op0507=2 & rss5 & Rtt5Conjugate & Rdd5 & $(END_PACKET) { + Rdd5 = cmpyrw(rss5,Rtt5Conjugate); + build EndPacket; +} + +# cmpyrw -- "Rdd32 = cmpyrw ( Rss32 , Rtt32 ) :<<1 :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 1 0 1 0 s s s s s P P 0 t t t t t 0 0 0 d d d d d +define pcodeop cmpyrwX2Sat; + +:cmpyrw":<<1:sat" Rdd5,rss5,rtt5 EndPacket is iclass=0xe & op2127=0x4a & op13=0 & op0507=0 & rss5 & rtt5 & Rdd5 & $(END_PACKET) { + Rdd5 = cmpyrwX2Sat(rss5,rtt5); + build EndPacket; +} + +# cmpyrw -- "Rdd32 = cmpyrw ( Rss32 , Rtt32* ) :<<1 :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 1 0 1 1 s s s s s P P 0 t t t t t 0 0 0 d d d d d + +:cmpyrw":<<1:sat" Rdd5,rss5,Rtt5Conjugate^"*" EndPacket is iclass=0xe & op2127=0x4b & op13=0 & op0507=0 & rss5 & Rtt5Conjugate & Rdd5 & $(END_PACKET) { + Rdd5 = cmpyrwX2Sat(rss5,Rtt5Conjugate); + build EndPacket; +} + +# cmpyrw -- "Rdd32 = cmpyrw ( Rss32 , Rtt32 ) :<<1 :rnd :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 1 1 1 0 s s s s s P P 0 t t t t t 0 0 0 d d d d d +define pcodeop cmpyrwX2RndSat; + +:cmpyrw":<<1:rnd:sat" Rdd5,rss5,rtt5 EndPacket is iclass=0xe & op2127=0x4e & op13=0 & op0507=0 & rss5 & rtt5 & Rdd5 & $(END_PACKET) { + Rdd5 = cmpyrwX2RndSat(rss5,rtt5); + build EndPacket; +} + +# cmpyrw -- "Rdd32 = cmpyrw ( Rss32 , Rtt32* ) :<<1 :rnd :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 1 1 1 1 s s s s s P P 0 t t t t t 0 0 0 d d d d d + +:cmpyrw":<<1:rnd:sat" Rdd5,rss5,Rtt5Conjugate^"*" EndPacket is iclass=0xe & op2127=0x4f & op13=0 & op0507=0 & rss5 & Rtt5Conjugate & Rdd5 & $(END_PACKET) { + Rdd5 = cmpyrwX2RndSat(rss5,Rtt5Conjugate); + build EndPacket; +} + +# cmpyrw -- "Rxx32 += cmpyrw ( Rss32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 1 0 1 0 0 s s s s s P P 0 t t t t t 0 1 0 x x x x x +define pcodeop cmpyrwAdd; + +:cmpyrw Rdd5,rss5,rtt5 EndPacket is iclass=0xe & op2127=0x54 & op13=0 & op0507=2 & rss5 & rtt5 & Rdd5 & rdd5 & $(END_PACKET) { + Rdd5 = cmpyrwAdd(rdd5,rss5,rtt5); + build EndPacket; +} + +# cmpyrw -- "Rxx32 += cmpyrw ( Rss32 , Rtt32* )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 1 0 1 1 0 s s s s s P P 0 t t t t t 0 1 0 x x x x x + +:cmpyrw Rdd5,rss5,Rtt5Conjugate^"*" EndPacket is iclass=0xe & op2127=0x56 & op13=0 & op0507=2 & rss5 & Rtt5Conjugate & Rdd5 & rdd5 & $(END_PACKET) { + Rdd5 = cmpyrwAdd(rdd5,rss5,Rtt5Conjugate); + build EndPacket; +} + + +# (v4,12) cmpyrwh -- "Rd32 = cmpyrwh ( Rss32 , Rt32 ) :<<1 :rnd :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 1 0 1 + + + s s s s s P P + t t t t t 1 1 0 d d d d d + +define pcodeop cmpyrwhX2RndSat; +:cmpyrwh":<<1:rnd:sat" Rd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x28 & op13=0 & op0507=6 & rss5 & rt5 & Rd5 & rd5 & $(END_PACKET) { + Rd5 = cmpyrwhX2RndSat(rd5,rss5,rt5); + build EndPacket; +} +# (v5,12) cmpyrwh -- "Rd32 = cmpyrwh ( Rss32 , Rt32 * ) :<<1 :rnd :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 1 0 1 + + + s s s s s P P + t t t t t 1 1 1 d d d d d + +:cmpyrwh":<<1:rnd:sat" Rd5,rss5,Rt5Conjugate EndPacket is iclass=12 & op2127=0x28 & op13=0 & op0507=7 & rss5 & Rt5Conjugate & Rd5 & rd5 & $(END_PACKET) { + Rd5 = cmpyrwhX2RndSat(rd5,rss5,Rt5Conjugate); + build EndPacket; +} + +# (v2,15) combine -- "Rd32 = combine ( Rt32.h , Rs32.h )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 1 0 0 1 1 1 0 0 s s s s s P P - t t t t t - - - d d d d d + +:combine Rd5,rt5H,rs5H EndPacket is iclass=0xf & op2127=0x1c & op13=0 & op0507=0 & Rd5 & rt5H & rs5H & $(END_PACKET) { + Rd5 = (zext(rt5H) << 16) + zext(rs5H); + build EndPacket; +} + +# (v2,15) combine -- "Rd32 = combine ( Rt32.h , Rs32.l )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 1 0 0 1 1 1 0 1 s s s s s P P - t t t t t - - - d d d d d + +:combine Rd5,rt5H,rs5L EndPacket is iclass=0xf & op2127=0x1d & op13=0 & op0507=0 & Rd5 & rt5H & rs5L & $(END_PACKET) { + Rd5 = (zext(rt5H) << 16) + zext(rs5L); + build EndPacket; +} + +# (v2,15) combine -- "Rd32 = combine ( Rt32.l , Rs32.h )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 1 0 0 1 1 1 1 0 s s s s s P P - t t t t t - - - d d d d d + +:combine Rd5,rt5L,rs5H EndPacket is iclass=0xf & op2127=0x1e & op13=0 & op0507=0 & Rd5 & rt5L & rs5H & $(END_PACKET) { + Rd5 = (zext(rt5L) << 16) + zext(rs5H); + build EndPacket; +} + +# (v2,15) combine -- "Rd32 = combine ( Rt32.l , Rs32.l )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 1 0 0 1 1 1 1 1 s s s s s P P - t t t t t - - - d d d d d + +:combine Rd5,rt5L,rs5L EndPacket is iclass=0xf & op2127=0x1f & op13=0 & op0507=0 & Rd5 & rt5L & rs5L & $(END_PACKET) { + Rd5 = (zext(rt5L) << 16) + zext(rs5L); + build EndPacket; +} + +# (v4,7) combine -- "Rdd32 = combine ( #s8 , #U6x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 1 1 1 0 0 1 + + I I I I I P P I i i i i i i i i d d d d d + +:combine Rdd5,Simm8_0512,Uimm32_1620_13x EndPacket is iclass=7 & op2127=0x64 & Rdd5 & rdd5h_ & rd5_ & Simm8_0512 & Uimm32_1620_13x & $(END_PACKET) { + build Rdd5; # build Rdd5 and assign hi/lo words separately to aid analysis + rdd5h_ = sext(Simm8_0512); + rd5_ = Uimm32_1620_13x; + build EndPacket; +} + +# (v2,7) combine -- "Rdd32 = combine ( #s8x , #S8 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 1 1 1 0 0 0 I I I I I I I P P I i i i i i i i i d d d d d + +:combine Rdd5,Simm32_0512x,Simm8_1622_13 EndPacket is iclass=7 & op2427=0xc & op23=0 & Rdd5 & rdd5h_ & rd5_ & Simm8_1622_13 & Simm32_0512x & $(END_PACKET) { + build Rdd5; # build Rdd5 and assign hi/lo words separately to aid analysis + rdd5h_ = Simm32_0512x; + rd5_ = sext(Simm8_1622_13); + build EndPacket; +} +# Special case (no immext): Rdd=combine(#-1,#s8) where s8 < 0 (maps to Rdd=#s8) +:assign Rdd5,Simm8_1622_13 EndPacket is iclass=7 & op2427=0xc & op23=0 & Rdd5 & Simm8_1622_13 & s0512=0xff & s22=1 & immext=0 & $(END_PACKET) { + Rdd5 = sext(Simm8_1622_13); + build EndPacket; +} +# Special case (no immext): Rdd=combine(#0,#s8) where s8 > 0 (maps to Rdd=#s8) +:assign Rdd5,Simm8_1622_13 EndPacket is iclass=7 & op2427=0xc & op23=0 & Rdd5 & Simm8_1622_13 & s0512=0 & s22=0 & immext=0 & $(END_PACKET) { + Rdd5 = zext(Simm8_1622_13); + build EndPacket; +} + +# (v4,7) combine -- "Rdd32 = combine ( #s8x , Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 1 0 0 1 1 + 0 1 s s s s s P P 1 i i i i i i i i d d d d d + +:combine Rdd5,Simm32_0512x,rs5 EndPacket is iclass=7 & op2127=0x19 & op13=1 & Rdd5 & rdd5h_ & rd5_ & rs5 & Simm32_0512x & $(END_PACKET) { + build Rdd5; # build Rdd5 and assign hi/lo words separately to aid analysis + rdd5h_ = Simm32_0512x; + rd5_ = rs5; + build EndPacket; +} + +# (v4,7) combine -- "Rdd32 = combine ( Rs32 , #s8x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 1 0 0 1 1 + 0 0 s s s s s P P 1 i i i i i i i i d d d d d + +:combine Rdd5,rs5,Simm32_0512x EndPacket is iclass=7 & op2127=0x18 & op13=1 & Rdd5 & rdd5h_ & rd5_ & rs5 & Simm32_0512x & $(END_PACKET) { + build Rdd5; # build Rdd5 and assign hi/lo words separately to aid analysis + rdd5h_ = rs5; + rd5_ = Simm32_0512x; + build EndPacket; +} + +# (v2,15) combine -- "Rdd32 = combine ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 1 0 1 0 1 0 - - s s s s s P P - t t t t t - - - d d d d d + +:combine Rdd5,rs5,rt5 EndPacket is iclass=0xf & op2427=5 & op2123=0 & op13=0 & op0507=0 & Rdd5 & rdd5h_ & rd5_ & rs5 & rt5 & $(END_PACKET) { + build Rdd5; # build Rdd5 and assign hi/lo words separately to aid analysis + rdd5h_ = rs5; + rd5_ = rt5; + build EndPacket; +} + +# (v2,15) combine -- "if ( Pu4 ) Rdd32 = combine ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 1 1 1 0 1 - - - s s s s s P P 0 t t t t t 0 u u d d d d d +# +# (v2,15) combine -- "if ( ! Pu4 ) Rdd32 = combine ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 1 1 1 0 1 - - - s s s s s P P 0 t t t t t 1 u u d d d d d +# +# (v2,15) combine -- "if ( Pu4 .new ) Rdd32 = combine ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 1 1 1 0 1 - - - s s s s s P P 1 t t t t t 0 u u d d d d d +# +# (v2,15) combine -- "if ( ! Pu4 .new ) Rdd32 = combine ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 1 1 1 0 1 + + + s s s s s P P 1 t t t t t 1 u u d d d d d + +:combine^PuCond0506_N13_S07 rdd5,rs5,rt5 EndPacket is iclass=15 & op2127=0x68 & PuCond0506_N13_S07 & rs5 & rt5 & rdd5 & rdd5h & rd5 & $(END_PACKET) { + hi:4 = rs5; + lo:4 = rt5; + build PuCond0506_N13_S07; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + # Write hi/lo regs separately to simplify analysis + rdd5h = hi; + rd5 = lo; + +} + +# if ([!]Pu4[.new]) Rdd32 = Rs32:Rt32 ( simplification of if ([!]Pu4[.new]) Rdd32 = combine ( Rs32 , Rt32 ) +# where Rs32 is odd and Rt32 is the corresponding low reg +:assign^PuCond0506_N13_S07 rdd5,rtt5 EndPacket is iclass=15 & op2127=0x68 & op16=1 & op8=0 & op0912=op1720 & PuCond0506_N13_S07 & rtt5 & rdd5 & $(END_PACKET) { + tmp:8 = rtt5; + build PuCond0506_N13_S07; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + rdd5 = tmp; + +} + +# (v4,8) cround -- "Rd32 = cround ( Rs32 , #u5 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 1 0 0 1 1 1 s s s s s P P 0 i i i i i 0 0 + d d d d d + +:cround Rd5,rs5,Uimm8_0812 EndPacket is iclass=8 & op2127=0x67 & op13=0 & op0507=0 & Rd5 & rs5 & Uimm8_0812 & $(END_PACKET) { + Rd5 = roundConvergent(rs5, Uimm8_0812); + build EndPacket; +} + +:cround Rdd5,rss5,Uimm8_0813 EndPacket is iclass=8 & op2127=0x67 & op13=0 & op0507=2 & Rdd5 & rss5 & Uimm8_0813 & $(END_PACKET) { + Rdd5 = roundConvergent(rss5, Uimm8_0813); + build EndPacket; +} + + +# (v4,12) cround -- "Rd32 = cround ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 1 1 0 1 1 + s s s s s P P + t t t t t 0 0 + d d d d d + +:cround Rd5,rs5,rt5 EndPacket is iclass=12 & op2127=0x36 & op13=0 & op0507=0 & Rd5 & rs5 & rt5 & $(END_PACKET) { + Rd5 = roundConvergent(rs5, rt5); + build EndPacket; +} + +:cround Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x36 & op13=0 & op0507=2 & Rdd5 & rss5 & rt5 & $(END_PACKET) { + Rdd5 = roundConvergent(rss5, rt5); + build EndPacket; +} + +# (v2,6) crswap -- "crswap ( Rx32 , sgp0 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 0 1 0 1 0 0 0 x x x x x P P + + + + + + + + + + + + + + + +:crswap Rx5,S0 EndPacket is iclass=6 & op2127=0x28 & op0013=0x00 & Rx5 & rx5 & S0 & $(END_PACKET) { + # TODO: Verify semantics - this was a guess based upon mnemonic + tmp:4 = S0; + S0 = rx5; + Rx5 = tmp; + build EndPacket; +} + +# (v4,6) crswap -- "crswap ( Rx32 , sgp1 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 0 1 0 1 0 0 1 x x x x x P P + + + + + + + + + + + + + + + +:crswap Rx5,S1 EndPacket is iclass=6 & op2127=0x29 & op0013=0x00 & Rx5 & rx5 & S1 & $(END_PACKET) { + # TODO: Verify semantics - this was a guess based upon mnemonic + tmp:4 = S1; + S1 = rx5; + Rx5 = tmp; + build EndPacket; +} + +# (v4,6) crswap -- "crswap ( Rxx32 , sgp1:0 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 1 1 0 1 1 + + x x x x x P P + + + + + + + + + 0 0 0 0 0 + +:crswap Rxx5,S1S0 EndPacket is iclass=6 & op2127=0x6c & op0013=0x00 & Rxx5 & rxx5 & S1S0 & $(END_PACKET) { + # TODO: Verify semantics - this was a guess based upon mnemonic + tmp:8 = S1S0; + S1S0 = rxx5; + Rxx5 = tmp; + build EndPacket; +} + +# (v2,6) cswi -- "cswi ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 0 1 0 0 0 0 0 s s s s s P P + + + + + + 0 0 1 + + + + + + +define pcodeop cswi; + +:cswi rs5 EndPacket is iclass=6 & op2127=0x20 & op0013=0x20 & rs5 & $(END_PACKET) { + cswi(rs5); + build EndPacket; +} + +# (v2,8) ct0 -- "Rd32 = ct0 ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 1 0 0 0 1 0 s s s s s P P + + + + + + 1 0 0 d d d d d + +:ct0 Rd5,rs5 EndPacket is iclass=8 & op2127=0x62 & op0513=4 & Rd5 & rs5 & $(END_PACKET) { + Rd5 = countTrailingZeros(rs5); + build EndPacket; +} + +# (v4,8) ct0 -- "Rd32 = ct0 ( Rss32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 0 0 0 1 1 1 s s s s s P P + + + + + + 0 1 + d d d d d + +:ct0 Rd5,rss5 EndPacket is iclass=8 & op2127=0x47 & op0513=2 & Rd5 & rss5 & $(END_PACKET) { + Rd5 = countTrailingZeros(rss5); + build EndPacket; +} + +# (v2,8) ct1 -- "Rd32 = ct1 ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 1 0 0 0 1 0 s s s s s P P + + + + + + 1 0 1 d d d d d + +:ct1 Rd5,rs5 EndPacket is iclass=8 & op2127=0x62 & op0513=5 & Rd5 & rs5 & $(END_PACKET) { + Rd5 = countTrailingOnes(rs5); + build EndPacket; +} + +# (v4,8) ct1 -- "Rd32 = ct1 ( Rss32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 0 0 0 1 1 1 s s s s s P P + + + + + + 1 0 + d d d d d + +:ct1 Rd5,rss5 EndPacket is iclass=8 & op2127=0x47 & op0513=0x04 & Rd5 & rss5 & $(END_PACKET) { + Rd5 = countTrailingOnes(rss5); + build EndPacket; +} + +# (v65,6) ctlbw -- "Rd32 = ctlbw ( Rss32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 1 1 0 0 1 1 0 s s s s s P P 0 t t t t t + + + d d d d d + +define pcodeop ctlbw; +:ctlbw Rd5,rss5,rt5 EndPacket is iclass=6 & op2127=0x66 & op13=0 & rss5 & rt5 & Rd5 & $(END_PACKET) { + Rd5 = ctlbw(rss5, rt5); + build EndPacket; +} + +# (v2,10) dccleana -- "dccleana ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 0 0 0 0 0 0 0 s s s s s P P + + + + + + + + + + + + + + + +define pcodeop dccleana; + +:dccleana rs5 EndPacket is iclass=10 & op2127=0 & op0013=0 & rs5 & $(END_PACKET) { + dccleana(rs5); + build EndPacket; +} + +# (v2,10) dccleanidx -- "dccleanidx ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 0 0 1 0 0 0 1 s s s s s P P + + + + + + + + + + + + + + + +define pcodeop dccleanidx; + +:dccleanidx rs5 EndPacket is iclass=10 & op2127=0x11 & op0013=0 & rs5 & $(END_PACKET) { + dccleanidx(rs5); + build EndPacket; +} + +# (v2,10) dccleaninva -- "dccleaninva ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 0 0 0 0 0 1 0 s s s s s P P + + + + + + + + + + + + + + + +define pcodeop dccleaninva; + +:dccleaninva rs5 EndPacket is iclass=10 & op2127=0x02 & op0013=0 & rs5 & $(END_PACKET) { + dccleaninva(rs5); + build EndPacket; +} + +# (v2,10) dccleaninvidx -- "dccleaninvidx ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 0 0 1 0 0 1 1 s s s s s P P + + + + + + + + + + + + + + + +define pcodeop dccleaninvidx; + +:dccleaninvidx rs5 EndPacket is iclass=10 & op2127=0x13 & op0013=0 & rs5 & $(END_PACKET) { + dccleaninvidx(rs5); + build EndPacket; +} + +# (v2,9) dcfetch -- "dcfetch ( Rs32 + #u11:3 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 0 1 0 0 0 0 0 s s s s s P P 0 + + i i i i i i i i i i i + +FetchAddrRsReld: "("^rs5^"+"^Uimm16_0010_shift3^")" is rs5 & Uimm16_0010_shift3 { ptr:4 = rs5 + zext(Uimm16_0010_shift3); export *[ram]:8 ptr; } +FetchAddrRsReld: "("^rs5^")" is rs5 & i0010=0 { export *[ram]:8 rs5; } + +define pcodeop dcfetch; + +:dcfetch FetchAddrRsReld EndPacket is iclass=9 & op2127=0x20 & op1112=0 & FetchAddrRsReld & $(END_PACKET) { + dcfetch(FetchAddrRsReld); + build EndPacket; +} + +# (v2,10) dcinva -- "dcinva ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 0 0 0 0 0 0 1 s s s s s P P + + + + + + + + + + + + + + + +define pcodeop dcinva; + +:dcinva rs5 EndPacket is iclass=10 & op2127=0x01 & op0013=0 & rs5 & $(END_PACKET) { + dcinva(rs5); + build EndPacket; +} + +# (v2,10) dcinvidx -- "dcinvidx ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 0 0 1 0 0 1 0 s s s s s P P + + + + + + + + + + + + + + + +define pcodeop dcinvidx; + +:dcinvidx rs5 EndPacket is iclass=10 & op2127=0x12 & op0013=0 & rs5 & $(END_PACKET) { + dcinvidx(rs5); + build EndPacket; +} + +# (v2,10) dckill -- "dckill" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 0 0 1 0 0 0 0 + + + + + P P + + + + + + + + + + + + + + + +define pcodeop dckill; + +:dckill EndPacket is iclass=10 & op2127=0x10 & op1620=0 & op0013=0 & $(END_PACKET) { + dckill(); + build EndPacket; +} + +# (v2,10) dctagr -- "Rd32 = dctagr ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 0 1 0 0 0 0 1 s s s s s P P + + + + + + + + + d d d d d + +define pcodeop dctagr; + +:dctagr Rd5,rs5 EndPacket is iclass=10 & op2127=0x21 & op0513=0 & rs5 & Rd5 & $(END_PACKET) { + Rd5 = dctagr(rs5); + build EndPacket; +} + +# (v2,10) dctagw -- "dctagw ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 0 1 0 0 0 0 0 s s s s s P P + t t t t t + + + + + + + + + +define pcodeop dctagw; + +:dctagw rs5,rt5 EndPacket is iclass=10 & op2127=0x20 & op13=0 & op0007=0 & rs5 & rt5 & $(END_PACKET) { + dctagw(rs5,rt5); + build EndPacket; +} + +# (v2,10) dczeroa -- "dczeroa ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 0 0 0 0 1 1 0 s s s s s P P 0 + + + + + + + + + + + + + + +define pcodeop dczeroa; + +:dczeroa rs5 EndPacket is iclass=10 & op2127=0x06 & op0013=0 & rs5 & $(END_PACKET) { + dczeroa(rs5); + build EndPacket; +} + +# (v4,9) dealloc_return -- "dealloc_return" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 0 1 1 0 0 0 0 1 1 1 1 0 P P 0 0 0 0 + + + + + 1 1 1 1 0 + +:dealloc_return EndPacket is iclass=9 & op2127=0x30 & op1620=0x1e & op0013=0x001e & $(END_PACKET) { + build EndPacket; + <> + deallocframe(FP); + return [LR]; +} + +# (v4,9) dealloc_return -- "dealloc_return" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 0 1 1 0 0 0 0 s s s s s P P 0 0 0 0 + + + + + 1 1 1 1 0 + +:dealloc_return rs5 EndPacket is iclass=9 & op2127=0x30 & rs5 & op0013=0x001e & $(END_PACKET) { + build EndPacket; + <> + deallocframe(rs5); + return [LR]; +} + +# dealloc_return -- "if ( Ps4 ) dealloc_return" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 0 1 1 0 0 0 0 1 1 1 1 0 P P 0 1 0 0 s s + + + 1 1 1 1 0 +# +# dealloc_return -- "if ( ! Ps4 ) dealloc_return" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 0 1 1 0 0 0 0 1 1 1 1 0 P P 1 1 0 0 s s + + + 1 1 1 1 0 +# +# dealloc_return:nt -- "if ( Ps4 .new ) dealloc_return:nt" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 0 1 1 0 0 0 0 1 1 1 1 0 P P 0 0 1 0 s s + + + 1 1 1 1 0 +# +# dealloc_return:nt -- "if ( ! Ps4 .new ) dealloc_return:nt" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 0 1 1 0 0 0 0 1 1 1 1 0 P P 1 0 1 0 s s + + + 1 1 1 1 0 +# +# dealloc_return:t -- "if ( Ps4 .new ) dealloc_return:t" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 0 1 1 0 0 0 0 1 1 1 1 0 P P 0 1 1 0 s s + + + 1 1 1 1 0 +# +# dealloc_return:t -- "if ( ! Ps4 .new ) dealloc_return:t" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 0 1 1 0 0 0 0 1 1 1 1 0 P P 1 1 1 0 s s + + + 1 1 1 1 0 + +DRTaken12: is op11=0 & op12=1 { } +DRTaken12: ":t" is op11=1 & op12=1 { } +DRTaken12: ":nt" is op11=1 & op12=0 { } + +:dealloc_return^FlowCond0809_N11_S13^DRTaken12 EndPacket is iclass=9 & op2127=0x30 & op1620=0x1e & (op1112=2 | op11=1) & op0007=0x1e & FlowCond0809_N11_S13 & DRTaken12 & $(END_PACKET) { + build FlowCond0809_N11_S13; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + deallocframe(FP); + return [LR]; + +} + +# (v4,9) dealloc_return -- "if ( Ps4 ) dealloc_return" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 0 1 1 0 0 0 0 s s s s s P P 0 1 0 0 s s + + + 1 1 1 1 0 +# +# (v4,9) dealloc_return -- "if ( ! Ps4 ) dealloc_return" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 0 1 1 0 0 0 0 s s s s s P P 1 1 0 0 s s + + + 1 1 1 1 0 +# +# (v4,9) dealloc_return:nt -- "if ( Ps4 .new ) dealloc_return:nt" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 0 1 1 0 0 0 0 s s s s s P P 0 0 1 0 s s + + + 1 1 1 1 0 +# +# (v4,9) dealloc_return:nt -- "if ( ! Ps4 .new ) dealloc_return:nt" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 0 1 1 0 0 0 0 s s s s s P P 1 0 1 0 s s + + + 1 1 1 1 0 +# +# (v4,9) dealloc_return:t -- "if ( Ps4 .new ) dealloc_return:t" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 0 1 1 0 0 0 0 s s s s s P P 0 1 1 0 s s + + + 1 1 1 1 0 +# +# (v4,9) dealloc_return:t -- "if ( ! Ps4 .new ) dealloc_return:t" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 0 1 1 0 0 0 0 s s s s s P P 1 1 1 0 s s + + + 1 1 1 1 0 + +:dealloc_return^FlowCond0809_N11_S13^DRTaken12 rs5 EndPacket is iclass=9 & op2127=0x30 & rs5 & (op1112=2 | op11=1) & op0007=0x1e & FlowCond0809_N11_S13 & DRTaken12 & $(END_PACKET) { + build FlowCond0809_N11_S13; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + deallocframe(rs5); + return [LR]; + +} + + +# (v2,9) deallocframe -- "deallocframe" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 0 0 0 0 0 0 0 1 1 1 1 0 P P 0 - - - - - - - - 1 1 1 1 0 + +:deallocframe EndPacket is iclass=9 & op2527=0 & op2224=0 & op21=0 & op1620=0x1e & op13=0 & op0512=0 & op0004=0x1e & $(END_PACKET) { + build EndPacket; + <> + deallocframe(FP); +} + +# (v4,12) decbin -- "Rdd32 = decbin ( Rss32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 0 0 1 1 1 + s s s s s P P + t t t t t 1 1 + d d d d d + +define pcodeop decbin; +:decbin Rdd5,rss5,rtt5 EndPacket is iclass=12 & op2127=0x0e & op13=0 & op0507=6 & Rdd5 & rss5 & rtt5 & $(END_PACKET) { + Rdd5 = decbin(rss5, rtt5); + build EndPacket; +} + +# (v2,8) deinterleave -- "Rdd32 = deinterleave ( Rss32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 0 0 0 1 1 + s s s s s P P + + + + + + 1 0 0 d d d d d +define pcodeop deinterleave; +:deinterleave Rdd5,rss5 EndPacket is iclass=8 & op2127=0x06 & op0513=0x04 & Rdd5 & rss5 & $(END_PACKET) { + Rdd5 = deinterleave(rss5); + build EndPacket; +} + +# (v69,6) diag -- "diag ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 0 0 1 0 0 1 0 s s s s s P P + + + + + + 0 0 1 + + + + + + +define pcodeop diag; +:diag rs5 EndPacket is iclass=6 & op2127=0x12 & op0507=1 & rs5 & $(END_PACKET) { + diag(rs5); + build EndPacket; +} + +# (v69,6) diag0 -- "diag0 ( Rss32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 0 0 1 0 0 1 0 s s s s s P P + t t t t t 0 1 0 + + + + + + +define pcodeop diag0; +:diag0 rss5,rtt5 EndPacket is iclass=6 & op2127=0x12 & op0507=2 & rss5 & rtt5 & $(END_PACKET) { + diag0(rss5, rtt5); + build EndPacket; +} + +# (v69,6) diag1 -- "diag1 ( Rss32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 0 0 1 0 0 1 0 s s s s s P P + t t t t t 0 1 1 + + + + + + +define pcodeop diag1; +:diag1 rss5,rtt5 EndPacket is iclass=6 & op2127=0x12 & op0507=3 & rss5 & rtt5 & $(END_PACKET) { + diag1(rss5, rtt5); + build EndPacket; +} + +# (v68,10) dmsyncht -- "Rd32 = dmsyncht" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 0 0 0 0 0 - - - - - P P - - - - - 0 1 1 1 d d d d d + +define pcodeop dmsyncht; +:dmsyncht Rd5 EndPacket is iclass=10 & op2127=0x40 & op0508=7 & Rd5 & $(END_PACKET) { + Rd5 = dmsyncht(); # Rd5=DM0; What is DM0 ? + build EndPacket; +} + +# (v4,8) extract -- "Rd32 = extract ( Rs32 , #u5 , #U5 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 1 0 1 1 I I s s s s s P P 0 i i i i i I I I d d d d d + +:extract Rd5,rs5,Uimm8_0812,Uimm8_2122_0507 EndPacket is iclass=8 & op2327=0x1b & op13=0 & Rd5 & rs5 & Uimm8_0812 & Uimm8_2122_0507 & $(END_PACKET) { + # width: Uimm8_0812 + # offset: Uimm8_2122_0507 + mask:4 = ~(-1 << Uimm8_0812); + tmp:4 = (rs5 >> Uimm8_2122_0507) & mask; + # force sign extension + ext:1 = 32 - Uimm8_0812; + Rd5 = (tmp << ext) >> ext; + build EndPacket; +} + +# (v4,12) extract -- "Rd32 = extract ( Rs32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 1 0 0 1 0 0 + s s s s s P P + t t t t t 0 1 + d d d d d + +:extract Rd5,rs5,rtt5 EndPacket is iclass=12 & op2127=0x48 & op13=0 & op0507=2 & Rd5 & rs5 & rtt5 & rtt5h & rt5 & $(END_PACKET) { + # width: rtt5h (hi-word of rtt5) + # offset: rt5 (lo-word of rtt5) + mask:4 = ~(-1 << rtt5h); + tmp:4 = (rs5 >> rt5) & mask; + # force sign extension + ext:4 = 32 - rtt5h; + Rd5 = (tmp << ext) >> ext; + build EndPacket; +} + +# (v4,8) extract -- "Rdd32 = extract ( Rss32 , #u6 , #U6 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 0 1 0 I I I s s s s s P P i i i i i i I I I d d d d d + +:extract Rdd5,rss5,Uimm8_0813,Uimm8_2123_0507 EndPacket is iclass=8 & op2427=0xa & Rdd5 & rss5 & Uimm8_0813 & Uimm8_2123_0507 & $(END_PACKET) { + # width: Uimm8_0813 + # offset: Uimm8_2123_0507 + mask:8 = ~(-1 << Uimm8_0813); + tmp:8 = (rss5 >> Uimm8_2123_0507) & mask; + # force sign extension + ext:1 = 64 - Uimm8_0813; + Rdd5 = (tmp << ext) >> ext; + build EndPacket; +} + +# (v4,12) extract -- "Rdd32 = extract ( Rss32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 0 0 1 1 1 + s s s s s P P + t t t t t 1 0 + d d d d d + +:extract Rdd5,rss5,rtt5 EndPacket is iclass=12 & op2127=0x0e & op13=0 & op0507=4 & Rdd5 & rss5 & rtt5 & rtt5h & rt5 & $(END_PACKET) { + # width: rtt5h (hi-word of rtt5) + # offset: rt5 (lo-word of rtt5) + mask:8 = ~(-1 << rtt5h); + tmp:8 = (rss5 >> rt5) & mask; + # force sign extension + ext:4 = 64 - rtt5h; + Rdd5 = (tmp << ext) >> ext; + build EndPacket; +} + +# (v2,8) extractu -- "Rd32 = extractu ( Rs32 , #u5 , #U5 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 1 0 1 0 I I s s s s s P P 0 i i i i i I I I d d d d d + +:extractu Rd5,rs5,Uimm8_0812,Uimm8_2122_0507 EndPacket is iclass=8 & op2327=0x1a & op13=0 & Rd5 & rs5 & Uimm8_0812 & Uimm8_2122_0507 & $(END_PACKET) { + # width: Uimm8_0812 + # offset: Uimm8_2122_0507 + mask:4 = ~(-1 << Uimm8_0812); + Rd5 = (rs5 >> Uimm8_2122_0507) & mask; + build EndPacket; +} + +# (v2,12) extractu -- "Rd32 = extractu ( Rs32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 1 0 0 1 0 0 + s s s s s P P + t t t t t 0 0 + d d d d d + +:extractu Rd5,rs5,rtt5 EndPacket is iclass=12 & op2127=0x48 & op13=0 & op0507=0 & Rd5 & rs5 & rtt5 & rtt5h & rt5 & $(END_PACKET) { + # width: rtt5h (hi-word of rtt5) + # offset: rt5 (lo-word of rtt5) + mask:4 = ~(-1 << rtt5h); + Rd5 = (rs5 >> rt5) & mask; + build EndPacket; +} + +# (v2,8) extractu -- "Rdd32 = extractu ( Rss32 , #u6 , #U6 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 0 0 1 I I I s s s s s P P i i i i i i I I I d d d d d + +:extractu Rdd5,rss5,Uimm8_0813,Uimm8_2123_0507 EndPacket is iclass=8 & op2427=1 & Rdd5 & rss5 & Uimm8_0813 & Uimm8_2123_0507 & $(END_PACKET) { + # width: Uimm8_0813 + # offset: Uimm8_2123_0507 + mask:8 = ~(-1 << Uimm8_0813); + Rdd5 = (rss5 >> Uimm8_2123_0507) & mask; + build EndPacket; +} + +# (v2,12) extractu -- "Rdd32 = extractu ( Rss32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 0 0 1 0 0 + s s s s s P P + t t t t t 0 0 + d d d d d + +:extractu Rdd5,rss5,rtt5 EndPacket is iclass=12 & op2127=0x08 & op13=0 & op0507=0 & Rdd5 & rss5 & rtt5 & rtt5h & rt5 & $(END_PACKET) { + # width: rtt5h (hi-word of rtt5) + # offset: rt5 (lo-word of rtt5) + mask:8 = ~(-1 << rtt5h); + Rdd5 = (rss5 >> rt5) & mask; + build EndPacket; +} + +# (v4,6) fastcorner9 -- "Pd4 = fastcorner9 ( Ps4 , Pt4 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 1 0 1 1 0 0 0 0 + + s s P P 1 + + + t t 1 + + 1 + + d d + +define pcodeop fastcorner9; + +:fastcorner9 Pd2,pu1617,pu0809 EndPacket is iclass=6 & op2127=0x58 & op1820=0 & op13=1 & op1012=0 & op0207=0x24 & Pd2 & pu1617 & pu0809 & $(END_PACKET) { + Pd2 = Pd2 & fastcorner9(pu1617,pu0809); + build EndPacket; +} + +# (v4,6) fastcorner9 -- "Pd4 = ! fastcorner9 ( Ps4 , Pt4 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 1 0 1 1 0 0 0 1 + + s s P P 1 + + + t t 1 + + 1 + + d d + +:fastcorner9! Pd2,pu1617,pu0809 EndPacket is iclass=6 & op2127=0x58 & op1820=4 & op13=1 & op1012=0 & op0207=0x24 & Pd2 & pu1617 & pu0809 & $(END_PACKET) { + Pd2 = Pd2 & ~fastcorner9(pu1617,pu0809); + build EndPacket; +} + +# (v4,6) getimask -- "Rd32 = getimask ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 0 1 1 0 0 0 0 s s s s s P P + + + + + + + + + d d d d d + +define pcodeop getimask; + +:getimask Rd5,rs5 EndPacket is iclass=6 & op2127=0x30 & op0513=0 & Rd5 & rs5 & $(END_PACKET) { + Rd5 = getimask(rs5); + build EndPacket; +} + +# (v4,5) hintjr -- "hintjr ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 1 0 0 1 0 1 0 1 s s s s s P P + + + + + + + + + + + + + + + +:hintjr rs5 EndPacket is iclass=5 & op2127=0x15 & op0013=0 & rs5 & $(END_PACKET) { + # TODO: appears in decomp compilation - not sure what it does + build EndPacket; +} + +# (v2,6) iassignr -- "Rd32 = iassignr ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 0 1 1 0 0 1 1 s s s s s P P + + + + + + + + + d d d d d + +define pcodeop iassignr; + +:iassignr Rd5,rs5 EndPacket is iclass=6 & op2127=0x33 & op0513=0 & rs5 & Rd5 & $(END_PACKET) { + Rd5 = iassignr(rs5); + build EndPacket; +} + +# (v2,6) iassignw -- "iassignw ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 0 1 0 0 0 0 0 s s s s s P P + + + + + + 0 1 0 + + + + + + +define pcodeop iassignw; # TODO: What affect does this have + +:iassignw rs5 EndPacket is iclass=6 & op2127=0x20 & op0013=0x40 & rs5 & $(END_PACKET) { + iassignw(rs5); + build EndPacket; +} + +# (v4,5) icdatar -- "Rd32 = icdatar ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 1 0 1 0 1 1 0 1 s s s s s P P + + + + + + + + + d d d d d + +define pcodeop icdatar; + +:icdatar Rd5,rs5 EndPacket is iclass=5 & op2127=0x2d & op0513=0 & rs5 & Rd5 & $(END_PACKET) { + Rd5 = icdatar(rs5); + build EndPacket; +} + +# (v66,5) icdataw -- "icdataw ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 1 0 1 0 1 1 1 0 s s s s s P P + t t t t t + + + + + + + + + +define pcodeop icache_data_write; # TODO: What affect does this have + +:icdataw rs5, rt5 EndPacket is iclass=5 & op2127=0x36 & rs5 & rt5 & $(END_PACKET) { + icache_data_write(rs5, rt5); + build EndPacket; +} + +# (v2,5) icinva -- "icinva ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 1 0 1 1 0 1 1 0 s s s s s P P 0 0 0 + + + + + + + + + + + + +define pcodeop icache_inv_addr; + +:icinva rs5 EndPacket is iclass=5 & op2127=0x36 & op0013=0 & rs5 & $(END_PACKET) { + icache_inv_addr(rs5); + build EndPacket; +} + +# (v2,5) icinvidx -- "icinvidx ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 1 0 1 1 0 1 1 0 s s s s s P P 0 0 1 + + + + + + + + + + + + +define pcodeop icinvidx; # TODO: What affect does this have + +:icinvidx rs5 EndPacket is iclass=5 & op2127=0x36 & op0013=0x800 & rs5 & $(END_PACKET) { + icinvidx(rs5); + build EndPacket; +} + +# (v2,5) ickill -- "ickill" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 1 0 1 1 0 1 1 0 + + + + + P P 0 1 0 + + + + + + + + + + + + +define pcodeop ickill; + +:ickill EndPacket is iclass=5 & op2127=0x36 & op1113=2 & $(END_PACKET) { + ickill(); + build EndPacket; +} + +# (v2,5) ictagr -- "Rd32 = ictagr ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 1 0 1 0 1 1 1 1 s s s s s P P + + + + + + + + + d d d d d + +define pcodeop ictagr; + +:ictagr Rd5,rs5 EndPacket is iclass=5 & op2127=0x2f & op0513=0 & Rd5 & rs5 & $(END_PACKET) { + Rd5 = ictagr(rs5); + build EndPacket; +} + +# (v4,5) ictagw -- "ictagw ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 1 0 1 0 1 1 1 0 s s s s s P P + t t t t t + + + + + + + + + +define pcodeop ictagw; + +:ictagw rs5,rt5 EndPacket is iclass=5 & op2127=0x2e & op13=0 & op0007=0 & Rd5 & rs5 & rt5 & $(END_PACKET) { + ictagw(rs5, rt5); + build EndPacket; +} + +# (v4,0) immext -- "immext ( #u26:6 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 0 i i i i i i i i i i i i P P i i i i i i i i i i i i i i + +Uimm32_1627_0013_6: "#"^val is i1627 & i0013 [ val = (i1627 << 20) | (i0013 << 6); xreg = xreg + 1; globalset(inst_next, xreg); ] { export *[const]:4 val; } + +:immext Uimm32_1627_0013_6 EndPacket is iclass=0 & i1627 & i0013 & Uimm32_1627_0013_6 & $(END_PACKET) + [ immext = (i1627 << 14) | i0013; globalset(inst_next,immext); immexted = 1; globalset(inst_next,immexted);] +{ + # Not sure about behavior - may be NOP and used as immediate value for next instruction + build EndPacket; +} + +# (v2,8) insert -- "Rx32 = insert ( Rs32 , #u5 , #U5 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 1 1 1 0 I I s s s s s P P 0 i i i i i I I I x x x x x + +:insert Rd5,rs5,Uimm8_0812,Uimm8_2122_0507 EndPacket is iclass=8 & op2327=0x1e & op13=0 & Rd5 & rd5 & rs5 & Uimm8_0812 & Uimm8_2122_0507 & $(END_PACKET) { + # width: Uimm8_0812 + # offset: Uimm8_2122_0507 + clrMask:4 = ~(((1 << Uimm8_0812) - 1) << Uimm8_2122_0507); + setMask:4 = (rs5 & ((1 << Uimm8_0812) - 1)) << Uimm8_2122_0507; + Rd5 = (rd5 & clrMask) | setMask; + build EndPacket; +} + +# (v2,12) insert -- "Rx32 = insert ( Rs32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 1 0 0 0 + + + s s s s s P P + t t t t t + + + x x x x x + +:insert Rd5,rs5,rtt5 EndPacket is iclass=12 & op2127=0x40 & op13=0 & op0507=0 & Rd5 & rd5 & rs5 & rtt5 & rtt5h & rt5 & $(END_PACKET) { + # width: rtt5h (hi-word of rtt5) + # offset: rt5 (lo-word of rtt5) + clrMask:4 = ~(((1 << rtt5h) - 1) << rt5); + setMask:4 = (rs5 & ((1 << rtt5h) - 1)) << rt5; + Rd5 = (rd5 & clrMask) | setMask; + build EndPacket; +} + +# (v2,8) insert -- "Rxx32 = insert ( Rss32 , #u6 , #U6 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 0 1 1 I I I s s s s s P P i i i i i i I I I x x x x x + +:insert Rdd5,rss5,Uimm8_0813,Uimm8_2123_0507 EndPacket is iclass=8 & op2427=3 & Rdd5 & rdd5 & rss5 & Uimm8_0813 & Uimm8_2123_0507 & $(END_PACKET) { + # width: Uimm8_0813 + # offset: Uimm8_2123_0507 + clrMask:8 = ~(((1 << Uimm8_0813) - 1) << Uimm8_2123_0507); + setMask:8 = (rss5 & ((1 << Uimm8_0813) - 1)) << Uimm8_2123_0507; + Rdd5 = (rdd5 & clrMask) | setMask; + build EndPacket; +} + +# (v2,12) insert -- "Rxx32 = insert ( Rss32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 1 0 1 0 0 + + s s s s s P P + t t t t t + + + x x x x x + +:insert Rdd5,rss5,rtt5 EndPacket is iclass=12 & op2127=0x50 & op13=0 & op0507=0 & Rdd5 & rdd5 & rss5 & rtt5 & rtt5h & rt5 & $(END_PACKET) { + # width: rtt5h (hi-word of rtt5) + # offset: rt5 (lo-word of rtt5) + clrMask:8 = ~(((1 << rtt5h) - 1) << rt5); + setMask:8 = (rss5 & ((1 << rtt5h) - 1)) << rt5; + Rdd5 = (rdd5 & clrMask) | setMask; + build EndPacket; +} + +# (v2,8) interleave -- "Rdd32 = interleave ( Rss32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 0 0 0 1 1 + s s s s s P P + + + + + + 1 0 1 d d d d d +define pcodeop interleave; +:interleave Rdd5,rss5 EndPacket is iclass=8 & op2127=0x06 & op0513=0x05 & Rdd5 & rss5 & $(END_PACKET) { + Rdd5 = interleave(rss5); + build EndPacket; +} + +# (v2,5) isync -- "isync" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 1 0 1 1 1 1 1 0 0 0 0 0 0 P P 0 - - - 0 0 0 0 0 0 0 0 1 0 + +define pcodeop isync; + +:isync EndPacket is iclass=5 & op2127=0x3e & op1620=0 & $(END_PACKET) { + isync(); + build EndPacket; +} + +# (v2,5) jump -- "jump #r22:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 1 1 0 0 i i i i i i i i i P P i i i i i i i i i i i i i - + +:jump RelDest22x EndPacket is iclass=5 & op2527=4 & op0=0 & RelDest22x & $(END_PACKET) { + build EndPacket; + <> + goto RelDest22x; +} + +# (v2,5) jump -- "if ( Pu4 ) jump #r15:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 1 1 1 0 0 i i 0 i i i i i P P i - 0 - u u i i i i i i i - +# +# (v2,5) jump -- "if ( ! Pu4 ) jump #r15:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 1 1 1 0 0 i i 1 i i i i i P P i - 0 - u u i i i i i i i - + +:jump^FlowCondUU RelDest15x EndPacket is iclass=5 & op2427=0xc & op1112=0 & op10=0 & op0=0 & FlowCondUU & RelDest15x & $(END_PACKET) { + build FlowCondUU; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + goto RelDest15x; + +} + +# (v60,5) jump:nt -- "if ( Pu4 ) jump:nt #r15:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 1 1 1 0 0 i i 0 i i i i i P P i 0 0 + u u i i i i i i i + +# +# (v60,5) jump:nt -- "if ( ! Pu4 ) jump:nt #r15:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 1 1 1 0 0 i i 1 i i i i i P P i 0 0 + u u i i i i i i i + +# +# (v60,5) jump:t -- "if ( Pu4 ) jump:t #r15:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 1 1 1 0 0 i i 0 i i i i i P P i 1 0 + u u i i i i i i i + +# +# (v60,5) jump:t -- "if ( ! Pu4 ) jump:t #r15:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 1 1 1 0 0 i i 1 i i i i i P P i 1 0 + u u i i i i i i i + + +:jump^FlowCondUU^Taken12 RelDest15x EndPacket is iclass=5 & op2427=0xc & op1011=0 & op0=0 & Taken12 & FlowCondUU & RelDest15x & $(END_PACKET) { + build FlowCondUU; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + goto RelDest15x; + +} + +# (v2,5) jump:nt -- "if ( Pu4 .new ) jump:nt #r15:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 1 1 1 0 0 i i 0 i i i i i P P i 0 1 + u u i i i i i i i + +# +# (v2,5) jump:nt -- "if ( ! Pu4 .new ) jump:nt #r15:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 1 1 1 0 0 i i 1 i i i i i P P i 0 1 + u u i i i i i i i + +# +# (v2,5) jump:t -- "if ( Pu4 .new ) jump:t #r15:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 1 1 1 0 0 i i 0 i i i i i P P i 1 1 + u u i i i i i i i + +# +# (v2,5) jump:t -- "if ( ! Pu4 .new ) jump:t #r15:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 1 1 1 0 0 i i 1 i i i i i P P i 1 1 + u u i i i i i i i + + +:jump^FlowCondNewUU^Taken12 RelDest15x EndPacket is iclass=5 & op2427=0xc & op1011=2 & op0=0 & Taken12 & FlowCondNewUU & RelDest15x & $(END_PACKET) { + build FlowCondNewUU; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + goto RelDest15x; + +} + +# (v4,6) jump:nt -- "if ( Rs32 != #0 ) jump:nt #r13:2" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 0 0 0 1 0 0 i s s s s s P P i 0 i i i i i i i i i i i + +# +# (v4,6) jump:t -- "if ( Rs32 != #0 ) jump:t #r13:2" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 0 0 0 1 0 0 i s s s s s P P i 1 i i i i i i i i i i i + +# +# (v4,6) jump:nt -- "if ( Rs32 <= #0 ) jump:nt #r13:2" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 0 0 0 1 1 1 i s s s s s P P i 0 i i i i i i i i i i i + +# +# (v4,6) jump:t -- "if ( Rs32 <= #0 ) jump:t #r13:2" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 0 0 0 1 1 1 i s s s s s P P i 1 i i i i i i i i i i i + +# +# (v4,6) jump:nt -- "if ( Rs32 == #0 ) jump:nt #r13:2" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 0 0 0 1 1 0 i s s s s s P P i 0 i i i i i i i i i i i + +# +# (v4,6) jump:t -- "if ( Rs32 == #0 ) jump:t #r13:2" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 0 0 0 1 1 0 i s s s s s P P i 1 i i i i i i i i i i i + +# +# (v4,6) jump:nt -- "if ( Rs32 >= #0 ) jump:nt #r13:2" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 0 0 0 1 0 1 i s s s s s P P i 0 i i i i i i i i i i i + +# +# (v4,6) jump:t -- "if ( Rs32 >= #0 ) jump:t #r13:2" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 0 0 0 1 0 1 i s s s s s P P i 1 i i i i i i i i i i i + + +JmpRsCmp_2223: "("^rs5^"!=#0)" is op2223=0 & rs5 { tmp:1 = rs5 != 0; export tmp; } +JmpRsCmp_2223: "("^rs5^">=#0)" is op2223=1 & rs5 { tmp:1 = rs5 s>= 0; export tmp; } +JmpRsCmp_2223: "("^rs5^"==#0)" is op2223=2 & rs5 { tmp:1 = rs5 == 0; export tmp; } +JmpRsCmp_2223: "("^rs5^"<=#0)" is op2223=3 & rs5 { tmp:1 = rs5 s<= 0; export tmp; } + +:jump.if^Taken12 JmpRsCmp_2223,RelDest13 EndPacket is iclass=6 & op2427=1 & op0=0 & Taken12 & JmpRsCmp_2223 & RelDest13 & $(END_PACKET) { + build EndPacket; + <> + if (JmpRsCmp_2223 == 0) goto ; + goto RelDest13; + +} + +# (v4,2) jump:nt -- "if ( cmp.eq ( Ns8 .new , #-1 ) ) jump:nt #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 - 1 1 0 0 0 i i - s s s P P 0 - - - - - i i i i i i i - +# +# (v4,2) jump:nt -- "if ( ! cmp.eq ( Ns8 .new , #-1 ) ) jump:nt #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 - 1 1 0 0 1 i i - s s s P P 0 - - - - - i i i i i i i - +# +# (v4,2) jump:t -- "if ( cmp.eq ( Ns8 .new , #-1 ) ) jump:t #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 - 1 1 0 0 0 i i - s s s P P 1 - - - - - i i i i i i i - +# +# (v4,2) jump:t -- "if ( ! cmp.eq ( Ns8 .new , #-1 ) ) jump:t #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 - 1 1 0 0 1 i i - s s s P P 1 - - - - - i i i i i i i - +# +# (v4,2) jump:nt -- "if ( cmp.eq ( Ns8 .new , #U5 ) ) jump:nt #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 - 1 0 0 0 0 i i - s s s P P 0 I I I I I i i i i i i i - +# +# (v4,2) jump:nt -- "if ( ! cmp.eq ( Ns8 .new , #U5 ) ) jump:nt #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 - 1 0 0 0 1 i i - s s s P P 0 I I I I I i i i i i i i - +# +# (v4,2) jump:t -- "if ( cmp.eq ( Ns8 .new , #U5 ) ) jump:t #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 - 1 0 0 0 0 i i - s s s P P 1 I I I I I i i i i i i i - +# +# (v4,2) jump:t -- "if ( ! cmp.eq ( Ns8 .new , #U5 ) ) jump:t #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 - 1 0 0 0 1 i i - s s s P P 1 I I I I I i i i i i i i - +# +# (v4,2) jump:nt -- "if ( cmp.eq ( Ns8 .new , Rt32 ) ) jump:nt #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 - 0 0 0 0 0 i i - s s s P P 0 t t t t t i i i i i i i - +# +# (v4,2) jump:nt -- "if ( ! cmp.eq ( Ns8 .new , Rt32 ) ) jump:nt #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 - 0 0 0 0 1 i i - s s s P P 0 t t t t t i i i i i i i - +# +# (v4,2) jump:t -- "if ( cmp.eq ( Ns8 .new , Rt32 ) ) jump:t #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 - 0 0 0 0 0 i i - s s s P P 1 t t t t t i i i i i i i - +# +# (v4,2) jump:t -- "if ( ! cmp.eq ( Ns8 .new , Rt32 ) ) jump:t #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 - 0 0 0 0 1 i i - s s s P P 1 t t t t t i i i i i i i - +# +# (v4,2) jump:nt -- "if ( cmp.gt ( Ns8 .new , #-1 ) ) jump:nt #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 - 1 1 0 1 0 i i - s s s P P 0 - - - - - i i i i i i i - +# +# (v4,2) jump:nt -- "if ( ! cmp.gt ( Ns8 .new , #-1 ) ) jump:nt #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 - 1 1 0 1 1 i i - s s s P P 0 - - - - - i i i i i i i - +# +# (v4,2) jump:t -- "if ( cmp.gt ( Ns8 .new , #-1 ) ) jump:t #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 - 1 1 0 1 0 i i - s s s P P 1 - - - - - i i i i i i i - +# +# (v4,2) jump:t -- "if ( ! cmp.gt ( Ns8 .new , #-1 ) ) jump:t #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 - 1 1 0 1 1 i i - s s s P P 1 - - - - - i i i i i i i - +# +# (v4,2) jump:nt -- "if ( cmp.gt ( Ns8 .new , #U5 ) ) jump:nt #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 - 1 0 0 1 0 i i - s s s P P 0 I I I I I i i i i i i i - +# +# (v4,2) jump:nt -- "if ( ! cmp.gt ( Ns8 .new , #U5 ) ) jump:nt #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 - 1 0 0 1 1 i i - s s s P P 0 I I I I I i i i i i i i - +# +# (v4,2) jump:t -- "if ( cmp.gt ( Ns8 .new , #U5 ) ) jump:t #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 - 1 0 0 1 0 i i - s s s P P 1 I I I I I i i i i i i i - +# +# (v4,2) jump:t -- "if ( ! cmp.gt ( Ns8 .new , #U5 ) ) jump:t #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 - 1 0 0 1 1 i i - s s s P P 1 I I I I I i i i i i i i - +# +# (v4,2) jump:nt -- "if ( cmp.gt ( Ns8 .new , Rt32 ) ) jump:nt #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 - 0 0 0 1 0 i i - s s s P P 0 t t t t t i i i i i i i - +# +# (v4,2) jump:nt -- "if ( ! cmp.gt ( Ns8 .new , Rt32 ) ) jump:nt #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 - 0 0 0 1 1 i i - s s s P P 0 t t t t t i i i i i i i - +# +# (v4,2) jump:t -- "if ( cmp.gt ( Ns8 .new , Rt32 ) ) jump:t #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 - 0 0 0 1 0 i i - s s s P P 1 t t t t t i i i i i i i - +# +# (v4,2) jump:t -- "if ( ! cmp.gt ( Ns8 .new , Rt32 ) ) jump:t #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 - 0 0 0 1 1 i i - s s s P P 1 t t t t t i i i i i i i - +# +# (v4,2) jump:nt -- "if ( cmp.gt ( Rt32 , Ns8 .new ) ) jump:nt #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 - 0 0 1 1 0 i i - s s s P P 0 t t t t t i i i i i i i - +# +# (v4,2) jump:nt -- "if ( ! cmp.gt ( Rt32 , Ns8 .new ) ) jump:nt #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 - 0 0 1 1 1 i i - s s s P P 0 t t t t t i i i i i i i - +# +# (v4,2) jump:t -- "if ( cmp.gt ( Rt32 , Ns8 .new ) ) jump:t #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 - 0 0 1 1 0 i i - s s s P P 1 t t t t t i i i i i i i - +# +# (v4,2) jump:t -- "if ( ! cmp.gt ( Rt32 , Ns8 .new ) ) jump:t #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 - 0 0 1 1 1 i i - s s s P P 1 t t t t t i i i i i i i - +# +# (v4,2) jump:nt -- "if ( cmp.gtu ( Ns8 .new , #U5 ) ) jump:nt #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 - 1 0 1 0 0 i i - s s s P P 0 I I I I I i i i i i i i - +# +# (v4,2) jump:nt -- "if ( ! cmp.gtu ( Ns8 .new , #U5 ) ) jump:nt #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 - 1 0 1 0 1 i i - s s s P P 0 I I I I I i i i i i i i - +# +# (v4,2) jump:t -- "if ( cmp.gtu ( Ns8 .new , #U5 ) ) jump:t #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 - 1 0 1 0 0 i i - s s s P P 1 I I I I I i i i i i i i - +# +# (v4,2) jump:t -- "if ( ! cmp.gtu ( Ns8 .new , #U5 ) ) jump:t #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 - 1 0 1 0 1 i i - s s s P P 1 I I I I I i i i i i i i - +# +# (v4,2) jump:nt -- "if ( cmp.gtu ( Ns8 .new , Rt32 ) ) jump:nt #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 - 0 0 1 0 0 i i - s s s P P 0 t t t t t i i i i i i i - +# +# (v4,2) jump:nt -- "if ( ! cmp.gtu ( Ns8 .new , Rt32 ) ) jump:nt #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 - 0 0 1 0 1 i i - s s s P P 0 t t t t t i i i i i i i - +# +# (v4,2) jump:t -- "if ( cmp.gtu ( Ns8 .new , Rt32 ) ) jump:t #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 - 0 0 1 0 0 i i - s s s P P 1 t t t t t i i i i i i i - +# +# (v4,2) jump:t -- "if ( ! cmp.gtu ( Ns8 .new , Rt32 ) ) jump:t #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 - 0 0 1 0 1 i i - s s s P P 1 t t t t t i i i i i i i - +# +# (v4,2) jump:nt -- "if ( cmp.gtu ( Rt32 , Ns8 .new ) ) jump:nt #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 - 0 1 0 0 0 i i - s s s P P 0 t t t t t i i i i i i i - +# +# (v4,2) jump:nt -- "if ( ! cmp.gtu ( Rt32 , Ns8 .new ) ) jump:nt #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 - 0 1 0 0 1 i i - s s s P P 0 t t t t t i i i i i i i - +# +# (v4,2) jump:t -- "if ( cmp.gtu ( Rt32 , Ns8 .new ) ) jump:t #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 - 0 1 0 0 0 i i - s s s P P 1 t t t t t i i i i i i i - +# +# (v4,2) jump:t -- "if ( ! cmp.gtu ( Rt32 , Ns8 .new ) ) jump:t #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 - 0 1 0 0 1 i i - s s s P P 1 t t t t t i i i i i i i - +# +# (v4,2) jump:nt -- "if ( tstbit ( Ns8 .new , #0 ) ) jump:nt #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 - 1 0 1 1 0 i i - s s s P P 0 - - - - - i i i i i i i - +# +# (v4,2) jump:nt -- "if ( ! tstbit ( Ns8 .new , #0 ) ) jump:nt #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 - 1 0 1 1 1 i i - s s s P P 0 - - - - - i i i i i i i - +# +# (v4,2) jump:t -- "if ( tstbit ( Ns8 .new , #0 ) ) jump:t #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 - 1 0 1 1 0 i i - s s s P P 1 - - - - - i i i i i i i - +# +# (v4,2) jump:t -- "if ( ! tstbit ( Ns8 .new , #0 ) ) jump:t #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 - 1 0 1 1 1 i i - s s s P P 1 - - - - - i i i i i i i - + +# All normal class-2 instructions are conditional jumps with compare +# and are handled by a single constructor although op2326 is not fully utilized + +JumpCmp_2326: "cmp.eq("^Nreg1618,rt5^")" is op2326=0 & Nreg1618 & rt5 { + tmp:4 = rt5; + <> + ConditionReg = (Nreg1618 == tmp); +} +JumpCmp_2326: "cmp.gt("^Nreg1618,rt5^")" is op2326=1 & Nreg1618 & rt5 { + tmp:4 = rt5; + <> + ConditionReg = (Nreg1618 s> tmp); +} +JumpCmp_2326: "cmp.gtu("^Nreg1618,rt5^")" is op2326=2 & Nreg1618 & rt5 { + tmp:4 = rt5; + <> + ConditionReg = (Nreg1618 > tmp); +} +JumpCmp_2326: "cmp.gt("^rt5,Nreg1618^")" is op2326=3 & Nreg1618 & rt5 { + tmp:4 = rt5; + <> + ConditionReg = (tmp s> Nreg1618); +} +JumpCmp_2326: "cmp.gtu("^rt5,Nreg1618^")" is op2326=4 & Nreg1618 & rt5 { + tmp:4 = rt5; + <> + ConditionReg = (tmp > Nreg1618); +} +### -- op2326 values 5-7 unused +JumpCmp_2326: "cmp.eq("^Nreg1618,Uimm8_0812^")" is op2326=8 & Nreg1618 & Uimm8_0812 { + <> + ConditionReg = (Nreg1618 == zext(Uimm8_0812)); +} +JumpCmp_2326: "cmp.gt("^Nreg1618,Uimm8_0812^")" is op2326=9 & Nreg1618 & Uimm8_0812 { + <> + ConditionReg = (Nreg1618 s> zext(Uimm8_0812)); +} +JumpCmp_2326: "cmp.gtu("^Nreg1618,Uimm8_0812^")" is op2326=10 & Nreg1618 & Uimm8_0812 { + <> + ConditionReg = (Nreg1618 > zext(Uimm8_0812)); +} +JumpCmp_2326: "tstbit("^Nreg1618,"#0)" is op2326=11 & Nreg1618 { + <> + ConditionReg = ((Nreg1618 & 1) != 0); +} +JumpCmp_2326: "cmp.eq("^Nreg1618,"#-1)" is op2326=12 & Nreg1618 { + <> + ConditionReg = (Nreg1618 == -1); +} +JumpCmp_2326: "cmp.gt("^Nreg1618,"#-1)" is op2326=13 & Nreg1618 { + <> + ConditionReg = (Nreg1618 s> -1); +} +### -- op2326 values 14-15 unused + +JumpIf_2326_S22: JumpCmp_2326 is op22=0 & JumpCmp_2326 { } +JumpIf_2326_S22: "!"^JumpCmp_2326 is op22=1 & JumpCmp_2326 { + <> + build JumpCmp_2326; + ConditionReg = !ConditionReg; +} + +:jump.if^Taken13 JumpIf_2326_S22,RelDest9x EndPacket is iclass=2 & op27=0 & Taken13 & JumpIf_2326_S22 & RelDest9x & $(END_PACKET) { + build EndPacket; + <> + build JumpIf_2326_S22; + if (ConditionReg == 0) goto ; + goto RelDest9x; + +} + + +# (v2,5) jumpr -- "jumpr Rs32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 1 0 0 1 0 1 0 0 s s s s s P P - - - - - - - - - - - - - - + +:jumpr rs5 EndPacket is iclass=5 & op2127=0x14 & op0013=0 & rs5 & $(END_PACKET) { + dest:4 = rs5; + build EndPacket; + <> + goto [dest]; +} + +# jumpr LR (special case: treat as return) +:jumpr LR EndPacket is iclass=5 & op2127=0x14 & op1620=31 & op0013=0 & LR & $(END_PACKET) { + dest:4 = LR; + build EndPacket; + <> + return [dest]; +} + +# jumprh -- "jumprh Rs32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 1 0 0 1 0 1 1 0 s s s s s P P - - - - - - - - - - - - - - + +:jumprh rs5 EndPacket is iclass=5 & op2127=0x16 & op0013=0 & rs5 & $(END_PACKET) { + dest:4 = rs5; + build EndPacket; + <> + goto [dest]; +} + +# jumpr LR (special case: treat as return) +:jumprh LR EndPacket is iclass=5 & op2127=0x16 & op1620=31 & op0013=0 & LR & $(END_PACKET) { + dest:4 = LR; + build EndPacket; + <> + return [dest]; +} + +# (v2,5) jumpr:nt -- "if ( Pu4 ) jumpr:nt Rs32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 1 0 0 1 1 0 1 0 s s s s s P P - 0 0 - u u - - - - - - - - +# +# (v2,5) jumpr:nt -- "if ( ! Pu4 ) jumpr:nt Rs32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 1 0 0 1 1 0 1 1 s s s s s P P - 0 0 - u u - - - - - - - - +# +# (v2,5) jumpr:t -- "if ( Pu4 ) jumpr:t Rs32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 1 0 0 1 1 0 1 0 s s s s s P P - 1 0 - u u - - - - - - - - +# +# (v2,5) jumpr:t -- "if ( ! Pu4 ) jumpr:t Rs32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 1 0 0 1 1 0 1 1 s s s s s P P - 1 0 - u u - - - - - - - - + +:jumpr^FlowCondUU^Taken12 rs5 EndPacket is iclass=5 & op2227=0xd & Taken12 & op11=0 & op0007=0 & rs5 & FlowCondUU & $(END_PACKET) { + dest:4 = rs5; + build FlowCondUU; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + goto [dest]; + +} + +# if ([!]Pu) jumpr LR (special case: treat as conditional return) +:jumpr^FlowCondUU^Taken12 LR EndPacket is iclass=5 & op2227=0xd & op1620=31 & Taken12 & op11=0 & op0007=0 & LR & FlowCondUU & $(END_PACKET) { + dest:4 = LR; + build FlowCondUU; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + return [dest]; + +} + +# (v4,5) jumpr:nt -- "if ( Pu4 .new ) jumpr:nt Rs32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 1 0 0 1 1 0 1 0 s s s s s P P - 0 1 - u u - - - - - - - - +# +# (v4,5) jumpr:nt -- "if ( ! Pu4 .new ) jumpr:nt Rs32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 1 0 0 1 1 0 1 1 s s s s s P P - 0 1 - u u - - - - - - - - +# +# (v4,5) jumpr:t -- "if ( Pu4 .new ) jumpr:t Rs32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 1 0 0 1 1 0 1 0 s s s s s P P - 1 1 - u u - - - - - - - - +# +# (v4,5) jumpr:t -- "if ( ! Pu4 .new ) jumpr:t Rs32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 1 0 0 1 1 0 1 1 s s s s s P P - 1 1 - u u - - - - - - - - + +:jumpr^FlowCondNewUU^Taken12 rs5 EndPacket is iclass=5 & op2227=0xd & Taken12 & op11=1 & rs5 & FlowCondNewUU & $(END_PACKET) { + dest:4 = rs5; + build FlowCondNewUU; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + goto [dest]; + +} + +# if ([!]Pu.new) jumpr LR (special case: treat as conditional return) +:jumpr^FlowCondNewUU LR EndPacket is iclass=5 & op2227=0xd & op1620=31 & Taken12 & op11=1 & LR & FlowCondNewUU & $(END_PACKET) { + dest:4 = LR; + build FlowCondNewUU; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + return [dest]; + +} + +# (v4,6) k0lock -- "k0lock" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 1 1 0 0 0 0 1 - - - - - P P - - - - - - 0 1 1 - - - - - + +define pcodeop k0lock; + +:k0lock EndPacket is iclass=6 & op2127=0x61 & op0507=3 & $(END_PACKET) { + k0lock(); + build EndPacket; +} + +# (v4,6) k0unlock -- "k0unlock" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 1 1 0 0 0 0 1 - - - - - P P - - - - - - 1 0 0 - - - - - + +define pcodeop k0unlock; + +:k0unlock EndPacket is iclass=6 & op2127=0x61 & op0507=4 & $(END_PACKET) { + k0unlock(); + build EndPacket; +} + +# (v65,10) l2cleanidx -- "l2cleanidx ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 0 1 1 0 0 0 1 s s s s s P P - - - - - - - - - - - - - - + +define pcodeop l2cleanidx; + +:l2cleanidx rs5 EndPacket is iclass=10 & op2127=0x31 & rs5 & $(END_PACKET) { + l2cleanidx(rs5); + build EndPacket; +} + +# (v4,10) l2cleaninvidx -- "l2cleaninvidx ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 0 0 0 1 1 s s s s s P P - - - - - - - - - - - - - - + +define pcodeop l2cleaninvidx; + +:l2cleaninvidx rs5 EndPacket is iclass=10 & op2127=0x43 & rs5 & $(END_PACKET) { + l2cleaninvidx(rs5); + build EndPacket; +} + +# (v4,10) l2fetch -- "l2fetch ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 0 1 1 0 0 + + s s s s s P P - t t t t t - - - - - - - - + +define pcodeop l2fetch; + +:l2fetch rs5,rt5 EndPacket is iclass=10 & op2127=0x30 & rs5 & rt5 & op13=0 & op0007=0 & $(END_PACKET) { + l2fetch(rs5,rt5); + build EndPacket; +} + +# (v?,10) l2fetch -- "l2fetch ( Rs32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 0 1 1 0 1 + + s s s s s P P - t t t t t - - - - - - - - + +:l2fetch rs5,rtt5 EndPacket is iclass=10 & op2127=0x34 & rs5 & rtt5 & $(END_PACKET) { + l2fetch(rs5,rtt5); + build EndPacket; +} + +# (v65,10) l2gclean -- "l2gclean" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 0 0 0 0 1 + + + + + P P - 1 0 0 - - - - - - - - - - + +define pcodeop l2gclean; + +:l2gclean EndPacket is iclass=10 & op2127=0x41 & op1012=4 & $(END_PACKET) { + l2gclean(); + build EndPacket; +} + +# (v65,10) l2gclean -- "l2gclean ( Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 0 1 1 0 1 0 1 + + + + + P P - t t t t t - - - - - - - - + +:l2gclean rtt5 EndPacket is iclass=10 & op2127=0x35 & rtt5 & $(END_PACKET) { + l2gclean(rtt5); + build EndPacket; +} + +# (v65,10) l2gcleaninv -- "l2gcleaninv" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 0 0 0 0 1 + + + + + P P - 1 1 0 - - - - - - - - - - + +define pcodeop l2gcleaninv; + +:l2gcleaninv EndPacket is iclass=10 & op2127=0x41 & op1012=6 & $(END_PACKET) { + l2gcleaninv(); + build EndPacket; +} + +# (v65,10) l2gcleaninv -- "l2gcleaninv ( Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 0 1 1 0 1 1 0 + + + + + P P - t t t t t - - - - - - - - + +:l2gcleaninv rtt5 EndPacket is iclass=10 & op2127=0x36 & rtt5 & $(END_PACKET) { + l2gcleaninv(rtt5); + build EndPacket; +} + +# (v65,10) l2gunlock -- "l2gunlock" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 0 0 0 0 1 + + + + + P P - 0 1 0 - - - - - - - - - - + +define pcodeop l2gunlock; + +:l2gunlock EndPacket is iclass=10 & op2127=0x41 & op1012=2 & $(END_PACKET) { + l2gunlock(); + build EndPacket; +} + +# (v65,10) l2invidx -- "l2invidx ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 0 1 1 0 0 1 0 s s s s s P P - - - - - - - - - - - - - - + +define pcodeop l2invidx; + +:l2invidx rs5 EndPacket is iclass=10 & op2127=0x32 & rs5 & $(END_PACKET) { + l2invidx(rs5); + build EndPacket; +} + +# (v2,10) l2kill -- "l2kill" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 0 0 0 0 1 - - - - - P P - 0 0 0 - - - - - - - - - - + +define pcodeop l2kill; + +:l2kill EndPacket is iclass=10 & op2127=0x41 & op1012=0 & $(END_PACKET) { + l2kill(); + build EndPacket; +} + +# (v65,10) l2tagr -- "Rd32 = l2tagr ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 0 1 0 0 0 1 1 s s s s s P P - - - - - - - - - d d d d d + +define pcodeop l2tagr; + +:l2tagr Rd5,rs5 EndPacket is iclass=10 & op2127=0x23 & Rd5 & rs5 & $(END_PACKET) { + Rd5 = l2tagr(rs5); + build EndPacket; +} + +# (v65,10) l2tagw -- "l2tagw ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 0 1 0 0 0 1 0 s s s s s P P 0 t t t t t - - - - - - - - + +define pcodeop l2tagw; + +:l2tagw rs5,rt5 EndPacket is iclass=10 & op2127=0x22 & op13=0 & rs5 & rt5 & $(END_PACKET) { + l2tagw(rs5,rt5); + build EndPacket; +} + +# (v4,10) l2unlocka -- "l2unlocka ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 0 1 1 0 0 1 1 s s s s s P P - - - - - - - - - - - - - - + +define pcodeop l2unlocka; + +:l2unlocka rs5 EndPacket is iclass=10 & op2127=0x33 & rs5 & $(END_PACKET) { + l2unlocka(rs5); + build EndPacket; +} + +# (v65,10) l2locka -- "Pd2 = l2locka ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 0 0 0 0 1 1 1 s s s s s P P 1 - - - - - - - - - - - d d + +define pcodeop l2locka; + +:l2locka Pd2,rs5 EndPacket is iclass=10 & op2127=0x7 & op13=1 & Pd2 & rs5 & $(END_PACKET) { + Pd2 = l2locka(rs5); + build EndPacket; +} + +# (v2,12) lfs -- "Rdd32 = lfs ( Rss32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 0 0 1 1 0 + s s s s s P P + t t t t t 1 1 + d d d d d + +define pcodeop lfs; +:lfs Rdd5,rss5,rtt5 EndPacket is iclass=12 & op2127=0x0c & op13=0 & op0507=6 & Rdd5 & rss5 & rtt5 & $(END_PACKET) { + Rdd5 = lfs(rss5, rtt5); + build EndPacket; +} + + +# linecpy -- "Rdd32 = linecpy( Rs32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 0 1 1 1 1 t t t t t P P 0 s s s s s 0 0 1 d d d d d + +define pcodeop linecpy; +:linecpy Rdd5,rt5,rss5 EndPacket is iclass=0x9 & op2127=0x4f & op13=0 & op0507=1 & Rdd5 & rss5 & rt5 & $(END_PACKET) { + Rdd5 = linecpy(rt5, rss5); +} + +# +# loop0/loop1 subconstructors +# + +# Loop relative addresseses support immext +LoopRelAddr7x: val is s0812 & i0304 & immexted=0 [ val = (((s0812 << 2) | i0304) << 2) + $(PKT_START); ] { export *[const]:4 val; } +LoopRelAddr7x: val is i0811 & immexted=1 [ val = (simmext << 6) | (i0811 << 2) + $(PKT_START); ] { export *[const]:4 val; } + +LoopRelMem7x: LoopRelAddr7x is LoopRelAddr7x { export *[ram]:4 LoopRelAddr7x; } + +LoopUimm10: "#"^val is i1620 & i0507 & i0001 [ val = (i1620 << 5) | (i0507 << 2) | i0001; ] { export *[const]:4 val; } + +# (v2,6) loop0 -- "loop0 ( #r7:2x , #U10 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 1 0 0 1 0 0 0 I I I I I P P - i i i i i I I I i i - I I + +:loop0 LoopRelMem7x,LoopUimm10 EndPacket is iclass=6 & op2127=0x48 & op13=0 & op2=0 & LoopRelMem7x & LoopRelAddr7x & LoopUimm10 & $(END_PACKET) { + SA0_ = LoopRelAddr7x; + LC0_ = LoopUimm10; + build EndPacket; + <> + SA0 = SA0_; + LC0 = LC0_; + $(LPCFG) = 0; +} + +# (v2,6) loop0 -- "loop0 ( #r7:2x , Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 0 0 0 0 0 0 0 s s s s s P P - i i i i i - - - i i - - - + +:loop0 LoopRelMem7x,rs5 EndPacket is iclass=6 & op2127=0 & op13=0 & op0507=0 & op0002=0 & LoopRelMem7x & LoopRelAddr7x & rs5 & $(END_PACKET) { + SA0_ = LoopRelAddr7x; + LC0_ = rs5; + build EndPacket; + <> + SA0 = SA0_; + LC0 = LC0_; + $(LPCFG) = 0; +} + +# (v2,6) loop1 -- "loop1 ( #r7:2x , #U10 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 1 0 0 1 0 0 1 I I I I I P P - i i i i i I I I i i - I I + +:loop1 LoopRelMem7x,LoopUimm10 EndPacket is iclass=6 & op2127=0x49 & op13=0 & op2=0 & LoopRelMem7x & LoopRelAddr7x & LoopUimm10 & $(END_PACKET) { + SA1_ = LoopRelAddr7x; + LC1_ = LoopUimm10; + build EndPacket; + <> + SA1 = SA1_; + LC1 = LC1_; + $(LPCFG) = 0; +} + +# (v2,6) loop1 -- "loop1 ( #r7:2x , Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 0 0 0 0 0 0 1 s s s s s P P - i i i i i - - - i i - - - + +:loop1 LoopRelMem7x,rs5 EndPacket is iclass=6 & op2127=1 & op13=0 & op0507=0 & op0002=0 & LoopRelMem7x & LoopRelAddr7x & rs5 & $(END_PACKET) { + SA1_ = LoopRelAddr7x; + LC1_ = rs5; + build EndPacket; + <> + SA1 = SA1_; + LC1 = LC1_; + $(LPCFG) = 0; +} + +# (v4,12) lsl -- "Rd32 = lsl ( #s6 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 1 1 0 1 0 + i i i i i P P + t t t t t 1 1 i d d d d d + +:lsl Rd5,Simm8_1620_05,rt5 EndPacket is iclass=12 & op2127=0x34 & op13=0 & op0607=3 & Rd5 & rt5 & Simm8_1620_05 & $(END_PACKET) { + Rd5 = sext(Simm8_1620_05) << rt5; + build EndPacket; +} + +# (v2,12) lsl -- "Rd32 = lsl ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 1 1 0 0 1 + s s s s s P P + t t t t t 1 1 + d d d d d + +:lsl Rd5,rs5,rt5 EndPacket is iclass=12 & op2127=0x32 & op13=0 & op0507=6 & Rd5 & rt5 & rs5 & $(END_PACKET) { + right:1 = rt5 s< 0; + Rd5 = (zext(right) * (rs5 >> -rt5)) + (zext(!right) * (rs5 << rt5)); + build EndPacket; +} + +# (v2,12) lsl -- "Rdd32 = lsl ( Rss32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 0 1 1 1 0 + s s s s s P P + t t t t t 1 1 + d d d d d + +:lsl Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x1c & op13=0 & op0507=6 & Rdd5 & rt5 & rss5 & $(END_PACKET) { + right:1 = rt5 s< 0; + Rdd5 = (zext(right) * (rss5 >> -rt5)) + (zext(!right) * (rss5 << rt5)); + build EndPacket; +} + +# (v2,12) lsl -- "Rx32 &= lsl ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 1 1 0 0 0 1 + s s s s s P P + t t t t t 1 1 + x x x x x + +:lsl&= Rd5,rs5,rt5 EndPacket is iclass=12 & op2127=0x62 & op13=0 & op0507=6 & Rd5 & rd5 & rt5 & rs5 & $(END_PACKET) { + right:1 = rt5 s< 0; + result:4 = (zext(right) * (rs5 >> -rt5)) + (zext(!right) * (rs5 << rt5)); + Rd5 = rd5 & result; + build EndPacket; +} + +# (v2,12) lsl -- "Rx32 += lsl ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 1 1 0 0 1 1 + s s s s s P P + t t t t t 1 1 + x x x x x + +:lsl+= Rd5,rs5,rt5 EndPacket is iclass=12 & op2127=0x66 & op13=0 & op0507=6 & Rd5 & rd5 & rt5 & rs5 & $(END_PACKET) { + right:1 = rt5 s< 0; + result:4 = (zext(right) * (rs5 >> -rt5)) + (zext(!right) * (rs5 << rt5)); + Rd5 = rd5 + result; + build EndPacket; +} + +# (v2,12) lsl -- "Rx32 -= lsl ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 1 1 0 0 1 0 + s s s s s P P + t t t t t 1 1 + x x x x x + +:lsl-= Rd5,rs5,rt5 EndPacket is iclass=12 & op2127=0x64 & op13=0 & op0507=6 & Rd5 & rd5 & rt5 & rs5 & $(END_PACKET) { + right:1 = rt5 s< 0; + result:4 = (zext(right) * (rs5 >> -rt5)) + (zext(!right) * (rs5 << rt5)); + Rd5 = rd5 - result; + build EndPacket; +} + +# (v2,12) lsl -- "Rx32 |= lsl ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 1 1 0 0 0 0 + s s s s s P P + t t t t t 1 1 + x x x x x + +:lsl|= Rd5,rs5,rt5 EndPacket is iclass=12 & op2127=0x60 & op13=0 & op0507=6 & Rd5 & rd5 & rt5 & rs5 & $(END_PACKET) { + right:1 = rt5 s< 0; + result:4 = (zext(right) * (rs5 >> -rt5)) + (zext(!right) * (rs5 << rt5)); + Rd5 = rd5 | result; + build EndPacket; +} + +# (v2,12) lsl -- "Rxx32 &= lsl ( Rss32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 1 0 1 1 0 1 0 s s s s s P P + t t t t t 1 1 + x x x x x + +:lsl&= Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x5a & op13=0 & op0507=6 & Rdd5 & rdd5 & rt5 & rss5 & $(END_PACKET) { + Rdd5 = rdd5 & (rss5 << rt5); + build EndPacket; +} + +# (v2,12) lsl -- "Rxx32 += lsl ( Rss32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 1 0 1 1 1 1 0 s s s s s P P + t t t t t 1 1 + x x x x x + +:lsl+= Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x5e & op13=0 & op0507=6 & Rdd5 & rdd5 & rt5 & rss5 & $(END_PACKET) { + right:1 = rt5 s< 0; + result:8 = (zext(right) * (rss5 >> -rt5)) + (zext(!right) * (rss5 << rt5)); + Rdd5 = rdd5 + result; + build EndPacket; +} + +# (v2,12) lsl -- "Rxx32 -= lsl ( Rss32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 1 0 1 1 1 0 0 s s s s s P P + t t t t t 1 1 + x x x x x + +:lsl-= Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x5c & op13=0 & op0507=6 & Rdd5 & rdd5 & rt5 & rss5 & $(END_PACKET) { + right:1 = rt5 s< 0; + result:8 = (zext(right) * (rss5 >> -rt5)) + (zext(!right) * (rss5 << rt5)); + Rdd5 = rdd5 - result; + build EndPacket; +} + +# (v4,12) lsl -- "Rxx32 ^= lsl ( Rss32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 1 0 1 1 0 1 1 s s s s s P P + t t t t t 1 1 + x x x x x + +:lsl"^=" Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x5b & op13=0 & op0507=6 & Rdd5 & rdd5 & rt5 & rss5 & $(END_PACKET) { + right:1 = rt5 s< 0; + result:8 = (zext(right) * (rss5 >> -rt5)) + (zext(!right) * (rss5 << rt5)); + Rdd5 = rdd5 ^ result; + build EndPacket; +} + +# (v2,12) lsl -- "Rxx32 |= lsl ( Rss32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 1 0 1 1 0 0 0 s s s s s P P + t t t t t 1 1 + x x x x x + +:lsl|= Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x58 & op13=0 & op0507=6 & Rdd5 & rdd5 & rt5 & rss5 & $(END_PACKET) { + right:1 = rt5 s< 0; + result:8 = (zext(right) * (rss5 >> -rt5)) + (zext(!right) * (rss5 << rt5)); + Rdd5 = rdd5 | result; + build EndPacket; +} + +# (v2,8) lsr -- "Rd32 = lsr ( Rs32 , #u5 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 1 0 0 0 0 0 s s s s s P P 0 i i i i i 0 0 1 d d d d d + +:lsr Rd5,rs5,Uimm8_0812 EndPacket is iclass=8 & op2127=0x60 & op13=0 & op0507=1 & Rd5 & rs5 & Uimm8_0812 & $(END_PACKET) { + Rd5 = rs5 >> Uimm8_0812; + build EndPacket; +} + +# (v2,12) lsr -- "Rd32 = lsr ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 1 1 0 0 1 + s s s s s P P + t t t t t 0 1 + d d d d d + +:lsr Rd5,rs5,rt5 EndPacket is iclass=12 & op2127=0x32 & op13=0 & op0507=2 & Rd5 & rs5 & rt5 & $(END_PACKET) { + left:1 = rt5 s< 0; + Rd5 = (zext(!left) * (rs5 >> rt5)) + (zext(left) * (rs5 << -rt5)); + build EndPacket; +} + +# (v2,8) lsr -- "Rdd32 = lsr ( Rss32 , #u6 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 0 0 0 0 0 + s s s s s P P i i i i i i 0 0 1 d d d d d + +:lsr Rdd5,rss5,Uimm8_0813 EndPacket is iclass=8 & op2127=0x00 & op0507=1 & Rdd5 & rss5 & Uimm8_0813 & $(END_PACKET) { + Rdd5 = rss5 >> Uimm8_0813; + build EndPacket; +} + +# (v2,12) lsr -- "Rdd32 = lsr ( Rss32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 0 1 1 1 0 + s s s s s P P + t t t t t 0 1 + d d d d d + +:lsr Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x1c & op13=0 & op0507=2 & Rdd5 & rss5 & rt5 & $(END_PACKET) { + left:1 = rt5 s< 0; + Rdd5 = (zext(!left) * (rss5 >> rt5)) + (zext(left) * (rss5 << -rt5)); + build EndPacket; +} + +# (v2,8) lsr -- "Rx32 &= lsr ( Rs32 , #u5 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 1 1 0 0 1 + s s s s s P P 0 i i i i i 0 0 1 x x x x x + +:lsr&= Rd5,rs5,Uimm8_0812 EndPacket is iclass=8 & op2127=0x72 & op13=0 & op0507=1 & Rd5 & rd5 & rs5 & Uimm8_0812 & $(END_PACKET) { + Rd5 = rd5 & (rs5 >> Uimm8_0812); + build EndPacket; +} + +# (v2,12) lsr -- "Rx32 &= lsr ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 1 1 0 0 0 1 + s s s s s P P + t t t t t 0 1 + x x x x x + +:lsr&= Rd5,rs5,rt5 EndPacket is iclass=12 & op2127=0x62 & op13=0 & op0507=2 & Rd5 & rd5 & rs5 & rt5 & $(END_PACKET) { + left:1 = rt5 s< 0; + result:4 = (zext(!left) * (rs5 >> rt5)) + (zext(left) * (rs5 << -rt5)); + Rd5 = rd5 & result; + build EndPacket; +} + +# (v2,8) lsr -- "Rx32 += lsr ( Rs32 , #u5 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 1 1 0 0 0 + s s s s s P P 0 i i i i i 1 0 1 x x x x x + +:lsr+= Rd5,rs5,Uimm8_0812 EndPacket is iclass=8 & op2127=0x70 & op13=0 & op0507=5 & Rd5 & rd5 & rs5 & Uimm8_0812 & $(END_PACKET) { + Rd5 = rd5 + (rs5 >> Uimm8_0812); + build EndPacket; +} + +# (v2,12) lsr -- "Rx32 += lsr ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 1 1 0 0 1 1 + s s s s s P P + t t t t t 0 1 + x x x x x + +:lsr+= Rd5,rs5,rt5 EndPacket is iclass=12 & op2127=0x66 & op13=0 & op0507=2 & Rd5 & rd5 & rs5 & rt5 & $(END_PACKET) { + left:1 = rt5 s< 0; + result:4 = (zext(!left) * (rs5 >> rt5)) + (zext(left) * (rs5 << -rt5)); + Rd5 = rd5 + result; + build EndPacket; +} + +# (v2,8) lsr -- "Rx32 -= lsr ( Rs32 , #u5 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 1 1 0 0 0 + s s s s s P P 0 i i i i i 0 0 1 x x x x x + +:lsr-= Rd5,rs5,Uimm8_0812 EndPacket is iclass=8 & op2127=0x70 & op13=0 & op0507=1 & Rd5 & rd5 & rs5 & Uimm8_0812 & $(END_PACKET) { + Rd5 = rd5 - (rs5 >> Uimm8_0812); + build EndPacket; +} + +# (v2,12) lsr -- "Rx32 -= lsr ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 1 1 0 0 1 0 + s s s s s P P + t t t t t 0 1 + x x x x x + +:lsr-= Rd5,rs5,rt5 EndPacket is iclass=12 & op2127=0x64 & op13=0 & op0507=2 & Rd5 & rd5 & rs5 & rt5 & $(END_PACKET) { + left:1 = rt5 s< 0; + result:4 = (zext(!left) * (rs5 >> rt5)) + (zext(left) * (rs5 << -rt5)); + Rd5 = rd5 - result; + build EndPacket; +} + +# (v2,8) lsr -- "Rx32 ^= lsr ( Rs32 , #u5 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 1 1 0 1 0 + s s s s s P P 0 i i i i i 0 0 1 x x x x x + +:lsr"^=" Rd5,rs5,Uimm8_0812 EndPacket is iclass=8 & op2127=0x74 & op13=0 & op0507=1 & Rd5 & rd5 & rs5 & Uimm8_0812 & $(END_PACKET) { + Rd5 = rd5 ^ (rs5 >> Uimm8_0812); + build EndPacket; +} + +# (v2,8) lsr -- "Rx32 |= lsr ( Rs32 , #u5 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 1 1 0 0 1 + s s s s s P P 0 i i i i i 1 0 1 x x x x x + +:lsr|= Rd5,rs5,Uimm8_0812 EndPacket is iclass=8 & op2127=0x72 & op13=0 & op0507=5 & Rd5 & rd5 & rs5 & Uimm8_0812 & $(END_PACKET) { + Rd5 = rd5 | (rs5 >> Uimm8_0812); + build EndPacket; +} + +# (v2,12) lsr -- "Rx32 |= lsr ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 1 1 0 0 0 0 + s s s s s P P + t t t t t 0 1 + x x x x x + +:lsr|= Rd5,rs5,rt5 EndPacket is iclass=12 & op2127=0x60 & op13=0 & op0507=2 & Rd5 & rd5 & rs5 & rt5 & $(END_PACKET) { + left:1 = rt5 s< 0; + result:4 = (zext(!left) * (rs5 >> rt5)) + (zext(left) * (rs5 << -rt5)); + Rd5 = rd5 | result; + build EndPacket; +} + +# (v2,8) lsr -- "Rxx32 &= lsr ( Rss32 , #u6 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 0 1 0 0 1 + s s s s s P P i i i i i i 0 0 1 x x x x x + +:lsr&= Rdd5,rss5,Uimm8_0813 EndPacket is iclass=8 & op2127=0x12 & op0507=1 & Rdd5 & rdd5 & rss5 & Uimm8_0813 & $(END_PACKET) { + Rdd5 = rdd5 & (rss5 >> Uimm8_0813); + build EndPacket; +} + +# (v2,12) lsr -- "Rxx32 &= lsr ( Rss32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 1 0 1 1 0 1 0 s s s s s P P + t t t t t 0 1 + x x x x x + +:lsr&= Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x5a & op13=0 & op0507=2 & Rdd5 & rdd5 & rss5 & rt5 & $(END_PACKET) { + left:1 = rt5 s< 0; + result:8 = (zext(!left) * (rss5 >> rt5)) + (zext(left) * (rss5 << -rt5)); + Rdd5 = rdd5 & result; + build EndPacket; +} + +# (v2,8) lsr -- "Rxx32 += lsr ( Rss32 , #u6 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 0 1 0 0 0 + s s s s s P P i i i i i i 1 0 1 x x x x x + +:lsr+= Rdd5,rss5,Uimm8_0813 EndPacket is iclass=8 & op2127=0x10 & op0507=5 & Rdd5 & rdd5 & rss5 & Uimm8_0813 & $(END_PACKET) { + Rdd5 = rdd5 + (rss5 >> Uimm8_0813); + build EndPacket; +} + +# (v2,12) lsr -- "Rxx32 += lsr ( Rss32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 1 0 1 1 1 1 0 s s s s s P P + t t t t t 0 1 + x x x x x + +:lsr+= Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x5e & op13=0 & op0507=2 & Rdd5 & rdd5 & rss5 & rt5 & $(END_PACKET) { + left:1 = rt5 s< 0; + result:8 = (zext(!left) * (rss5 >> rt5)) + (zext(left) * (rss5 << -rt5)); + Rdd5 = rdd5 + result; + build EndPacket; +} + +# (v2,8) lsr -- "Rxx32 -= lsr ( Rss32 , #u6 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 0 1 0 0 0 + s s s s s P P i i i i i i 0 0 1 x x x x x + +:lsr-= Rdd5,rss5,Uimm8_0813 EndPacket is iclass=8 & op2127=0x10 & op0507=1 & Rdd5 & rdd5 & rss5 & Uimm8_0813 & $(END_PACKET) { + Rdd5 = rdd5 - (rss5 >> Uimm8_0813); + build EndPacket; +} + +# (v2,12) lsr -- "Rxx32 -= lsr ( Rss32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 1 0 1 1 1 0 0 s s s s s P P + t t t t t 0 1 + x x x x x + +:lsr-= Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x5c & op13=0 & op0507=2 & Rdd5 & rdd5 & rss5 & rt5 & $(END_PACKET) { + left:1 = rt5 s< 0; + result:8 = (zext(!left) * (rss5 >> rt5)) + (zext(left) * (rss5 << -rt5)); + Rdd5 = rdd5 - result; + build EndPacket; +} + +# (v2,8) lsr -- "Rxx32 ^= lsr ( Rss32 , #u6 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 0 1 0 1 0 + s s s s s P P i i i i i i 0 0 1 x x x x x + +:lsr"^=" Rdd5,rss5,Uimm8_0813 EndPacket is iclass=8 & op2127=0x14 & op0507=1 & Rdd5 & rdd5 & rss5 & Uimm8_0813 & $(END_PACKET) { + Rdd5 = rdd5 ^ (rss5 >> Uimm8_0813); + build EndPacket; +} + +# (v4,12) lsr -- "Rxx32 ^= lsr ( Rss32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 1 0 1 1 0 1 1 s s s s s P P + t t t t t 0 1 + x x x x x + +:lsr"^=" Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x5b & op13=0 & op0507=2 & Rdd5 & rdd5 & rss5 & rt5 & $(END_PACKET) { + left:1 = rt5 s< 0; + result:8 = (zext(!left) * (rss5 >> rt5)) + (zext(left) * (rss5 << -rt5)); + Rdd5 = rdd5 ^ result; + build EndPacket; +} + +# (v2,8) lsr -- "Rxx32 |= lsr ( Rss32 , #u6 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 0 1 0 0 1 + s s s s s P P i i i i i i 1 0 1 x x x x x + +:lsr|= Rdd5,rss5,Uimm8_0813 EndPacket is iclass=8 & op2127=0x12 & op0507=5 & Rdd5 & rdd5 & rss5 & Uimm8_0813 & $(END_PACKET) { + Rdd5 = rdd5 | (rss5 >> Uimm8_0813); + build EndPacket; +} + +# (v2,12) lsr -- "Rxx32 |= lsr ( Rss32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 1 0 1 1 0 0 0 s s s s s P P + t t t t t 0 1 + x x x x x + +:lsr|= Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x58 & op13=0 & op0507=2 & Rdd5 & rdd5 & rss5 & rt5 & $(END_PACKET) { + left:1 = rt5 s< 0; + result:8 = (zext(!left) * (rss5 >> rt5)) + (zext(left) * (rss5 << -rt5)); + Rdd5 = rdd5 | result; + build EndPacket; +} + +# (v2,8) mask -- "Rdd32 = mask ( Pt4 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 1 1 0 + + + + + + + + P P + + + + t t + + + d d d d d + +define pcodeop maskGenerate; +:mask Rdd5,pu0809 EndPacket is iclass=8 & op2127=0x30 & op1620=0 & op1013=0 & op0507=0 & Rdd5 & pu0809 & $(END_PACKET) { + val:1 = 0xff; + Rdd5[0,8] = val * (pu0809) & 1; + Rdd5[8,8] = val * (pu0809 >> 1) & 1; + Rdd5[16,8] = val * (pu0809 >> 2) & 1; + Rdd5[24,8] = val * (pu0809 >> 3) & 1; + Rdd5[32,8] = val * (pu0809 >> 4) & 1; + Rdd5[40,8] = val * (pu0809 >> 5) & 1; + Rdd5[48,8] = val * (pu0809 >> 6) & 1; + Rdd5[56,8] = val * (pu0809 >> 7) & 1; + build EndPacket; +} + +# mask -- "Rd32 = mask ( #u5 , #U5 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 1 0 1 0 I I - - - - - P P 1 i i i i i I I I d d d d d + +:mask Rd5,Uimm8_0812,Uimm8_2122_0507 EndPacket is iclass=8 & op2327=0x1a & op13=1 & Rd5 & op1620=0 & Uimm8_0812 & Uimm8_2122_0507 & $(END_PACKET) { + Rd5 = ((1< rt5; + Rd5 = (zext(bool) * rs5) + (zext(!bool) * rt5); + build EndPacket; +} + +# (v4,13) max -- "Rdd32 = max ( Rss32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 1 1 1 0 s s s s s P P + t t t t t 1 0 0 d d d d d + +:max Rdd5,rss5,rtt5 EndPacket is iclass=13 & op2127=0x1e & op13=0 & op0507=4 & Rdd5 & rss5 & rtt5 & $(END_PACKET) { + bool:1 = rss5 s> rtt5; + Rdd5 = (zext(bool) * rss5) + (zext(!bool) * rtt5); + build EndPacket; +} + +# (v2,13) maxu -- "Rd32 = maxu ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 1 0 1 1 1 0 s s s s s P P + t t t t t 1 + + d d d d d + +:maxu Rd5,rs5,rt5 EndPacket is iclass=13 & op2127=0x2e & op13=0 & op0507=4 & Rd5 & rs5 & rt5 & $(END_PACKET) { + bool:1 = rs5 > rt5; + Rd5 = (zext(bool) * rs5) + (zext(!bool) * rt5); + build EndPacket; +} + +# (v4,13) maxu -- "Rdd32 = maxu ( Rss32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 1 1 1 0 s s s s s P P + t t t t t 1 0 1 d d d d d + +:maxu Rdd5,rss5,rtt5 EndPacket is iclass=13 & op2127=0x1e & op13=0 & op0507=5 & Rdd5 & rss5 & rtt5 & $(END_PACKET) { + bool:1 = rss5 > rtt5; + Rdd5 = (zext(bool) * rss5) + (zext(!bool) * rtt5); + build EndPacket; +} + +# (v2,9) memb -- "Rd32 = memb ( Rs32 + #s11:0x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 0 i i 1 0 0 0 s s s s s P P i i i i i i i i i d d d d d + +:memb Rd5,LdMemRsRelxC9b0 EndPacket is iclass=9 & op27=0 & op2224=4 & op21=0 & Rd5 & LdMemRsRelxC9b0 & $(END_PACKET) { + Rd5 = sext(LdMemRsRelxC9b0); + build EndPacket; +} + +# (v4,3) memb -- "Rd32 = memb ( Rs32 + Rt32 << #n2 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 1 0 1 0 0 0 0 s s s s s P P n t t t t t n + + d d d d d + +:memb Rd5,MemRsRelShiftC3b EndPacket is iclass=3 & op2127=0x50 & op0506=0 & Rd5 & MemRsRelShiftC3b & $(END_PACKET) { + Rd5 = sext(MemRsRelShiftC3b); + build EndPacket; +} + +# (v4,9) memb -- "Rd32 = memb ( Rt32 << #n2 + #U6x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 1 0 1 0 0 0 t t t t t P P n 1 I I I I n I I d d d d d + +:memb Rd5,LdMemRsRelShiftxC9b EndPacket is iclass=9 & op2127=0x68 & op12=1 & Rd5 & LdMemRsRelShiftxC9b & $(END_PACKET) { + Rd5 = sext(LdMemRsRelShiftxC9b); + build EndPacket; +} + +# (v4,9) memb -- "Rd32 = memb ( Rf32 = #U6x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 1 1 0 0 0 f f f f f P P 0 1 I I I I + I I d d d d d + +:memb Rd5,LdMemRsAssignxC9b EndPacket is iclass=9 & op2127=0x58 & op1213=1 & op7=0 & Rd5 & LdMemRsAssignxC9b & $(END_PACKET) { + Rd5 = sext(LdMemRsAssignxC9b); + build EndPacket; +} + +# (v2,9) memb -- "Rd32 = memb ( Rz32 ++ #s4:0 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 1 1 0 0 0 z z z z z P P 0 0 + + + i i i i d d d d d + +:memb Rd5,LdMemAIS4C9b0 EndPacket is iclass=9 & op2127=0x58 & op0913=0 & Rd5 & LdMemAIS4C9b0 & $(END_PACKET) { + Rd5 = sext(LdMemAIS4C9b0); + build EndPacket; +} + +# +# (v2,9) memb -- "Rd32 = memb ( Rz32 ++ Mu2 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 1 0 1 0 0 0 z z z z z P P u 0 + + + + 0 + + d d d d d +# +# (v2,9) memb -- "Rd32 = memb ( Rz32 ++ Mu2 :brev )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 1 1 1 0 0 0 z z z z z P P u 0 + + + + 0 + + d d d d d + +:memb Rd5,LdMemAIMuC9b EndPacket is iclass=9 & op2627=3 & op2124=8 & op0512=0 & Rd5 & LdMemAIMuC9b & $(END_PACKET) { + Rd5 = sext(LdMemAIMuC9b); + build EndPacket; +} + +# (v2,9) memb -- "Rd32 = memb ( Rz32 ++ #s4:0 :circ ( Mu2 ) )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 0 1 0 0 0 z z z z z P P u 0 + + 0 i i i i d d d d d + +:memb Rd5,LdMemAIS4CircMuC9b0 EndPacket is iclass=9 & op2127=0x48 & op0912=0 & Rd5 & LdMemAIS4CircMuC9b0 & $(END_PACKET) { + Rd5 = sext(LdMemAIS4CircMuC9b0); + build EndPacket; +} + +# (v2,9) memb -- "Rd32 = memb ( Rz32 ++I :circ ( Mu2 ) )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 0 1 0 0 0 z z z z z P P u 0 + + 1 + 0 + + d d d d d + +:memb Rd5,LdMemAIICircMuC9b EndPacket is iclass=9 & op2127=0x48 & op0512=0x10 & Rd5 & LdMemAIICircMuC9b & $(END_PACKET) { + Rd5 = sext(LdMemAIICircMuC9b); + build EndPacket; +} + +# (v2,4) memb -- "Rd32 = memb ( gp + #u16:0x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 1 i i 1 0 0 0 i i i i i P P i i i i i i i i i d d d d d + +:memb Rd5,LdMemGPRelxC4b EndPacket is iclass=4 & op27=1 & op2224=4 & op21=0 & Rd5 & LdMemGPRelxC4b & $(END_PACKET) { + Rd5 = sext(LdMemGPRelxC4b); + build EndPacket; +} + + +# (v4,10) memb -- "memb ( Rf32 = #U6x ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 1 1 1 0 1 f f f f f P P 0 0 0 t t t 1 + I I I I I I + +:memb StMemRsAssignxC10b,Nreg0810 EndPacket is iclass=10 & op2127=0x5d & op1113=0 & op0607=2 & Nreg0810 & StMemRsAssignxC10b & $(END_PACKET) { + build EndPacket; + <> + StMemRsAssignxC10b = Nreg0810:1; +} + +# (v4,10) memb -- "memb ( Rf32 = #U6x ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 1 1 0 0 0 f f f f f P P 0 t t t t t 1 + I I I I I I + +:memb StMemRsAssignxC10b,rt5 EndPacket is iclass=10 & op2127=0x58 & op13=0 & op0607=2 & rt5 & StMemRsAssignxC10b & $(END_PACKET) { + tmp:1 = rt5:1; + build EndPacket; + <> + StMemRsAssignxC10b = tmp; +} + +# (v4,10) memb -- "memb ( Rs32 + #s11:0x ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 0 i i 1 1 0 1 s s s s s P P i 0 0 t t t i i i i i i i i + +:memb StMemRsRelxC10b,Nreg0810 EndPacket is iclass=10 & op27=0 & op2224=6 & op21=1 & op1112=0 & Nreg0810 & StMemRsRelxC10b & $(END_PACKET) { + build EndPacket; + <> + StMemRsRelxC10b = Nreg0810:1; +} + +# (v2,10) memb -- "memb ( Rs32 + #s11:0x ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 0 i i 1 0 0 0 s s s s s P P i t t t t t i i i i i i i i + +:memb StMemRsRelxC10b,rt5 EndPacket is iclass=10 & op27=0 & op2224=4 & op21=0 & rt5 & StMemRsRelxC10b & $(END_PACKET) { + tmp:1 = rt5:1; + build EndPacket; + <> + StMemRsRelxC10b = tmp; +} + +# (v4,3) memb -- "memb ( Rs32 + #u6:0 ) = #S8x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 1 1 0 + + 0 0 s s s s s P P I i i i i i i I I I I I I I + +:memb StMemRsRelC3b,Simm8_13_0006x EndPacket is iclass=3 & op2127=0x60 & StMemRsRelC3b & Simm8_13_0006x & $(END_PACKET) { + build EndPacket; + <> + StMemRsRelC3b = Simm8_13_0006x; +} + +# (v4,3) memb -- "memb ( Rs32 + #u6:0x ) &= Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 1 1 1 0 + 0 0 s s s s s P P 0 i i i i i i 1 0 t t t t t + +:memb&= StMemRsRelxC3b,ru5 EndPacket is iclass=3 & op2127=0x70 & op13=0 & op0506=2 & StMemRsRelxC3b & ru5 & $(END_PACKET) { + tmp:1 = StMemRsRelxC3b & ru5:1; + build EndPacket; + <> + StMemRsRelxC3b = tmp; +} + +# (v4,3) memb -- "memb ( Rs32 + #u6:0x ) += #U5" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 1 1 1 1 + 0 0 s s s s s P P 0 i i i i i i 0 0 I I I I I + +:memb+= StMemRsRelxC3b,Uimm8_0004 EndPacket is iclass=3 & op2127=0x78 & op13=0 & op0506=0 & StMemRsRelxC3b & Uimm8_0004 & $(END_PACKET) { + tmp:1 = StMemRsRelxC3b + Uimm8_0004; + build EndPacket; + <> + StMemRsRelxC3b = tmp; +} + +# (v4,3) memb -- "memb ( Rs32 + #u6:0x ) += Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 1 1 1 0 + 0 0 s s s s s P P 0 i i i i i i 0 0 t t t t t + +:memb+= StMemRsRelxC3b,ru5 EndPacket is iclass=3 & op2127=0x70 & op13=0 & op0506=0 & StMemRsRelxC3b & ru5 & $(END_PACKET) { + tmp:1 = StMemRsRelxC3b + ru5:1; + build EndPacket; + <> + StMemRsRelxC3b = tmp; +} + +# (v4,3) memb -- "memb ( Rs32 + #u6:0x ) -= #U5" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 1 1 1 1 + 0 0 s s s s s P P 0 i i i i i i 0 1 I I I I I + +:memb-= StMemRsRelxC3b,Uimm8_0004 EndPacket is iclass=3 & op2127=0x78 & op13=0 & op0506=1 & StMemRsRelxC3b & Uimm8_0004 & $(END_PACKET) { + tmp:1 = StMemRsRelxC3b - Uimm8_0004; + build EndPacket; + <> + StMemRsRelxC3b = tmp; +} + +# (v4,3) memb -- "memb ( Rs32 + #u6:0x ) -= Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 1 1 1 0 + 0 0 s s s s s P P 0 i i i i i i 0 1 t t t t t + +:memb-= StMemRsRelxC3b,ru5 EndPacket is iclass=3 & op2127=0x70 & op13=0 & op0506=1 & StMemRsRelxC3b & ru5 & $(END_PACKET) { + tmp:1 = StMemRsRelxC3b - ru5:1; + build EndPacket; + <> + StMemRsRelxC3b = tmp; +} + +# (v4,3) memb -- "memb ( Rs32 + #u6:0x ) = clrbit ( #U5 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 1 1 1 1 + 0 0 s s s s s P P 0 i i i i i i 1 0 I I I I I + +:memb StMemRsRelxC3b,ClrBit_0004b EndPacket is iclass=3 & op2127=0x78 & op13=0 & op0506=2 & StMemRsRelxC3b & ClrBit_0004b & $(END_PACKET) { + tmp:1 = StMemRsRelxC3b & ClrBit_0004b; + build EndPacket; + <> + StMemRsRelxC3b = tmp; +} + +# (v4,3) memb -- "memb ( Rs32 + #u6:0x ) = setbit ( #U5 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 1 1 1 1 + 0 0 s s s s s P P 0 i i i i i i 1 1 I I I I I + +:memb StMemRsRelxC3b,SetBit_0004b EndPacket is iclass=3 & op2127=0x78 & op13=0 & op0506=3 & StMemRsRelxC3b & SetBit_0004b & $(END_PACKET) { + tmp:1 = StMemRsRelxC3b | SetBit_0004b; + build EndPacket; + <> + StMemRsRelxC3b = tmp; +} + +# (v4,3) memb -- "memb ( Rs32 + #u6:0x ) |= Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 1 1 1 0 + 0 0 s s s s s P P 0 i i i i i i 1 1 t t t t t + +:memb|= StMemRsRelxC3b,ru5 EndPacket is iclass=3 & op2127=0x70 & op13=0 & op0506=3 & StMemRsRelxC3b & ru5 & $(END_PACKET) { + tmp:1 = StMemRsRelxC3b | ru5:1; + build EndPacket; + <> + StMemRsRelxC3b = tmp; +} + +# (v4,3) memb -- "memb ( Rs32 + Ru32 << #n2 ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 1 0 1 1 1 0 1 s s s s s P P n u u u u u n + + 0 0 t t t + +:memb MemRsRelShiftC3b,Nreg0002 EndPacket is iclass=3 & op2127=0x5d & op0306=0 & MemRsRelShiftC3b & Nreg0002 & $(END_PACKET) { + build EndPacket; + <> + MemRsRelShiftC3b = Nreg0002:1; +} + +# (v4,3) memb -- "memb ( Rs32 + Ru32 << #n2 ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 1 0 1 1 0 0 0 s s s s s P P n u u u u u n + + t t t t t + +:memb MemRsRelShiftC3b,ru5 EndPacket is iclass=3 & op2127=0x58 & op0506=0 & MemRsRelShiftC3b & ru5 & $(END_PACKET) { + tmp:1 = ru5:1; + build EndPacket; + <> + MemRsRelShiftC3b = tmp; +} + +# (v4,10) memb -- "memb ( Ru32 << #n2 + #U6x ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 1 0 1 1 0 1 u u u u u P P n 0 0 t t t 1 n I I I I I I + +:memb StMemRsRelShiftxC10b,Nreg0810 EndPacket is iclass=10 & op2127=0x6d & op1112=0 & op7=1 & Nreg0810 & StMemRsRelShiftxC10b & $(END_PACKET) { + build EndPacket; + <> + StMemRsRelShiftxC10b = Nreg0810:1; +} + +# (v4,10) memb -- "memb ( Ru32 << #n2 + #U6x ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 1 0 1 0 0 0 u u u u u P P n t t t t t 1 n I I I I I I + +:memb StMemRsRelShiftxC10b,rt5 EndPacket is iclass=10 & op2127=0x68 & op7=1 & rt5 & StMemRsRelShiftxC10b & $(END_PACKET) { + tmp:1 = rt5:1; + build EndPacket; + <> + StMemRsRelShiftxC10b = tmp; +} + +# (v4,10) memb -- "memb ( Rz32 ++ #s4:0 ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 1 1 1 0 1 z z z z z P P 0 0 0 t t t 0 i i i i + 0 + + +:memb StMemAIS4C10b,Nreg0810 EndPacket is iclass=10 & op2127=0x5d & op1113=0 & op7=0 & op0002=0 & Nreg0810 & StMemAIS4C10b & $(END_PACKET) { + build EndPacket; + <> + StMemAIS4C10b = Nreg0810:1; +} + +# (v4,10) memb -- "memb ( Rz32 ++ #s4:0 :circ ( Mu2 ) ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 0 1 1 0 1 z z z z z P P u 0 0 t t t 0 i i i i + 0 + + +:memb StMemAIS4CircMuC10b,Nreg0810 EndPacket is iclass=10 & op2127=0x4d & op1112=0 & op7=0 & op0002=0 & Nreg0810 & StMemAIS4CircMuC10b & $(END_PACKET) { + build EndPacket; + <> + StMemAIS4CircMuC10b = Nreg0810:1; +} + +# (v4,10) memb -- "memb ( Rz32 ++ Mu2 ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 1 0 1 1 0 1 z z z z z P P u 0 0 t t t 0 + + + + + + + +# +# (v4,10) memb -- "memb ( Rz32 ++ Mu2 :brev ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 1 1 1 1 0 1 z z z z z P P u 0 0 t t t 0 + + + + + + + + +:memb StMemAIMuC10b,Nreg0810 EndPacket is iclass=10 & op2627=3 & op2124=0xd & op1112=0 & op0007=0 & Nreg0810 & StMemAIMuC10b & $(END_PACKET) { + build EndPacket; + <> + StMemAIMuC10b = Nreg0810:1; +} + +# (v4,10) memb -- "memb ( Rz32 ++I :circ ( Mu2 ) ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 0 1 1 0 1 z z z z z P P u 0 0 t t t 0 + + + + + 1 + + +:memb StMemAIICircMuC10b,Nreg0810 EndPacket is iclass=10 & op2127=0x4d & op1112=0 & op0007=2 & Nreg0810 & StMemAIICircMuC10b & $(END_PACKET) { + build EndPacket; + <> + StMemAIICircMuC10b = Nreg0810:1; +} + +# (v2,10) memb -- "memb ( Rz32 ++ #s4:0 ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 1 1 0 0 0 z z z z z P P 0 t t t t t 0 i i i i + 0 + + +:memb StMemAIS4C10b,rt5 EndPacket is iclass=10 & op2127=0x58 & op13=0 & op7=0 & op0002=0 & rt5 & StMemAIS4C10b & $(END_PACKET) { + tmp:1 = rt5:1; + build EndPacket; + <> + StMemAIS4C10b = tmp; +} + +# (v2,10) memb -- "memb ( Rz32 ++ #s4:0 :circ ( Mu2 ) ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 0 1 0 0 0 z z z z z P P u t t t t t 0 i i i i + 0 + + +:memb StMemAIS4CircMuC10b,rt5 EndPacket is iclass=10 & op2127=0x48 & op7=0 & op0002=0 & rt5 & StMemAIS4CircMuC10b & $(END_PACKET) { + tmp:1 = rt5:1; + build EndPacket; + <> + StMemAIS4CircMuC10b = tmp; +} + +# (v2,10) memb -- "memb ( Rz32 ++ Mu2 ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 1 0 1 0 0 0 z z z z z P P u t t t t t 0 + + + + + + + +# +# (v2,10) memb -- "memb ( Rz32 ++ Mu2 :brev ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 1 1 1 0 0 0 z z z z z P P u t t t t t 0 + + + + + + + + +:memb StMemAIMuC10b,rt5 EndPacket is iclass=10 & op2627=3 & op2124=8 & op0007=0 & rt5 & StMemAIMuC10b & $(END_PACKET) { + tmp:1 = rt5:1; + build EndPacket; + <> + StMemAIMuC10b = tmp; +} + +# (v2,10) memb -- "memb ( Rz32 ++I :circ ( Mu2 ) ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 0 1 0 0 0 z z z z z P P u t t t t t 0 + + + + + 1 + + +:memb StMemAIICircMuC10b,rt5 EndPacket is iclass=10 & op2127=0x48 & op0007=0x2 & rt5 & StMemAIICircMuC10b & $(END_PACKET) { + tmp:1 = rt5:1; + build EndPacket; + <> + StMemAIICircMuC10b = tmp; +} + +# (v4,4) memb -- "memb ( gp + #u16:0x ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 1 i i 0 1 0 1 i i i i i P P i 0 0 t t t i i i i i i i i + +:memb StMemGPRelxC4b,Nreg0810 EndPacket is iclass=4 & op27=1 & op2224=2 & op21=1 & op1112=0 & Nreg0810 & StMemGPRelxC4b & $(END_PACKET) { + build EndPacket; + <> + StMemGPRelxC4b = Nreg0810:1; +} + +# (v2,4) memb -- "memb ( gp + #u16:0x ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 1 i i 0 0 0 0 i i i i i P P i t t t t t i i i i i i i i + +:memb StMemGPRelxC4b,rt5 EndPacket is iclass=4 & op27=1 & op2224=0 & op21=0 & rt5 & StMemGPRelxC4b & $(END_PACKET) { + tmp:1 = rt5:1; + build EndPacket; + <> + StMemGPRelxC4b = tmp; +} + +# (v4,9) memb -- "if ( Pt4 ) Rd32 = memb ( #u6x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 1 1 1 0 0 0 i i i i i P P 1 0 0 t t i 1 + + d d d d d +# +# (v4,9) memb -- "if ( ! Pt4 ) Rd32 = memb ( #u6x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 1 1 1 0 0 0 i i i i i P P 1 0 1 t t i 1 + + d d d d d +# +# (v4,9) memb -- "if ( Pt4 .new ) Rd32 = memb ( #u6x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 1 1 1 0 0 0 i i i i i P P 1 1 0 t t i 1 + + d d d d d +# +# (v4,9) memb -- "if ( ! Pt4 .new ) Rd32 = memb ( #u6x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 1 1 1 0 0 0 i i i i i P P 1 1 1 t t i 1 + + d d d d d + +:memb^PuCond0910_N12_S11 rd5,LdMemAbsU6xC9b EndPacket is iclass=9 & op2127=0x78 & op13=1 & op0507=4 & rd5 & LdMemAbsU6xC9b & PuCond0910_N12_S11 & $(END_PACKET) { + tmp:4 = 0; + build PuCond0910_N12_S11; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + tmp = sext(LdMemAbsU6xC9b); + + <> + if (ConditionReg == 0) goto ; + rd5 = tmp; + +} + +# (v2,4) memb -- "if ( Pt4 ) Rd32 = memb ( Rs32 + #u6:0x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 0 0 0 1 0 0 0 s s s s s P P 0 t t i i i i i i d d d d d +# +# (v2,4) memb -- "if ( ! Pt4 ) Rd32 = memb ( Rs32 + #u6:0x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 0 1 0 1 0 0 0 s s s s s P P 0 t t i i i i i i d d d d d +# +# (v2,4) memb -- "if ( Pt4 .new ) Rd32 = memb ( Rs32 + #u6:0x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 0 0 1 1 0 0 0 s s s s s P P 0 t t i i i i i i d d d d d +# +# (v2,4) memb -- "if ( ! Pt4 .new ) Rd32 = memb ( Rs32 + #u6:0x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 0 1 1 1 0 0 0 s s s s s P P 0 t t i i i i i i d d d d d + +:memb^PuCond1112_N25_S26 rd5,LdMemRsRelxC4b EndPacket is iclass=4 & op27=0 & op2124=8 & op13=0 & rd5 & LdMemRsRelxC4b & PuCond1112_N25_S26 & $(END_PACKET) { + tmp:4 = 0; + build PuCond1112_N25_S26; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + tmp = sext(LdMemRsRelxC4b); + + <> + if (ConditionReg == 0) goto ; + rd5 = tmp; + +} + +# (v2,9) memb -- "if ( Pt4 ) Rd32 = memb ( Rz32 ++ #s4:0 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 1 1 0 0 0 z z z z z P P 1 0 0 t t i i i i d d d d d +# +# (v2,9) memb -- "if ( ! Pt4 ) Rd32 = memb ( Rz32 ++ #s4:0 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 1 1 0 0 0 z z z z z P P 1 0 1 t t i i i i d d d d d +# +# (v4,9) memb -- "if ( Pt4 .new ) Rd32 = memb ( Rz32 ++ #s4:0 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 1 1 0 0 0 z z z z z P P 1 1 0 t t i i i i d d d d d +# +# (v4,9) memb -- "if ( ! Pt4 .new ) Rd32 = memb ( Rz32 ++ #s4:0 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 1 1 0 0 0 z z z z z P P 1 1 1 t t i i i i d d d d d + +:memb^PuCond0910_N12_S11 rd5,LdMemAIS4C9b0 EndPacket is iclass=9 & op2127=0x58 & op13=1 & rd5 & LdMemAIS4C9b0 & rs5 & PuCond0910_N12_S11 & $(END_PACKET) [ cond=1; ] { + tmp:4 = 0; + build PuCond0910_N12_S11; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + tmp = sext(LdMemAIS4C9b0); + + <> + if (ConditionReg == 0) goto ; + rd5 = tmp; + +} + +# (v4,3) memb -- "if ( Pv4 ) Rd32 = memb ( Rs32 + Rt32 << #n2 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 0 0 0 0 0 0 0 s s s s s P P n t t t t t n v v d d d d d +# +# (v4,3) memb -- "if ( ! Pv4 ) Rd32 = memb ( Rs32 + Rt32 << #n2 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 0 0 0 1 0 0 0 s s s s s P P n t t t t t n v v d d d d d +# +# (v4,3) memb -- "if ( Pv4 .new ) Rd32 = memb ( Rs32 + Rt32 << #n2 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 0 0 1 0 0 0 0 s s s s s P P n t t t t t n v v d d d d d +# +# (v4,3) memb -- "if ( ! Pv4 .new ) Rd32 = memb ( Rs32 + Rt32 << #n2 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 0 0 1 1 0 0 0 s s s s s P P n t t t t t n v v d d d d d + +:memb^PuCond0506_N25_S24 rd5,MemRsRelShiftC3b EndPacket is iclass=3 & op2627=0 & op2123=0 & rd5_ & rd5 & MemRsRelShiftC3b & PuCond0506_N25_S24 & $(END_PACKET) { + tmp:4 = 0; + build PuCond0506_N25_S24; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + tmp = sext(MemRsRelShiftC3b); + + <> + if (ConditionReg == 0) goto ; + rd5 = tmp; + +} + +# (v4,10) memb -- "if ( Pv4 ) memb ( #u6x ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 1 1 1 1 0 1 + + + i i P P 0 0 0 t t t 1 i i i i 0 v v +# +# (v4,10) memb -- "if ( Pv4 .new ) memb ( #u6x ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 1 1 1 1 0 1 + + + i i P P 1 0 0 t t t 1 i i i i 0 v v +# +# (v4,10) memb -- "if ( ! Pv4 ) memb ( #u6x ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 1 1 1 1 0 1 + + + i i P P 0 0 0 t t t 1 i i i i 1 v v +# +# (v4,10) memb -- "if ( ! Pv4 .new ) memb ( #u6x ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 1 1 1 1 0 1 + + + i i P P 1 0 0 t t t 1 i i i i 1 v v + +:memb^PuCond0001_N13_S02 StMemAbsU6xC10b,Nreg0810 EndPacket is iclass=10 & op2127=0x7d & op1820=0 & op1112=0 & op7=1 & Nreg0810 & StMemAbsU6xC10b & PuCond0001_N13_S02 & $(END_PACKET) { + build PuCond0001_N13_S02; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + StMemAbsU6xC10b = Nreg0810:1; + +} + +# (v4,10) memb -- "if ( Pv4 ) memb ( #u6x ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 1 1 1 0 0 0 - - - i i P P 0 t t t t t 1 i i i i 0 v v +# +# (v4,10) memb -- "if ( ! Pv4 ) memb ( #u6x ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 1 1 1 0 0 0 - - - i i P P 0 t t t t t 1 i i i i 1 v v +# +# (v4,10) memb -- "if ( Pv4 .new ) memb ( #u6x ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 1 1 1 0 0 0 - - - i i P P 1 t t t t t 1 i i i i 0 v v +# +# (v4,10) memb -- "if ( ! Pv4 .new ) memb ( #u6x ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 1 1 1 0 0 0 - - - i i P P 1 t t t t t 1 i i i i 1 v v + +:memb^PuCond0001_N13_S02 StMemAbsU6xC10b,rt5 EndPacket is iclass=10 & op2127=0x78 & op1820=0 & op7=1 & rt5 & StMemAbsU6xC10b & PuCond0001_N13_S02 & $(END_PACKET) { + tmp:1 = rt5:1; + build PuCond0001_N13_S02; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + StMemAbsU6xC10b = tmp; + +} + +# (v4,3) memb -- "if ( Pv4 ) memb ( Rs32 + #u6:0 ) = #S6x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 1 0 0 0 0 0 0 s s s s s P P I i i i i i i v v I I I I I +# +# (v4,3) memb -- "if ( ! Pv4 ) memb ( Rs32 + #u6:0 ) = #S6x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 1 0 0 0 1 0 0 s s s s s P P I i i i i i i v v I I I I I +# +# (v4,3) memb -- "if ( Pv4 .new ) memb ( Rs32 + #u6:0 ) = #S6x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 1 0 0 1 0 0 0 s s s s s P P I i i i i i i v v I I I I I +# +# (v4,3) memb -- "if ( ! Pv4 .new ) memb ( Rs32 + #u6:0 ) = #S6x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 1 0 0 1 1 0 0 s s s s s P P I i i i i i i v v I I I I I + +:memb^PuCond0506_N24_S23 StMemRsRelC3b,Simm8_13_0004x EndPacket is iclass=3 & op2527=4 & op2122=0 & Simm8_13_0004x & StMemRsRelC3b & PuCond0506_N24_S23 & $(END_PACKET) { + build PuCond0506_N24_S23; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + StMemRsRelC3b = Simm8_13_0004x; + +} + +# (v4,4) memb -- "if ( Pv4 ) memb ( Rs32 + #u6:0x ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 0 0 0 0 1 0 1 s s s s s P P i 0 0 t t t i i i i i 0 v v +# +# (v4,4) memb -- "if ( Pv4 .new ) memb ( Rs32 + #u6:0x ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 0 0 1 0 1 0 1 s s s s s P P i 0 0 t t t i i i i i 0 v v +# +# (v4,4) memb -- "if ( ! Pv4 ) memb ( Rs32 + #u6:0x ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 0 1 0 0 1 0 1 s s s s s P P i 0 0 t t t i i i i i 0 v v +# +# (v4,4) memb -- "if ( ! Pv4 .new ) memb ( Rs32 + #u6:0x ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 0 1 1 0 1 0 1 s s s s s P P i 0 0 t t t i i i i i 0 v v + +:memb^PuCond0001_N25_S26 StMemRsRelxC4b,Nreg0810 EndPacket is iclass=4 & op27=0 & op2224=2 & op21=1 & op1112=0 & op2=0 & Nreg0810 & StMemRsRelxC4b & PuCond0001_N25_S26 & $(END_PACKET) { + build PuCond0001_N25_S26; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + StMemRsRelxC4b = Nreg0810:1; + +} + +# (v4,4) memb -- "if ( Pv4 .new ) memb ( Rs32 + #u6:0x ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 0 0 1 0 0 0 0 s s s s s P P i t t t t t i i i i i 0 v v +# +# (v4,4) memb -- "if ( ! Pv4 .new ) memb ( Rs32 + #u6:0x ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 0 1 1 0 0 0 0 s s s s s P P i t t t t t i i i i i 0 v v +# +# (v2,4) memb -- "if ( Pv4 ) memb ( Rs32 + #u6:0x ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 0 0 0 0 0 0 0 s s s s s P P i t t t t t i i i i i 0 v v +# +# (v2,4) memb -- "if ( ! Pv4 ) memb ( Rs32 + #u6:0x ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 0 1 0 0 0 0 0 s s s s s P P i t t t t t i i i i i 0 v v + +:memb^PuCond0001_N25_S26 StMemRsRelxC4b,rt5 EndPacket is iclass=4 & op27=0 & op2124=0 & op2=0 & rt5 & StMemRsRelxC4b & PuCond0001_N25_S26 & $(END_PACKET) { + tmp:1 = rt5:1; + build PuCond0001_N25_S26; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + StMemRsRelxC4b = tmp; + +} + +# (v4,3) memb -- "if ( Pv4 ) memb ( Rs32 + Ru32 << #n2 ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 0 1 0 0 1 0 1 s s s s s P P n u u u u u n v v 0 0 t t t +# +# (v4,3) memb -- "if ( Pv4 .new ) memb ( Rs32 + Ru32 << #n2 ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 0 1 1 0 1 0 1 s s s s s P P n u u u u u n v v 0 0 t t t +# +# (v4,3) memb -- "if ( ! Pv4 ) memb ( Rs32 + Ru32 << #n2 ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 0 1 0 1 1 0 1 s s s s s P P n u u u u u n v v 0 0 t t t +# +# (v4,3) memb -- "if ( ! Pv4 .new ) memb ( Rs32 + Ru32 << #n2 ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 0 1 1 1 1 0 1 s s s s s P P n u u u u u n v v 0 0 t t t + +:memb^PuCond0506_N25_S24 MemRsRelShiftC3b,Nreg0002 EndPacket is iclass=3 & op2627=1 & op2123=5 & op0304=0 & Nreg0002 & MemRsRelShiftC3b & PuCond0506_N25_S24 & $(END_PACKET) { + build PuCond0506_N25_S24; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + MemRsRelShiftC3b = Nreg0002:1; + +} + +# (v4,3) memb -- "if ( Pv4 ) memb ( Rs32 + Ru32 << #n2 ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 0 1 0 0 0 0 0 s s s s s P P n u u u u u n v v t t t t t +# +# (v4,3) memb -- "if ( ! Pv4 ) memb ( Rs32 + Ru32 << #n2 ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 0 1 0 1 0 0 0 s s s s s P P n u u u u u n v v t t t t t +# +# (v4,3) memb -- "if ( Pv4 .new ) memb ( Rs32 + Ru32 << #n2 ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 0 1 1 0 0 0 0 s s s s s P P n u u u u u n v v t t t t t +# +# (v4,3) memb -- "if ( ! Pv4 .new ) memb ( Rs32 + Ru32 << #n2 ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 0 1 1 1 0 0 0 s s s s s P P n u u u u u n v v t t t t t + +:memb^PuCond0506_N25_S24 MemRsRelShiftC3b,ru5 EndPacket is iclass=3 & op2627=1 & op2223=0 & op21=0 & ru5 & MemRsRelShiftC3b & PuCond0506_N25_S24 & $(END_PACKET) { + tmp:1 = ru5:1; + build PuCond0506_N25_S24; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + MemRsRelShiftC3b = tmp; + +} + +# (v4,10) memb -- "if ( Pv4 ) memb ( Rz32 ++ #s4:0 ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 1 1 1 0 1 z z z z z P P 1 0 0 t t t 0 i i i i 0 v v +# +# (v4,10) memb -- "if ( Pv4 .new ) memb ( Rz32 ++ #s4:0 ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 1 1 1 0 1 z z z z z P P 1 0 0 t t t 1 i i i i 0 v v +# +# (v4,10) memb -- "if ( ! Pv4 ) memb ( Rz32 ++ #s4:0 ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 1 1 1 0 1 z z z z z P P 1 0 0 t t t 0 i i i i 1 v v +# +# (v4,10) memb -- "if ( ! Pv4 .new ) memb ( Rz32 ++ #s4:0 ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 1 1 1 0 1 z z z z z P P 1 0 0 t t t 1 i i i i 1 v v + +:memb^PuCond0001_N07_S02 StMemAIS4C10b,Nreg0810 EndPacket is iclass=10 & op2127=0x5d & op1113=4 & Nreg0810 & StMemAIS4C10b & PuCond0001_N07_S02 & $(END_PACKET) [ cond=1; ] { + build PuCond0001_N07_S02; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + StMemAIS4C10b = Nreg0810:1; + +} + +# (v4,10) memb -- "if ( Pv4 .new ) memb ( Rz32 ++ #s4:0 ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 1 1 0 0 0 z z z z z P P 1 t t t t t 1 i i i i 0 v v +# +# (v4,10) memb -- "if ( ! Pv4 .new ) memb ( Rz32 ++ #s4:0 ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 1 1 0 0 0 z z z z z P P 1 t t t t t 1 i i i i 1 v v +# +# (v2,10) memb -- "if ( Pv4 ) memb ( Rz32 ++ #s4:0 ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 1 1 0 0 0 z z z z z P P 1 t t t t t 0 i i i i 0 v v +# +# (v2,10) memb -- "if ( ! Pv4 ) memb ( Rz32 ++ #s4:0 ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 1 1 0 0 0 z z z z z P P 1 t t t t t 0 i i i i 1 v v + +:memb^PuCond0001_N07_S02 StMemAIS4C10b,rt5 EndPacket is iclass=10 & op2127=0x58 & op13=1 & rt5 & StMemAIS4C10b & PuCond0001_N07_S02 & $(END_PACKET) [ cond=1; ] { + tmp:1 = rt5:1; + build PuCond0001_N07_S02; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + StMemAIS4C10b = tmp; + +} + +# (v4,9) memb_fifo -- "Ryy32 = memb_fifo ( Rf32 = #U6x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 1 0 1 0 0 f f f f f P P 0 1 I I I I + I I y y y y y + + +:memb_fifo Rdd5,LdMemRsAssignxC9b EndPacket is iclass=9 & op2127=0x54 & op1213=1 & op7=0 & LdMemRsAssignxC9b & Rdd5 & $(END_PACKET) { + local tmp_byte = LdMemRsAssignxC9b; + Rdd5 = (Rdd5 >> 8) | (zext(tmp_byte) << 56); + build EndPacket; +} + +# (v4,9) memb_fifo -- "Ryy32 = memb_fifo ( Rs32 + #s11:0x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 0 i i 0 1 0 0 s s s s s P P i i i i i i i i i y y y y y + +:memb_fifo Rdd5,LdMemRsRelxC9b0 EndPacket is iclass=9 & op27=0 & op2124=4 & LdMemRsRelxC9b0 & Rdd5 & $(END_PACKET) { + local tmp_byte = LdMemRsRelxC9b0; + Rdd5 = (Rdd5 >> 8) | (zext(tmp_byte) << 56); + build EndPacket; +} + +# (v4,9) memb_fifo -- "Ryy32 = memb_fifo ( Rt32 << #n2 + #U6x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 1 0 0 1 0 0 t t t t t P P n 1 I I I I n I I y y y y y + +:memb_fifo Rdd5,LdMemRsRelShiftxC9b EndPacket is iclass=9 & op2127=0x64 & op12=1 & LdMemRsRelShiftxC9b & Rdd5 & $(END_PACKET) { + local tmp_byte = LdMemRsRelShiftxC9b; + Rdd5 = (Rdd5 >> 8) | (zext(tmp_byte) << 56); + build EndPacket; +} + +# (v4,9) memb_fifo -- "Ryy32 = memb_fifo ( Rz32 ++ #s4:0 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 1 0 1 0 0 z z z z z P P 0 0 + + + i i i i y y y y y + +:memb_fifo Rdd5,LdMemAIS4C9b0 EndPacket is iclass=9 & op2127=0x54 & op0913=0 & LdMemAIS4C9b0 & Rdd5 & $(END_PACKET) { + local tmp_byte = LdMemAIS4C9b0; + Rdd5 = (Rdd5 >> 8) | (zext(tmp_byte) << 56); + build EndPacket; +} + +# (v4,9) memb_fifo -- "Ryy32 = memb_fifo ( Rz32 ++ #s4:0 :circ ( Mu2 ) )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 0 0 1 0 0 z z z z z P P u 0 + + 0 i i i i y y y y y + +:memb_fifo Rdd5,LdMemAIS4CircMuC9b0 EndPacket is iclass=9 & op2127=0x44 & op0912=0 & LdMemAIS4CircMuC9b0 & Rdd5 & $(END_PACKET) { + local tmp_byte = LdMemAIS4CircMuC9b0; + Rdd5 = (Rdd5 >> 8) | (zext(tmp_byte) << 56); + build EndPacket; +} + +# (v4,9) memb_fifo -- "Ryy32 = memb_fifo ( Rz32 ++ Mu2 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 1 0 0 1 0 0 z z z z z P P u 0 + + + + 0 + + y y y y y +# +# (v4,9) memb_fifo -- "Ryy32 = memb_fifo ( Rz32 ++ Mu2 :brev )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 1 1 0 1 0 0 z z z z z P P u 0 + + + + 0 + + y y y y y + +:memb_fifo Rdd5,LdMemAIMuC9b EndPacket is iclass=9 & op2627=3 & op2124=4 & op0512=0 & LdMemAIMuC9b & Rdd5 & $(END_PACKET) { + local tmp_byte = LdMemAIMuC9b; + Rdd5 = (Rdd5 >> 8) | (zext(tmp_byte) << 56); + build EndPacket; +} + +# (v4,9) memb_fifo -- "Ryy32 = memb_fifo ( Rz32 ++I :circ ( Mu2 ) )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 0 0 1 0 0 z z z z z P P u 0 + + 1 + 0 + + y y y y y + +:memb_fifo Rdd5,LdMemAIICircMuC9b EndPacket is iclass=9 & op2127=0x44 & op0512=0x10 & LdMemAIICircMuC9b & Rdd5 & $(END_PACKET) { + local tmp_byte = LdMemAIICircMuC9b; + Rdd5 = (Rdd5 >> 8) | (zext(tmp_byte) << 56); + build EndPacket; +} + +# (v4,9) membh -- "Rd32 = membh ( Rf32 = #U6x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 1 0 0 0 1 f f f f f P P 0 1 I I I I + I I d d d d d + +# TODO: Uncertain how dest register is modified - could be very simple +define pcodeop membh32; # It is assumed that a byte is loaded from memory at the specified address +define pcodeop membh64; # It is assumed that a byte is loaded from memory at the specified address + +:membh Rd5,LdMemRsAssignxC9b EndPacket is iclass=9 & op2127=0x51 & op1213=1 & op7=0 & Rd5 & LdMemRsAssignxC9b & $(END_PACKET) { + Rd5 = membh32(LdMemRsAssignxC9b); + build EndPacket; +} + +# (v4,9) membh -- "Rd32 = membh ( Rs32 + #s11:1x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 0 i i 0 0 0 1 s s s s s P P i i i i i i i i i d d d d d + +:membh Rd5,LdMemRsRelxC9b1 EndPacket is iclass=9 & op27=0 & op2224=0 & op21=1 & Rd5 & LdMemRsRelxC9b1 & $(END_PACKET) { + Rd5 = membh32(LdMemRsRelxC9b1); + build EndPacket; +} + +# (v4,9) membh -- "Rd32 = membh ( Rt32 << #n2 + #U6x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 1 0 0 0 0 1 t t t t t P P n 1 I I I I n I I d d d d d + +:membh Rd5,LdMemRsRelShiftxC9b EndPacket is iclass=9 & op2127=0x61 & op12=1 & Rd5 & LdMemRsRelShiftxC9b & $(END_PACKET) { + Rd5 = membh32(LdMemRsRelShiftxC9b); + build EndPacket; +} + +# (v4,9) membh -- "Rd32 = membh ( Rz32 ++ #s4:1 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 1 0 0 0 1 z z z z z P P 0 0 + + + i i i i d d d d d + +:membh Rd5,LdMemAIS4C9b1 EndPacket is iclass=9 & op2127=0x51 & op0913=0 & Rd5 & LdMemAIS4C9b1 & $(END_PACKET) { + Rd5 = membh32(LdMemAIS4C9b1); + build EndPacket; +} + +# (v4,9) membh -- "Rd32 = membh ( Rz32 ++ #s4:1 :circ ( Mu2 ) )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 0 0 0 0 1 z z z z z P P u 0 + + 0 i i i i d d d d d + +:membh Rd5,LdMemAIS4CircMuC9b1 EndPacket is iclass=9 & op2127=0x41 & op0912=0 & Rd5 & LdMemAIS4CircMuC9b1 & $(END_PACKET) { + Rd5 = membh32(LdMemAIS4CircMuC9b1); + build EndPacket; +} + +# (v4,9) membh -- "Rd32 = membh ( Rz32 ++ Mu2 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 1 0 0 0 0 1 z z z z z P P u 0 + + + + 0 + + d d d d d +# +# (v4,9) membh -- "Rd32 = membh ( Rz32 ++ Mu2 :brev )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 1 1 0 0 0 1 z z z z z P P u 0 + + + + 0 + + d d d d d + +:membh Rd5,LdMemAIMuC9b EndPacket is iclass=9 & op2627=3 & op2124=1 & op0512=0 & Rd5 & LdMemAIMuC9b & $(END_PACKET) { + Rd5 = membh32(LdMemAIMuC9b); + build EndPacket; +} + +# (v4,9) membh -- "Rd32 = membh ( Rz32 ++I :circ ( Mu2 ) )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 0 0 0 0 1 z z z z z P P u 0 + + 1 + 0 + + d d d d d + +:membh Rd5,LdMemAIICircMuC9b EndPacket is iclass=9 & op2127=0x41 & op0512=0x10 & Rd5 & LdMemAIICircMuC9b & $(END_PACKET) { + Rd5 = membh32(LdMemAIICircMuC9b); + build EndPacket; +} + +# (v4,9) membh -- "Rdd32 = membh ( Rf32 = #U6x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 1 0 1 1 1 f f f f f P P 0 1 I I I I + I I d d d d d + +:membh Rdd5,LdMemRsAssignxC9b EndPacket is iclass=9 & op2127=0x57 & op1213=1 & op7=0 & Rdd5 & LdMemRsAssignxC9b & $(END_PACKET) { + Rdd5 = membh64(LdMemRsAssignxC9b); + build EndPacket; +} + +# (v4,9) membh -- "Rdd32 = membh ( Rs32 + #s11:2x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 0 i i 0 1 1 1 s s s s s P P i i i i i i i i i d d d d d + +:membh Rdd5,LdMemRsRelxC9b2 EndPacket is iclass=9 & op27=0 & op2224=3 & op21=1 & Rdd5 & LdMemRsRelxC9b2 & $(END_PACKET) { + Rdd5 = membh64(LdMemRsRelxC9b2); + build EndPacket; +} + +# (v4,9) membh -- "Rdd32 = membh ( Rt32 << #n2 + #U6x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 1 0 0 1 1 1 t t t t t P P n 1 I I I I n I I d d d d d + +:membh Rdd5,LdMemRsRelShiftxC9b EndPacket is iclass=9 & op2127=0x67 & op12=1 & Rdd5 & LdMemRsRelShiftxC9b & $(END_PACKET) { + Rdd5 = membh32(LdMemRsRelShiftxC9b); + build EndPacket; +} + +# (v4,9) membh -- "Rdd32 = membh ( Rz32 ++ #s4:2 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 1 0 1 1 1 z z z z z P P 0 0 + + + i i i i d d d d d + +:membh Rdd5,LdMemAIS4C9b2 EndPacket is iclass=9 & op2127=0x57 & op0913=0 & Rdd5 & LdMemAIS4C9b2 & $(END_PACKET) { + Rdd5 = membh64(LdMemAIS4C9b2); + build EndPacket; +} + +# (v4,9) membh -- "Rdd32 = membh ( Rz32 ++ #s4:2 :circ ( Mu2 ) )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 0 0 1 1 1 z z z z z P P u 0 + + 0 i i i i d d d d d + +:membh Rdd5,LdMemAIS4CircMuC9b2 EndPacket is iclass=9 & op2127=0x47 & op0912=0 & Rdd5 & LdMemAIS4CircMuC9b2 & $(END_PACKET) { + Rdd5 = membh64(LdMemAIS4CircMuC9b2); + build EndPacket; +} + +# (v4,9) membh -- "Rdd32 = membh ( Rz32 ++ Mu2 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 1 0 0 1 1 1 z z z z z P P u 0 + + + + 0 + + d d d d d +# +# (v4,9) membh -- "Rdd32 = membh ( Rz32 ++ Mu2 :brev )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 1 1 0 1 1 1 z z z z z P P u 0 + + + + 0 + + d d d d d + +:membh Rdd5,LdMemAIMuC9b EndPacket is iclass=9 & op2627=3 & op2124=7 & op0512=0 & Rdd5 & LdMemAIMuC9b & $(END_PACKET) { + Rdd5 = membh64(LdMemAIMuC9b); + build EndPacket; +} + +# (v4,9) membh -- "Rdd32 = membh ( Rz32 ++I :circ ( Mu2 ) )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 0 0 1 1 1 z z z z z P P u 0 + + 1 + 0 + + d d d d d + +:membh Rdd5,LdMemAIICircMuC9b EndPacket is iclass=9 & op2127=0x47 & op0512=0x10 & Rdd5 & LdMemAIICircMuC9b & $(END_PACKET) { + Rdd5 = membh64(LdMemAIICircMuC9b); + build EndPacket; +} + +# (v4,9) memd -- "Rdd32 = memd ( Rf32 = #U6x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 1 1 1 1 0 f f f f f P P 0 1 I I I I + I I d d d d d + +:memd Rdd5,LdMemRsAssignxC9d EndPacket is iclass=9 & op2127=0x5e & op7=0 & op1213=1 & Rdd5 & LdMemRsAssignxC9d & $(END_PACKET) { + Rdd5 = LdMemRsAssignxC9d; + build EndPacket; +} + +# (v2,9) memd -- "Rdd32 = memd ( Rs32 + #s11:3x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 0 i i 1 1 1 0 s s s s s P P i i i i i i i i i d d d d d + +:memd Rdd5,LdMemRsRelxC9d EndPacket is iclass=9 & op27=0 & op2224=7 & op21=0 & Rdd5 & LdMemRsRelxC9d & $(END_PACKET) { + Rdd5 = LdMemRsRelxC9d; + build EndPacket; +} + +# (v4,3) memd -- "Rdd32 = memd ( Rs32 + Rt32 << #n2 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 1 0 1 0 1 1 0 s s s s s P P n t t t t t n - - d d d d d + +:memd Rdd5,MemRsRelShiftC3d EndPacket is iclass=3 & op2127=0x56 & Rdd5 & MemRsRelShiftC3d & $(END_PACKET) { + Rdd5 = MemRsRelShiftC3d; + build EndPacket; +} + +# (v4,9) memd -- "Rdd32 = memd ( Rt32 << #n2 + #U6x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 1 0 1 1 1 0 t t t t t P P n 1 I I I I n I I d d d d d + +:memd Rdd5,LdMemRsRelShiftxC9d EndPacket is iclass=9 & op2127=0x6e & op12=1 & Rdd5 & LdMemRsRelShiftxC9d & $(END_PACKET) { + Rdd5 = LdMemRsRelShiftxC9d; + build EndPacket; +} + +# (v2,9) memd -- "Rdd32 = memd ( Rz32 ++ #s4:3 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 1 1 1 1 0 z z z z z P P 0 0 + + + i i i i d d d d d + +:memd Rdd5,LdMemAIS4C9d EndPacket is iclass=9 & op2127=0x5e & op0913=0 & Rdd5 & LdMemAIS4C9d & $(END_PACKET) { + Rdd5 = LdMemAIS4C9d; + build EndPacket; +} + +# (v2,9) memd -- "Rdd32 = memd ( Rz32 ++ #s4:3 :circ ( Mu2 ) )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 0 1 1 1 0 z z z z z P P u 0 + + 0 i i i i d d d d d + +:memd Rdd5,LdMemAIS4CircMuC9d EndPacket is iclass=9 & op2127=0x4e & op0912=0 & Rdd5 & LdMemAIS4CircMuC9d & $(END_PACKET) { + Rdd5 = LdMemAIS4CircMuC9d; + build EndPacket; +} + +# (v2,9) memd -- "Rdd32 = memd ( Rz32 ++ Mu2 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 1 0 1 1 1 0 z z z z z P P u 0 - - - - 0 - - d d d d d +# +# (v2,9) memd -- "Rdd32 = memd ( Rz32 ++ Mu2 :brev )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 1 1 1 1 1 0 z z z z z P P u 0 + + + + 0 + + d d d d d + +:memd Rdd5,LdMemAIMuC9d EndPacket is iclass=9 & op2627=3 & op2124=0xe & op0512=0 & Rdd5 & LdMemAIMuC9d & $(END_PACKET) { + Rdd5 = LdMemAIMuC9d; + build EndPacket; +} + +# (v2,9) memd -- "Rdd32 = memd ( Rz32 ++I :circ ( Mu2 ) )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 0 1 1 1 0 z z z z z P P u 0 + + 1 + 0 + + d d d d d + +:memd Rdd5,LdMemAIICircMuC9d EndPacket is iclass=9 & op2127=0x4e & op0512=0x10 & Rdd5 & LdMemAIICircMuC9d & $(END_PACKET) { + Rdd5 = LdMemAIICircMuC9d; + build EndPacket; +} + +# (v2,4) memd -- "Rdd32 = memd ( gp + #u16:3x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 1 i i 1 1 1 0 i i i i i P P i i i i i i i i i d d d d d + +:memd Rdd5,LdMemGPRelxC4d EndPacket is iclass=4 & op27=1 & op2224=7 & op21=0 & Rdd5 & LdMemGPRelxC4d & $(END_PACKET) { + Rdd5 = LdMemGPRelxC4d; + build EndPacket; +} + + +# (v4,10) memd -- "memd ( Rf32 = #U6x ) = Rtt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 1 1 1 1 0 f f f f f P P 0 t t t t t 1 + I I I I I I + +:memd StMemRsAssignxC10d,rtt5 EndPacket is iclass=10 & op2127=0x5e & op13=0 & op0607=2 & rtt5 & StMemRsAssignxC10d & $(END_PACKET) { + tmp:8 = rtt5; + build EndPacket; + <> + StMemRsAssignxC10d = tmp; +} + +# (v2,10) memd -- "memd ( Rs32 + #s11:3x ) = Rtt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 0 i i 1 1 1 0 s s s s s P P i t t t t t i i i i i i i i + +:memd StMemRsRelxC10d,rtt5 EndPacket is iclass=10 & op27=0 & op2224=7 & op21=0 & rtt5 & StMemRsRelxC10d & $(END_PACKET) { + tmp:8 = rtt5; + build EndPacket; + <> + StMemRsRelxC10d = tmp; +} + +# (v4,3) memd -- "memd ( Rs32 + Ru32 << #n2 ) = Rtt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 1 0 1 1 1 1 0 s s s s s P P n u u u u u n - - t t t t t + +:memd MemRsRelShiftC3d,ruu5 EndPacket is iclass=3 & op2127=0x5e & ruu5 & MemRsRelShiftC3d & $(END_PACKET) { + tmp:8 = ruu5; + build EndPacket; + <> + MemRsRelShiftC3d = tmp; +} + +# (v4,10) memd -- "memd ( Ru32 << #n2 + #U6x ) = Rtt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 1 0 1 1 1 0 u u u u u P P n t t t t t 1 n I I I I I I + +:memd StMemRsRelShiftxC10d,rtt5 EndPacket is iclass=10 & op2127=0x6e & op7=1 & rtt5 & StMemRsRelShiftxC10d & $(END_PACKET) { + tmp:8 = rtt5; + build EndPacket; + <> + StMemRsRelShiftxC10d = tmp; +} + +# (v2,10) memd -- "memd ( Rz32 ++ #s4:3 ) = Rtt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 1 1 1 1 0 z z z z z P P 0 t t t t t 0 i i i i + 0 + + +:memd StMemAIS4C10d,rtt5 EndPacket is iclass=10 & op2127=0x5e & op13=0 & op7=0 & op0002=0 & rtt5 & StMemAIS4C10d & $(END_PACKET) { + tmp:8 = rtt5; + build EndPacket; + <> + StMemAIS4C10d = tmp; +} + +# (v2,10) memd -- "memd ( Rz32 ++ #s4:3 :circ ( Mu2 ) ) = Rtt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 0 1 1 1 0 z z z z z P P u t t t t t 0 i i i i + 0 + + +:memd StMemAIS4CircMuC10d,rtt5 EndPacket is iclass=10 & op2127=0x4e & op7=0 & op0002=0 & rtt5 & StMemAIS4CircMuC10d & $(END_PACKET) { + tmp:8 = rtt5; + build EndPacket; + <> + StMemAIS4CircMuC10d = tmp; +} + +# (v2,10) memd -- "memd ( Rz32 ++ Mu2 ) = Rtt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 1 0 1 1 1 0 z z z z z P P u t t t t t 0 + + + + + + + +# +# (v2,10) memd -- "memd ( Rz32 ++ Mu2 :brev ) = Rtt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 1 1 1 1 1 0 z z z z z P P u t t t t t 0 + + + + + + + + +:memd StMemAIMuC10d,rtt5 EndPacket is iclass=10 & op2627=3 & op2124=0xe & rtt5 & StMemAIMuC10d & $(END_PACKET) { + tmp:8 = rtt5; + build EndPacket; + <> + StMemAIMuC10d = tmp; +} + +# (v2,10) memd -- "memd ( Rz32 ++I :circ ( Mu2 ) ) = Rtt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 0 1 1 1 0 z z z z z P P u t t t t t 0 + + + + + 1 + + +:memd StMemAIICircMuC10d,rtt5 EndPacket is iclass=10 & op2127=0x4e & op0007=2 & rtt5 & StMemAIICircMuC10d & $(END_PACKET) { + tmp:8 = rtt5; + build EndPacket; + <> + StMemAIICircMuC10d = tmp; +} + +# (v2,4) memd -- "memd ( gp + #u16:3x ) = Rtt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 1 i i 0 1 1 0 i i i i i P P i t t t t t i i i i i i i i + +:memd StMemGPRelxC4d,rtt5 EndPacket is iclass=4 & op27=1 & op2224=3 & op21=0 & rtt5 & StMemGPRelxC4d & $(END_PACKET) { + tmp:8 = rtt5; + build EndPacket; + <> + StMemGPRelxC4d = tmp; +} + +# (v4,9) memd -- "if ( Pt4 ) Rdd32 = memd ( #u6x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 1 1 1 1 1 0 i i i i i P P 1 0 0 t t i 1 + + d d d d d +# +# (v4,9) memd -- "if ( ! Pt4 ) Rdd32 = memd ( #u6x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 1 1 1 1 1 0 i i i i i P P 1 0 1 t t i 1 + + d d d d d +# +# (v4,9) memd -- "if ( Pt4 .new ) Rdd32 = memd ( #u6x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 1 1 1 1 1 0 i i i i i P P 1 1 0 t t i 1 + + d d d d d +# +# (v4,9) memd -- "if ( ! Pt4 .new ) Rdd32 = memd ( #u6x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 1 1 1 1 1 0 i i i i i P P 1 1 1 t t i 1 + + d d d d d + +:memd^PuCond0910_N12_S11 rdd5,LdMemAbsU6xC9d EndPacket is iclass=9 & op2127=0x7e & op13=1 & op0507=4 & rdd5 & LdMemAbsU6xC9d & PuCond0910_N12_S11 & $(END_PACKET) { + tmp:8 = 0; + build PuCond0910_N12_S11; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + tmp = LdMemAbsU6xC9d; + + <> + if (ConditionReg == 0) goto ; + rdd5 = tmp; + +} + +# (v2,4) memd -- "if ( Pt4 ) Rdd32 = memd ( Rs32 + #u6:3x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 0 0 0 1 1 1 0 s s s s s P P 0 t t i i i i i i d d d d d +# +# (v2,4) memd -- "if ( ! Pt4 ) Rdd32 = memd ( Rs32 + #u6:3x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 0 1 0 1 1 1 0 s s s s s P P 0 t t i i i i i i d d d d d +# +# (v2,4) memd -- "if ( Pt4 .new ) Rdd32 = memd ( Rs32 + #u6:3x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 0 0 1 1 1 1 0 s s s s s P P 0 t t i i i i i i d d d d d +# +# (v2,4) memd -- "if ( ! Pt4 .new ) Rdd32 = memd ( Rs32 + #u6:3x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 0 1 1 1 1 1 0 s s s s s P P 0 t t i i i i i i d d d d d + +:memd^PuCond1112_N25_S26 rdd5,LdMemRsRelxC4d EndPacket is iclass=4 & op27=0 & op2224=7 & op21=0 & op13=0 & rdd5 & LdMemRsRelxC4d & PuCond1112_N25_S26 & $(END_PACKET) { + tmp:8 = 0; + build PuCond1112_N25_S26; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + tmp = LdMemRsRelxC4d; + + <> + if (ConditionReg == 0) goto ; + rdd5 = tmp; + +} + +# (v2,9) memd -- "if ( Pt4 ) Rdd32 = memd ( Rz32 ++ #s4:3 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 1 1 1 1 0 z z z z z P P 1 0 0 t t i i i i d d d d d +# +# (v2,9) memd -- "if ( ! Pt4 ) Rdd32 = memd ( Rz32 ++ #s4:3 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 1 1 1 1 0 z z z z z P P 1 0 1 t t i i i i d d d d d +# +# (v4,9) memd -- "if ( Pt4 .new ) Rdd32 = memd ( Rz32 ++ #s4:3 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 1 1 1 1 0 z z z z z P P 1 1 0 t t i i i i d d d d d +# +# (v4,9) memd -- "if ( ! Pt4 .new ) Rdd32 = memd ( Rz32 ++ #s4:3 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 1 1 1 1 0 z z z z z P P 1 1 1 t t i i i i d d d d d + +:memd^PuCond0910_N12_S11 rdd5,LdMemAIS4C9d EndPacket is iclass=9 & op2127=0x5e & op13=1 & rdd5 & LdMemAIS4C9d & PuCond0910_N12_S11 & $(END_PACKET) [ cond=1; ] { + tmp:8 = 0; + build PuCond0910_N12_S11; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + tmp = LdMemAIS4C9d; + + <> + if (ConditionReg == 0) goto ; + rdd5 = tmp; + +} + +# (v4,3) memd -- "if ( Pv4 ) Rdd32 = memd ( Rs32 + Rt32 << #n2 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 0 0 0 0 1 1 0 s s s s s P P n t t t t t n v v d d d d d +# +# (v4,3) memd -- "if ( ! Pv4 ) Rdd32 = memd ( Rs32 + Rt32 << #n2 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 0 0 0 1 1 1 0 s s s s s P P n t t t t t n v v d d d d d +# +# (v4,3) memd -- "if ( Pv4 .new ) Rdd32 = memd ( Rs32 + Rt32 << #n2 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 0 0 1 0 1 1 0 s s s s s P P n t t t t t n v v d d d d d +# +# (v4,3) memd -- "if ( ! Pv4 .new ) Rdd32 = memd ( Rs32 + Rt32 << #n2 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 0 0 1 1 1 1 0 s s s s s P P n t t t t t n v v d d d d d + +:memd^PuCond0506_N25_S24 rdd5,MemRsRelShiftC3d EndPacket is iclass=3 & op2627=0 & op2123=6 & rdd5 & MemRsRelShiftC3d & PuCond0506_N25_S24 & $(END_PACKET) { + tmp:8 = 0; + build PuCond0506_N25_S24; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + tmp = MemRsRelShiftC3d; + + <> + if (ConditionReg == 0) goto ; + rdd5 = tmp; + +} + +# (v4,10) memd -- "if ( Pv4 ) memd ( #u6x ) = Rtt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 1 1 1 1 1 0 + + + i i P P 0 t t t t t 1 i i i i 0 v v +# +# (v4,10) memd -- "if ( ! Pv4 ) memd ( #u6x ) = Rtt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 1 1 1 1 1 0 + + + i i P P 0 t t t t t 1 i i i i 1 v v +# +# (v4,10) memd -- "if ( Pv4 .new ) memd ( #u6x ) = Rtt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 1 1 1 1 1 0 + + + i i P P 1 t t t t t 1 i i i i 0 v v +# +# (v4,10) memd -- "if ( ! Pv4 .new ) memd ( #u6x ) = Rtt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 1 1 1 1 1 0 + + + i i P P 1 t t t t t 1 i i i i 1 v v + +:memd^PuCond0001_N13_S02 StMemAbsU6xC10d,rtt5 EndPacket is iclass=10 & op2127=0x7e & op1820=0 & op7=1 & rtt5 & StMemAbsU6xC10d & PuCond0001_N13_S02 & $(END_PACKET) { + tmp:8 = rtt5; + build PuCond0001_N13_S02; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + StMemAbsU6xC10d = tmp; + +} + +# (v4,4) memd -- "if ( Pv4 .new ) memd ( Rs32 + #u6:3x ) = Rtt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 0 0 1 0 1 1 0 s s s s s P P i t t t t t i i i i i 0 v v +# +# (v4,4) memd -- "if ( ! Pv4 .new ) memd ( Rs32 + #u6:3x ) = Rtt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 0 1 1 0 1 1 0 s s s s s P P i t t t t t i i i i i 0 v v +# +# (v2,4) memd -- "if ( Pv4 ) memd ( Rs32 + #u6:3x ) = Rtt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 0 0 0 0 1 1 0 s s s s s P P i t t t t t i i i i i 0 v v +# +# (v2,4) memd -- "if ( ! Pv4 ) memd ( Rs32 + #u6:3x ) = Rtt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 0 1 0 0 1 1 0 s s s s s P P i t t t t t i i i i i 0 v v + +:memd^PuCond0001_N25_S26 StMemRsRelxC4d,rtt5 EndPacket is iclass=4 & op27=0 & op2224=3 & op21=0 & op2=0 & rtt5 & StMemRsRelxC4d & PuCond0001_N25_S26 & $(END_PACKET) { + tmp:8 = rtt5; + build PuCond0001_N25_S26; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + StMemRsRelxC4d = tmp; + +} + +# (v4,3) memd -- "if ( Pv4 ) memd ( Rs32 + Ru32 << #n2 ) = Rtt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 0 1 0 0 1 1 0 s s s s s P P n u u u u u n v v t t t t t +# +# (v4,3) memd -- "if ( ! Pv4 ) memd ( Rs32 + Ru32 << #n2 ) = Rtt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 0 1 0 1 1 1 0 s s s s s P P n u u u u u n v v t t t t t +# +# (v4,3) memd -- "if ( Pv4 .new ) memd ( Rs32 + Ru32 << #n2 ) = Rtt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 0 1 1 0 1 1 0 s s s s s P P n u u u u u n v v t t t t t +# +# (v4,3) memd -- "if ( ! Pv4 .new ) memd ( Rs32 + Ru32 << #n2 ) = Rtt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 0 1 1 1 1 1 0 s s s s s P P n u u u u u n v v t t t t t + +:memd^PuCond0506_N25_S24 MemRsRelShiftC3d,ruu5 EndPacket is iclass=3 & op2627=1 & op2223=3 & op21=0 & ruu5 & MemRsRelShiftC3d & PuCond0506_N25_S24 & $(END_PACKET) { + tmp:8 = ruu5; + build PuCond0506_N25_S24; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + MemRsRelShiftC3d = tmp; + +} + +# (v4,10) memd -- "if ( Pv4 .new ) memd ( Rz32 ++ #s4:3 ) = Rtt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 1 1 1 1 0 z z z z z P P 1 t t t t t 1 i i i i 0 v v +# +# (v4,10) memd -- "if ( ! Pv4 .new ) memd ( Rz32 ++ #s4:3 ) = Rtt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 1 1 1 1 0 z z z z z P P 1 t t t t t 1 i i i i 1 v v +# +# (v2,10) memd -- "if ( Pv4 ) memd ( Rz32 ++ #s4:3 ) = Rtt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 1 1 1 1 0 z z z z z P P 1 t t t t t 0 i i i i 0 v v +# +# (v2,10) memd -- "if ( ! Pv4 ) memd ( Rz32 ++ #s4:3 ) = Rtt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 1 1 1 1 0 z z z z z P P 1 t t t t t 0 i i i i 1 v v + +:memd^PuCond0001_N07_S02 StMemAIS4C10d,rtt5 EndPacket is iclass=10 & op2127=0x5e & op13=1 & rtt5 & StMemAIS4C10d & PuCond0001_N07_S02 & $(END_PACKET) [ cond=1; ] { + tmp:8 = rtt5; + build PuCond0001_N07_S02; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + StMemAIS4C10d = tmp; + +} + +# memd_aq -- "Rdd32 = memd_aq ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 0 0 1 0 0 0 0 s s s s s P P 0 1 1 - - - 0 0 0 d d d d d + +:memd_aq Rdd5,LdMemRsRelC9d EndPacket is iclass=9 & op2527=1 & op2224=0 & op21=0 & Rdd5 & op1113=3 & op0810=0 & op0507=0 & LdMemRsRelC9d & $(END_PACKET) { + Rdd5 = LdMemRsRelC9d; + build EndPacket; +} + +# memd_rl -- "memd_rl ( Rs32 ):at = Rtt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 0 0 0 0 1 1 1 s s s s s P P 0 t t t t t - - 0 0 1 0 d d +define pcodeop waitAllThreads; +:memd_rl":at" StMemRsRelPdC9d, rtt5 EndPacket is iclass=0xa & op2527=0 & op2224=3 & op21=1 & op13=0 & rtt5 & op0607=0 & op0205=0x2 & StMemRsRelPdC9d & $(END_PACKET) { + tmp:8 = rtt5; + build EndPacket; + <> + waitAllThreads(); + StMemRsRelPdC9d = tmp; +} + +# memd_rl -- "memd_rl ( Rs32 ):st = Rtt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 0 0 0 0 1 1 1 s s s s s P P 0 t t t t t - - 1 0 1 0 d d +define pcodeop waitSameDomain; +:memd_rl":st" StMemRsRelPdC9d, rtt5 EndPacket is iclass=0xa & op2527=0 & op2224=3 & op21=1 & op13=0 & rtt5 & op0607=0 & op0205=0xa & StMemRsRelPdC9d & $(END_PACKET) { + tmp:8 = rtt5; + build EndPacket; + <> + waitSameDomain(); + StMemRsRelPdC9d = tmp; +} + +# (v4,9) memd_locked -- "Rdd32 = memd_locked ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 0 0 1 0 0 0 0 s s s s s P P 0 1 + + + + + + + d d d d d + +:memd_locked Rdd5,StMemRsRelPdC9d EndPacket is iclass=9 & op2127=0x10 & op0513=0x80 & Rdd5 & StMemRsRelPdC9d & $(END_PACKET) { + # NOTE: Manual does not indicate lock use, cannot be group with other instructions + Rdd5 = StMemRsRelPdC9d; + build EndPacket; +} + +# (v4,10) memd_locked -- "memd_locked ( Rs32 , Pd4 ) = Rtt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 0 0 0 0 1 1 1 s s s s s P P + t t t t t + + + + + + d d + +:memd_locked StMemRsRelPdC9d,rtt5 EndPacket is iclass=10 & op2127=0x07 & op13=0 & op0207=0 & StMemRsRelPdC9d & rtt5 & pu0001 & $(END_PACKET) { + # NOTE: cannot be group with other instructions + rc:1 = lock(); + lockOK:1 = rc != 0; + tmp:8 = rtt5; + build EndPacket; + <> + pu0001 = lockOK * 0xff; + <> + if (!lockOK) goto ; + StMemRsRelPdC9d = tmp; + unlock(); + +} + +# (v4,9) memh -- "Rd32 = memh ( Rf32 = #U6x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 1 1 0 1 0 f f f f f P P 0 1 I I I I + I I d d d d d + +:memh Rd5,LdMemRsAssignxC9h EndPacket is iclass=9 & op2127=0x5a & op1213=1 & op7=0 & Rd5 & LdMemRsAssignxC9h & $(END_PACKET) { + Rd5 = sext(LdMemRsAssignxC9h); + build EndPacket; +} + +# (v2,9) memh -- "Rd32 = memh ( Rs32 + #s11:1x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 0 i i 1 0 1 0 s s s s s P P i i i i i i i i i d d d d d + +:memh Rd5,LdMemRsRelxC9h EndPacket is iclass=9 & op27=0 & op2224=5 & op21=0 & Rd5 & LdMemRsRelxC9h & $(END_PACKET) { + Rd5 = sext(LdMemRsRelxC9h); + build EndPacket; +} + +# (v4,3) memh -- "Rd32 = memh ( Rs32 + Rt32 << #n2 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 1 0 1 0 0 1 0 s s s s s P P n t t t t t n + + d d d d d + +:memh Rd5,MemRsRelShiftC3h EndPacket is iclass=3 & op2127=0x52 & op0506=0 & Rd5 & MemRsRelShiftC3h & $(END_PACKET) { + Rd5 = sext(MemRsRelShiftC3h); + build EndPacket; +} + +# (v4,9) memh -- "Rd32 = memh ( Rt32 << #n2 + #U6x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 1 0 1 0 1 0 t t t t t P P n 1 I I I I n I I d d d d d + +:memh Rd5,LdMemRsRelShiftxC9h EndPacket is iclass=9 & op2127=0x6a & op12=1 & Rd5 & LdMemRsRelShiftxC9h & $(END_PACKET) { + Rd5 = sext(LdMemRsRelShiftxC9h); + build EndPacket; +} + +# (v2,9) memh -- "Rd32 = memh ( Rz32 ++ #s4:1 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 1 1 0 1 0 z z z z z P P 0 0 + + + i i i i d d d d d + +:memh Rd5,LdMemAIS4C9h EndPacket is iclass=9 & op2127=0x5a & op0913=0 & Rd5 & LdMemAIS4C9h & $(END_PACKET) { + Rd5 = sext(LdMemAIS4C9h); + build EndPacket; +} + +# (v2,9) memh -- "Rd32 = memh ( Rz32 ++ #s4:1 :circ ( Mu2 ) )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 0 1 0 1 0 z z z z z P P u 0 + + 0 i i i i d d d d d + +:memh Rd5,LdMemAIS4CircMuC9h EndPacket is iclass=9 & op2127=0x4a & op0912=0 & Rd5 & LdMemAIS4CircMuC9h & $(END_PACKET) { + Rd5 = sext(LdMemAIS4CircMuC9h); + build EndPacket; +} + +# (v2,9) memh -- "Rd32 = memh ( Rz32 ++ Mu2 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 1 0 1 0 1 0 z z z z z P P u 0 + + + + 0 + + d d d d d +# +# (v2,9) memh -- "Rd32 = memh ( Rz32 ++ Mu2 :brev )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 1 1 1 0 1 0 z z z z z P P u 0 + + + + 0 + + d d d d d + +:memh Rd5,LdMemAIMuC9h EndPacket is iclass=9 & op2627=3 & op2124=0xa & op0512=0 & Rd5 & LdMemAIMuC9h & $(END_PACKET) { + Rd5 = sext(LdMemAIMuC9h); + build EndPacket; +} + +# (v2,9) memh -- "Rd32 = memh ( Rz32 ++I :circ ( Mu2 ) )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 0 1 0 1 0 z z z z z P P u 0 + + 1 + 0 + + d d d d d + +:memh Rd5,LdMemAIICircMuC9h EndPacket is iclass=9 & op2127=0x4a & op0512=0x10 & Rd5 & LdMemAIICircMuC9h & $(END_PACKET) { + Rd5 = sext(LdMemAIICircMuC9h); + build EndPacket; +} + +# (v2,4) memh -- "Rd32 = memh ( gp + #u16:1x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 1 i i 1 0 1 0 i i i i i P P i i i i i i i i i d d d d d + +:memh Rd5,LdMemGPRelxC4h EndPacket is iclass=4 & op27=1 & op2224=5 & op21=0 & Rd5 & LdMemGPRelxC4h & $(END_PACKET) { + Rd5 = sext(LdMemGPRelxC4h); + build EndPacket; +} + +# (v4,10) memh -- "memh ( Rf32 = #U6x ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 1 1 1 0 1 f f f f f P P 0 0 1 t t t 1 + I I I I I I + +:memh StMemRsAssignxC10h,Nreg0810 EndPacket is iclass=10 & op2127=0x5d & op1113=1 & op0607=2 & Nreg0810 & StMemRsAssignxC10h & $(END_PACKET) { + build EndPacket; + <> + StMemRsAssignxC10h = Nreg0810:2; +} + +# (v4,10) memh -- "memh ( Rf32 = #U6x ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 1 1 0 1 0 f f f f f P P 0 t t t t t 1 + I I I I I I +# +# (v4,10) memh -- "memh ( Rf32 = #U6x ) = Rt32.h" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 1 1 0 1 1 f f f f f P P 0 t t t t t 1 + I I I I I I + +:memh StMemRsAssignxC10h,Rt5HL21 EndPacket is iclass=10 & op2227=0x2d & op13=0 & op0607=2 & Rt5HL21 & StMemRsAssignxC10h & $(END_PACKET) { + tmp:2 = Rt5HL21; + build EndPacket; + <> + StMemRsAssignxC10h = tmp; +} + +# (v4,10) memh -- "memh ( Rs32 + #s11:1x ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 0 i i 1 1 0 1 s s s s s P P i 0 1 t t t i i i i i i i i + +:memh StMemRsRelxC10h,Nreg0810 EndPacket is iclass=10 & op27=0 & op2224=6 & op21=1 & op1112=1 & Nreg0810 & StMemRsRelxC10h & $(END_PACKET) { + build EndPacket; + <> + StMemRsRelxC10h = Nreg0810:2; +} + +# (v2,10) memh -- "memh ( Rs32 + #s11:1x ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 0 i i 1 0 1 0 s s s s s P P i t t t t t i i i i i i i i +# +# (v2,10) memh -- "memh ( Rs32 + #s11:1x ) = Rt32.h" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 0 i i 1 0 1 1 s s s s s P P i t t t t t i i i i i i i i + +:memh StMemRsRelxC10h,Rt5HL21 EndPacket is iclass=10 & op27=0 & op2224=5 & Rt5HL21 & StMemRsRelxC10h & $(END_PACKET) { + tmp:2 = Rt5HL21; + build EndPacket; + <> + StMemRsRelxC10h = tmp; +} + +# (v4,3) memh -- "memh ( Rs32 + #u6:1 ) = #S8x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 1 1 0 + + 0 1 s s s s s P P I i i i i i i I I I I I I I + +:memh StMemRsRelC3h,Simm16_13_0006x EndPacket is iclass=3 & op2127=0x61 & StMemRsRelC3h & Simm16_13_0006x & $(END_PACKET) { + build EndPacket; + <> + StMemRsRelC3h = Simm16_13_0006x; +} + +# (v4,3) memh -- "memh ( Rs32 + #u6:1x ) &= Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 1 1 1 0 + 0 1 s s s s s P P 0 i i i i i i 1 0 t t t t t + +:memh&= StMemRsRelxC3h,ru5 EndPacket is iclass=3 & op2127=0x71 & op13=0 & op0506=2 & StMemRsRelxC3h & ru5 & $(END_PACKET) { + tmp:2 = StMemRsRelxC3h & ru5:2; + build EndPacket; + <> + StMemRsRelxC3h = tmp; +} + +# (v4,3) memh -- "memh ( Rs32 + #u6:1x ) += #U5" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 1 1 1 1 + 0 1 s s s s s P P 0 i i i i i i 0 0 I I I I I + +:memh+= StMemRsRelxC3h,Uimm8_0004 EndPacket is iclass=3 & op2127=0x79 & op13=0 & op0506=0 & StMemRsRelxC3h & Uimm8_0004 & $(END_PACKET) { + tmp:2 = StMemRsRelxC3h + zext(Uimm8_0004); + build EndPacket; + <> + StMemRsRelxC3h = tmp; +} + +# (v4,3) memh -- "memh ( Rs32 + #u6:1x ) += Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 1 1 1 0 + 0 1 s s s s s P P 0 i i i i i i 0 0 t t t t t + +:memh+= StMemRsRelxC3h,ru5 EndPacket is iclass=3 & op2127=0x71 & op13=0 & op0506=0 & StMemRsRelxC3h & ru5 & $(END_PACKET) { + tmp:2 = StMemRsRelxC3h + ru5:2; + build EndPacket; + <> + StMemRsRelxC3h = tmp; +} + +# (v4,3) memh -- "memh ( Rs32 + #u6:1x ) -= #U5" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 1 1 1 1 + 0 1 s s s s s P P 0 i i i i i i 0 1 I I I I I + +:memh-= StMemRsRelxC3h,Uimm8_0004 EndPacket is iclass=3 & op2127=0x79 & op13=0 & op0506=1 & StMemRsRelxC3h & Uimm8_0004 & $(END_PACKET) { + tmp:2 = StMemRsRelxC3h - zext(Uimm8_0004); + build EndPacket; + <> + StMemRsRelxC3h = tmp; +} + +# (v4,3) memh -- "memh ( Rs32 + #u6:1x ) -= Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 1 1 1 0 + 0 1 s s s s s P P 0 i i i i i i 0 1 t t t t t + +:memh-= StMemRsRelxC3h,ru5 EndPacket is iclass=3 & op2127=0x71 & op13=0 & op0506=1 & StMemRsRelxC3h & ru5 & $(END_PACKET) { + tmp:2 = StMemRsRelxC3h - ru5:2; + build EndPacket; + <> + StMemRsRelxC3h = tmp; +} + +# (v4,3) memh -- "memh ( Rs32 + #u6:1x ) = clrbit ( #U5 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 1 1 1 1 + 0 1 s s s s s P P 0 i i i i i i 1 0 I I I I I + +:memh StMemRsRelxC3h,ClrBit_0004h EndPacket is iclass=3 & op2127=0x79 & op13=0 & op0506=2 & StMemRsRelxC3h & ClrBit_0004h & $(END_PACKET) { + tmp:2 = StMemRsRelxC3h & ClrBit_0004h; + build EndPacket; + <> + StMemRsRelxC3h = tmp; +} + +# (v4,3) memh -- "memh ( Rs32 + #u6:1x ) = setbit ( #U5 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 1 1 1 1 + 0 1 s s s s s P P 0 i i i i i i 1 1 I I I I I + +:memh StMemRsRelxC3h,SetBit_0004h EndPacket is iclass=3 & op2127=0x79 & op13=0 & op0506=3 & StMemRsRelxC3h & SetBit_0004h & $(END_PACKET) { + tmp:2 = StMemRsRelxC3h | SetBit_0004h; + build EndPacket; + <> + StMemRsRelxC3h = tmp; +} + +# (v4,3) memh -- "memh ( Rs32 + #u6:1x ) |= Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 1 1 1 0 + 0 1 s s s s s P P 0 i i i i i i 1 1 t t t t t + +:memh|= StMemRsRelxC3h,ru5 EndPacket is iclass=3 & op2127=0x71 & op13=0 & op0506=3 & StMemRsRelxC3h & ru5 & $(END_PACKET) { + tmp:2 = StMemRsRelxC3h | ru5:2; + build EndPacket; + <> + StMemRsRelxC3h = tmp; +} + +# (v4,3) memh -- "memh ( Rs32 + Ru32 << #n2 ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 1 0 1 1 1 0 1 s s s s s P P n u u u u u n + + 0 1 t t t + +:memh MemRsRelShiftC3h,Nreg0002 EndPacket is iclass=3 & op2127=0x5d & op0306=1 & MemRsRelShiftC3h & Nreg0002 & $(END_PACKET) { + build EndPacket; + <> + MemRsRelShiftC3h = Nreg0002:2; +} + +# (v4,3) memh -- "memh ( Rs32 + Ru32 << #n2 ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 1 0 1 1 0 1 0 s s s s s P P n u u u u u n + + t t t t t +# +# (v4,3) memh -- "memh ( Rs32 + Ru32 << #n2 ) = Rt32.h" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 1 0 1 1 0 1 1 s s s s s P P n u u u u u n + + t t t t t + +:memh MemRsRelShiftC3h,Ru5HL21 EndPacket is iclass=3 & op2227=0x2d & op0506=0 & MemRsRelShiftC3h & Ru5HL21 & $(END_PACKET) { + tmp:2 = Ru5HL21; + build EndPacket; + <> + MemRsRelShiftC3h = tmp; +} + +# (v4,10) memh -- "memh ( Ru32 << #n2 + #U6x ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 1 0 1 1 0 1 u u u u u P P n 0 1 t t t 1 n I I I I I I + +:memh StMemRsRelShiftxC10h,Nreg0810 EndPacket is iclass=10 & op2127=0x6d & op1112=1 & op7=1 & Nreg0810 & StMemRsRelShiftxC10h & $(END_PACKET) { + build EndPacket; + <> + StMemRsRelShiftxC10h = Nreg0810:2; +} + +# (v4,10) memh -- "memh ( Ru32 << #n2 + #U6x ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 1 0 1 0 1 0 u u u u u P P n t t t t t 1 n I I I I I I +# +# (v4,10) memh -- "memh ( Ru32 << #n2 + #U6x ) = Rt32.h" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 1 0 1 0 1 1 u u u u u P P n t t t t t 1 n I I I I I I + +:memh StMemRsRelShiftxC10h,Rt5HL21 EndPacket is iclass=10 & op2227=0x35 & op7=1 & Rt5HL21 & StMemRsRelShiftxC10h & $(END_PACKET) { + tmp:2 = Rt5HL21; + build EndPacket; + <> + StMemRsRelShiftxC10h = tmp; +} + +# (v4,10) memh -- "memh ( Rz32 ++ #s4:1 ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 1 1 1 0 1 z z z z z P P 0 0 1 t t t 0 i i i i + 0 + + +:memh StMemAIS4C10h,Nreg0810 EndPacket is iclass=10 & op2127=0x5d & op1113=1 & op7=0 & op0002=0 & Nreg0810 & StMemAIS4C10h & $(END_PACKET) { + build EndPacket; + <> + StMemAIS4C10h = Nreg0810:2; +} + +# (v4,10) memh -- "memh ( Rz32 ++ #s4:1 :circ ( Mu2 ) ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 0 1 1 0 1 z z z z z P P u 0 1 t t t 0 i i i i + 0 + + +:memh StMemAIS4CircMuC10h,Nreg0810 EndPacket is iclass=10 & op2127=0x4d & op1112=1 & op7=0 & op0002=0 & Nreg0810 & StMemAIS4CircMuC10h & $(END_PACKET) { + build EndPacket; + <> + StMemAIS4CircMuC10h = Nreg0810:2; +} + +# (v4,10) memh -- "memh ( Rz32 ++ Mu2 ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 1 0 1 1 0 1 z z z z z P P u 0 1 t t t 0 + + + + + + + +# +# (v4,10) memh -- "memh ( Rz32 ++ Mu2 :brev ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 1 1 1 1 0 1 z z z z z P P u 0 1 t t t 0 + + + + + + + + +:memh StMemAIMuC10h,Nreg0810 EndPacket is iclass=10 & op2627=3 & op2124=0xd & op1112=1 & op0007=0 & Nreg0810 & StMemAIMuC10h & $(END_PACKET) { + build EndPacket; + <> + StMemAIMuC10h = Nreg0810:2; +} + +# (v4,10) memh -- "memh ( Rz32 ++I :circ ( Mu2 ) ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 0 1 1 0 1 z z z z z P P u 0 1 t t t 0 + + + + + 1 + + +:memh StMemAIICircMuC10h,Nreg0810 EndPacket is iclass=10 & op2127=0x4d & op1112=1 & op0007=2 & Nreg0810 & StMemAIICircMuC10h & $(END_PACKET) { + build EndPacket; + <> + StMemAIICircMuC10h = Nreg0810:2; +} + +# (v2,10) memh -- "memh ( Rz32 ++ #s4:1 ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 1 1 0 1 0 z z z z z P P 0 t t t t t 0 i i i i + 0 + +# +# (v2,10) memh -- "memh ( Rz32 ++ #s4:1 ) = Rt32.h" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 1 1 0 1 1 z z z z z P P 0 t t t t t 0 i i i i + 0 + + +:memh StMemAIS4C10h,Rt5HL21 EndPacket is iclass=10 & op2227=0x2d & op13=0 & op7=0 & op0002=0 & Rt5HL21 & StMemAIS4C10h & $(END_PACKET) { + tmp:2 = Rt5HL21; + build EndPacket; + <> + StMemAIS4C10h = tmp; +} + +# (v2,10) memh -- "memh ( Rz32 ++ #s4:1 :circ ( Mu2 ) ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 0 1 0 1 0 z z z z z P P u t t t t t 0 i i i i + 0 + +# +# (v2,10) memh -- "memh ( Rz32 ++ #s4:1 :circ ( Mu2 ) ) = Rt32.h" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 0 1 0 1 1 z z z z z P P u t t t t t 0 i i i i + 0 + + +:memh StMemAIS4CircMuC10h,Rt5HL21 EndPacket is iclass=10 & op2227=0x25 & op7=0 & op0002=0 & Rt5HL21 & StMemAIS4CircMuC10h & $(END_PACKET) { + tmp:2 = Rt5HL21; + build EndPacket; + <> + StMemAIS4CircMuC10h = tmp; +} + +# (v2,10) memh -- "memh ( Rz32 ++ Mu2 ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 1 0 1 0 1 0 z z z z z P P u t t t t t 0 - - - - - - - +# +# (v2,10) memh -- "memh ( Rz32 ++ Mu2 ) = Rt32.h" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 1 0 1 0 1 1 z z z z z P P u t t t t t 0 - - - - - - - +# +# (v2,10) memh -- "memh ( Rz32 ++ Mu2 :brev ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 1 1 1 0 1 0 z z z z z P P u t t t t t 0 + + + + + + + +# +# (v2,10) memh -- "memh ( Rz32 ++ Mu2 :brev ) = Rt32.h" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 1 1 1 0 1 1 z z z z z P P u t t t t t 0 + + + + + + + + +:memh StMemAIMuC10h,Rt5HL21 EndPacket is iclass=10 & op2627=3 & op2224=5 & op0007=0 & Rt5HL21 & StMemAIMuC10h & $(END_PACKET) { + tmp:2 = Rt5HL21; + build EndPacket; + <> + StMemAIMuC10h = tmp; +} + +# (v2,10) memh -- "memh ( Rz32 ++I :circ ( Mu2 ) ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 0 1 0 1 0 z z z z z P P u t t t t t 0 + + + + + 1 + +# +# (v2,10) memh -- "memh ( Rz32 ++I :circ ( Mu2 ) ) = Rt32.h" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 0 1 0 1 1 z z z z z P P u t t t t t 0 + + + + + 1 + + +:memh StMemAIICircMuC10h,Rt5HL21 EndPacket is iclass=10 & op2227=0x25 & op0007=2 & Rt5HL21 & StMemAIICircMuC10h & $(END_PACKET) { + tmp:2 = Rt5HL21; + build EndPacket; + <> + StMemAIICircMuC10h = tmp; +} + +# (v4,4) memh -- "memh ( gp + #u16:1x ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 1 i i 0 1 0 1 i i i i i P P i 0 1 t t t i i i i i i i i + +:memh StMemGPRelxC4h,Nreg0810 EndPacket is iclass=4 & op27=1 & op2124=5 & op1112=1 & Nreg0810 & StMemGPRelxC4h & $(END_PACKET) { + build EndPacket; + <> + StMemGPRelxC4h = Nreg0810:2; +} + +# (v2,4) memh -- "memh ( gp + #u16:1x ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 1 i i 0 0 1 0 i i i i i P P i t t t t t i i i i i i i i +# +# (v2,4) memh -- "memh ( gp + #u16:1x ) = Rt32.h" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 1 i i 0 0 1 1 i i i i i P P i t t t t t i i i i i i i i + +:memh StMemGPRelxC4h,Rt5HL21 EndPacket is iclass=4 & op27=1 & op2224=1 & Rt5HL21 & StMemGPRelxC4h & $(END_PACKET) { + tmp:2 = Rt5HL21; + build EndPacket; + <> + StMemGPRelxC4h = tmp; +} + +# (v4,9) memh -- "if ( Pt4 ) Rd32 = memh ( #u6x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 1 1 1 0 1 0 i i i i i P P 1 0 0 t t i 1 + + d d d d d +# +# (v4,9) memh -- "if ( ! Pt4 ) Rd32 = memh ( #u6x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 1 1 1 0 1 0 i i i i i P P 1 0 1 t t i 1 + + d d d d d +# +# (v4,9) memh -- "if ( Pt4 .new ) Rd32 = memh ( #u6x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 1 1 1 0 1 0 i i i i i P P 1 1 0 t t i 1 + + d d d d d +# +# (v4,9) memh -- "if ( ! Pt4 .new ) Rd32 = memh ( #u6x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 1 1 1 0 1 0 i i i i i P P 1 1 1 t t i 1 + + d d d d d + +:memh^PuCond0910_N12_S11 rd5,LdMemAbsU6xC9h EndPacket is iclass=9 & op2127=0x7a & op13=1 & op0507=4 & rd5 & LdMemAbsU6xC9h & PuCond0910_N12_S11 & $(END_PACKET) { + tmp:4 = 0; + build PuCond0910_N12_S11; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + tmp = sext(LdMemAbsU6xC9h); + + <> + if (ConditionReg == 0) goto ; + rd5 = tmp; + +} + +# (v2,4) memh -- "if ( Pt4 ) Rd32 = memh ( Rs32 + #u6:1x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 0 0 0 1 0 1 0 s s s s s P P 0 t t i i i i i i d d d d d +# +# (v2,4) memh -- "if ( ! Pt4 ) Rd32 = memh ( Rs32 + #u6:1x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 0 1 0 1 0 1 0 s s s s s P P 0 t t i i i i i i d d d d d +# +# (v2,4) memh -- "if ( Pt4 .new ) Rd32 = memh ( Rs32 + #u6:1x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 0 0 1 1 0 1 0 s s s s s P P 0 t t i i i i i i d d d d d +# +# (v2,4) memh -- "if ( ! Pt4 .new ) Rd32 = memh ( Rs32 + #u6:1x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 0 1 1 1 0 1 0 s s s s s P P 0 t t i i i i i i d d d d d + +:memh^PuCond1112_N25_S26 rd5,LdMemRsRelxC4h EndPacket is iclass=4 & op27=0 & op2224=5 & op21=0 & op13=0 & rd5 & LdMemRsRelxC4h & PuCond1112_N25_S26 & $(END_PACKET) { + tmp:4 = 0; + build PuCond1112_N25_S26; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + tmp = sext(LdMemRsRelxC4h); + + <> + if (ConditionReg == 0) goto ; + rd5 = tmp; + +} + +# (v2,9) memh -- "if ( Pt4 ) Rd32 = memh ( Rz32 ++ #s4:1 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 1 1 0 1 0 z z z z z P P 1 0 0 t t i i i i d d d d d +# +# (v2,9) memh -- "if ( ! Pt4 ) Rd32 = memh ( Rz32 ++ #s4:1 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 1 1 0 1 0 z z z z z P P 1 0 1 t t i i i i d d d d d +# +# (v4,9) memh -- "if ( Pt4 .new ) Rd32 = memh ( Rz32 ++ #s4:1 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 1 1 0 1 0 z z z z z P P 1 1 0 t t i i i i d d d d d +# +# (v4,9) memh -- "if ( ! Pt4 .new ) Rd32 = memh ( Rz32 ++ #s4:1 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 1 1 0 1 0 z z z z z P P 1 1 1 t t i i i i d d d d d + +:memh^PuCond0910_N12_S11 rd5,LdMemAIS4C9h EndPacket is iclass=9 & op2127=0x5a & op13=1 & rd5 & LdMemAIS4C9h & PuCond0910_N12_S11 & $(END_PACKET) [ cond=1; ] { + tmp:4 = 0; + build PuCond0910_N12_S11; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + tmp = sext(LdMemAIS4C9h); + + <> + if (ConditionReg == 0) goto ; + rd5 = tmp; + +} + +# (v4,3) memh -- "if ( Pv4 ) Rd32 = memh ( Rs32 + Rt32 << #n2 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 0 0 0 0 0 1 0 s s s s s P P n t t t t t n v v d d d d d +# +# (v4,3) memh -- "if ( ! Pv4 ) Rd32 = memh ( Rs32 + Rt32 << #n2 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 0 0 0 1 0 1 0 s s s s s P P n t t t t t n v v d d d d d +# +# (v4,3) memh -- "if ( Pv4 .new ) Rd32 = memh ( Rs32 + Rt32 << #n2 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 0 0 1 0 0 1 0 s s s s s P P n t t t t t n v v d d d d d +# +# (v4,3) memh -- "if ( ! Pv4 .new ) Rd32 = memh ( Rs32 + Rt32 << #n2 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 0 0 1 1 0 1 0 s s s s s P P n t t t t t n v v d d d d d + +:memh^PuCond0506_N25_S24 rd5,MemRsRelShiftC3h EndPacket is iclass=3 & op2627=0 & op2123=2 & rd5 & MemRsRelShiftC3h & PuCond0506_N25_S24 & $(END_PACKET) { + tmp:4 = 0; + build PuCond0506_N25_S24; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + tmp = sext(MemRsRelShiftC3h); + + <> + if (ConditionReg == 0) goto ; + rd5 = tmp; + +} + +# (v4,10) memh -- "if ( Pv4 ) memh ( #u6x ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 1 1 1 1 0 1 + + + i i P P 0 0 1 t t t 1 i i i i 0 v v +# +# (v4,10) memh -- "if ( Pv4 .new ) memh ( #u6x ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 1 1 1 1 0 1 + + + i i P P 1 0 1 t t t 1 i i i i 0 v v +# +# (v4,10) memh -- "if ( ! Pv4 ) memh ( #u6x ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 1 1 1 1 0 1 + + + i i P P 0 0 1 t t t 1 i i i i 1 v v +# +# (v4,10) memh -- "if ( ! Pv4 .new ) memh ( #u6x ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 1 1 1 1 0 1 + + + i i P P 1 0 1 t t t 1 i i i i 1 v v + +:memh^PuCond0001_N13_S02 StMemAbsU6xC10h,Nreg0810 EndPacket is iclass=10 & op2127=0x7d & op1820=0 & op1112=1 & op7=1 & Nreg0810 & StMemAbsU6xC10h & PuCond0001_N13_S02 & $(END_PACKET) { + build PuCond0001_N13_S02; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + StMemAbsU6xC10h = Nreg0810:2; + +} + +# (v4,10) memh -- "if ( Pv4 ) memh ( #u6x ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 1 1 1 0 1 0 - - - i i P P 0 t t t t t 1 i i i i 0 v v +# +# (v4,10) memh -- "if ( ! Pv4 ) memh ( #u6x ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 1 1 1 0 1 0 - - - i i P P 0 t t t t t 1 i i i i 1 v v +# +# (v4,10) memh -- "if ( Pv4 .new ) memh ( #u6x ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 1 1 1 0 1 0 - - - i i P P 1 t t t t t 1 i i i i 0 v v +# +# (v4,10) memh -- "if ( ! Pv4 .new ) memh ( #u6x ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 1 1 1 0 1 0 - - - i i P P 1 t t t t t 1 i i i i 1 v v +# +# (v4,10) memh -- "if ( Pv4 ) memh ( #u6x ) = Rt32.h" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 1 1 1 0 1 1 - - - i i P P 0 t t t t t 1 i i i i 0 v v +# +# (v4,10) memh -- "if ( ! Pv4 ) memh ( #u6x ) = Rt32.h" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 1 1 1 0 1 1 - - - i i P P 0 t t t t t 1 i i i i 1 v v +# +# (v4,10) memh -- "if ( Pv4 .new ) memh ( #u6x ) = Rt32.h" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 1 1 1 0 1 1 - - - i i P P 1 t t t t t 1 i i i i 0 v v +# +# (v4,10) memh -- "if ( ! Pv4 .new ) memh ( #u6x ) = Rt32.h" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 1 1 1 0 1 1 - - - i i P P 1 t t t t t 1 i i i i 1 v v + +:memh^PuCond0001_N13_S02 StMemAbsU6xC10h,Rt5HL21 EndPacket is iclass=10 & op2227=0x3d & op1820=0 & op7=1 & Rt5HL21 & StMemAbsU6xC10h & PuCond0001_N13_S02 & $(END_PACKET) { + tmp:2 = Rt5HL21; + build PuCond0001_N13_S02; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + StMemAbsU6xC10h = tmp; + +} + +# (v4,3) memh -- "if ( Pv4 ) memh ( Rs32 + #u6:1 ) = #S6x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 1 0 0 0 0 0 1 s s s s s P P I i i i i i i v v I I I I I +# +# (v4,3) memh -- "if ( ! Pv4 ) memh ( Rs32 + #u6:1 ) = #S6x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 1 0 0 0 1 0 1 s s s s s P P I i i i i i i v v I I I I I +# +# (v4,3) memh -- "if ( Pv4 .new ) memh ( Rs32 + #u6:1 ) = #S6x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 1 0 0 1 0 0 1 s s s s s P P I i i i i i i v v I I I I I +# +# (v4,3) memh -- "if ( ! Pv4 .new ) memh ( Rs32 + #u6:1 ) = #S6x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 1 0 0 1 1 0 1 s s s s s P P I i i i i i i v v I I I I I + +:memh^PuCond0506_N24_S23 StMemRsRelC3h,Simm16_13_0004x EndPacket is iclass=3 & op2527=4 & op2122=1 & Simm16_13_0004x & StMemRsRelC3h & PuCond0506_N24_S23 & $(END_PACKET) { + build PuCond0506_N24_S23; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + StMemRsRelC3h = Simm16_13_0004x; + +} + +# (v4,4) memh -- "if ( Pv4 ) memh ( Rs32 + #u6:1x ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 0 0 0 0 1 0 1 s s s s s P P i 0 1 t t t i i i i i 0 v v +# +# (v4,4) memh -- "if ( Pv4 .new ) memh ( Rs32 + #u6:1x ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 0 0 1 0 1 0 1 s s s s s P P i 0 1 t t t i i i i i 0 v v +# +# (v4,4) memh -- "if ( ! Pv4 ) memh ( Rs32 + #u6:1x ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 0 1 0 0 1 0 1 s s s s s P P i 0 1 t t t i i i i i 0 v v +# +# (v4,4) memh -- "if ( ! Pv4 .new ) memh ( Rs32 + #u6:1x ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 0 1 1 0 1 0 1 s s s s s P P i 0 1 t t t i i i i i 0 v v + +:memh^PuCond0001_N25_S26 StMemRsRelxC4h,Nreg0810 EndPacket is iclass=4 & op27=0 & op2224=2 & op21=1 & op1112=1 & op2=0 & Nreg0810 & StMemRsRelxC4h & PuCond0001_N25_S26 & $(END_PACKET) { + build PuCond0001_N25_S26; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + StMemRsRelxC4h = Nreg0810:2; + +} + +# (v2,4) memh -- "if ( Pv4 ) memh ( Rs32 + #u6:1x ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 0 0 0 0 0 1 0 s s s s s P P i t t t t t i i i i i 0 v v +# +# (v2,4) memh -- "if ( ! Pv4 ) memh ( Rs32 + #u6:1x ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 0 1 0 0 0 1 0 s s s s s P P i t t t t t i i i i i 0 v v +# +# (v2,4) memh -- "if ( Pv4 ) memh ( Rs32 + #u6:1x ) = Rt32.h" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 0 0 0 0 0 1 1 s s s s s P P i t t t t t i i i i i 0 v v +# +# (v2,4) memh -- "if ( ! Pv4 ) memh ( Rs32 + #u6:1x ) = Rt32.h" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 0 1 0 0 0 1 1 s s s s s P P i t t t t t i i i i i 0 v v +# +# (v4,4) memh -- "if ( Pv4 .new ) memh ( Rs32 + #u6:1x ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 0 0 1 0 0 1 0 s s s s s P P i t t t t t i i i i i 0 v v +# +# (v4,4) memh -- "if ( ! Pv4 .new ) memh ( Rs32 + #u6:1x ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 0 1 1 0 0 1 0 s s s s s P P i t t t t t i i i i i 0 v v +# +# (v4,4) memh -- "if ( Pv4 .new ) memh ( Rs32 + #u6:1x ) = Rt32.h" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 0 0 1 0 0 1 1 s s s s s P P i t t t t t i i i i i 0 v v +# +# (v4,4) memh -- "if ( ! Pv4 .new ) memh ( Rs32 + #u6:1x ) = Rt32.h" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 0 1 1 0 0 1 1 s s s s s P P i t t t t t i i i i i 0 v v + +:memh^PuCond0001_N25_S26 StMemRsRelxC4h,Rt5HL21 EndPacket is iclass=4 & op27=0 & op2224=1 & op2=0 & Rt5HL21 & StMemRsRelxC4h & PuCond0001_N25_S26 & $(END_PACKET) { + tmp:2 = Rt5HL21; + build PuCond0001_N25_S26; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + StMemRsRelxC4h = tmp; + +} + +# (v4,3) memh -- "if ( Pv4 ) memh ( Rs32 + Ru32 << #n2 ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 0 1 0 0 1 0 1 s s s s s P P n u u u u u n v v 0 1 t t t +# +# (v4,3) memh -- "if ( Pv4 .new ) memh ( Rs32 + Ru32 << #n2 ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 0 1 1 0 1 0 1 s s s s s P P n u u u u u n v v 0 1 t t t +# +# (v4,3) memh -- "if ( ! Pv4 ) memh ( Rs32 + Ru32 << #n2 ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 0 1 0 1 1 0 1 s s s s s P P n u u u u u n v v 0 1 t t t +# +# (v4,3) memh -- "if ( ! Pv4 .new ) memh ( Rs32 + Ru32 << #n2 ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 0 1 1 1 1 0 1 s s s s s P P n u u u u u n v v 0 1 t t t + +:memh^PuCond0506_N25_S24 MemRsRelShiftC3h,Nreg0002 EndPacket is iclass=3 & op2627=1 & op2123=5 & op0304=1 & Nreg0002 & MemRsRelShiftC3h & PuCond0506_N25_S24 & $(END_PACKET) { + build PuCond0506_N25_S24; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + MemRsRelShiftC3h = Nreg0002:2; + +} + +# (v4,3) memh -- "if ( Pv4 ) memh ( Rs32 + Ru32 << #n2 ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 0 1 0 0 0 1 0 s s s s s P P n u u u u u n v v t t t t t +# +# (v4,3) memh -- "if ( ! Pv4 ) memh ( Rs32 + Ru32 << #n2 ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 0 1 0 1 0 1 0 s s s s s P P n u u u u u n v v t t t t t +# +# (v4,3) memh -- "if ( Pv4 .new ) memh ( Rs32 + Ru32 << #n2 ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 0 1 1 0 0 1 0 s s s s s P P n u u u u u n v v t t t t t +# +# (v4,3) memh -- "if ( ! Pv4 .new ) memh ( Rs32 + Ru32 << #n2 ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 0 1 1 1 0 1 0 s s s s s P P n u u u u u n v v t t t t t +# +# (v4,3) memh -- "if ( Pv4 ) memh ( Rs32 + Ru32 << #n2 ) = Rt32.h" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 0 1 0 0 0 1 1 s s s s s P P n u u u u u n v v t t t t t +# +# (v4,3) memh -- "if ( ! Pv4 ) memh ( Rs32 + Ru32 << #n2 ) = Rt32.h" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 0 1 0 1 0 1 1 s s s s s P P n u u u u u n v v t t t t t +# +# (v4,3) memh -- "if ( Pv4 .new ) memh ( Rs32 + Ru32 << #n2 ) = Rt32.h" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 0 1 1 0 0 1 1 s s s s s P P n u u u u u n v v t t t t t +# +# (v4,3) memh -- "if ( ! Pv4 .new ) memh ( Rs32 + Ru32 << #n2 ) = Rt32.h" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 0 1 1 1 0 1 1 s s s s s P P n u u u u u n v v t t t t t + +:memh^PuCond0506_N25_S24 MemRsRelShiftC3h,Ru5HL21 EndPacket is iclass=3 & op2627=1 & op2223=1 & Ru5HL21 & MemRsRelShiftC3h & PuCond0506_N25_S24 & $(END_PACKET) { + tmp:2 = Ru5HL21; + build PuCond0506_N25_S24; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + MemRsRelShiftC3h = tmp; + +} + +# (v4,10) memh -- "if ( Pv4 ) memh ( Rz32 ++ #s4:1 ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 1 1 1 0 1 z z z z z P P 1 0 1 t t t 0 i i i i 0 v v +# +# (v4,10) memh -- "if ( Pv4 .new ) memh ( Rz32 ++ #s4:1 ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 1 1 1 0 1 z z z z z P P 1 0 1 t t t 1 i i i i 0 v v +# +# (v4,10) memh -- "if ( ! Pv4 ) memh ( Rz32 ++ #s4:1 ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 1 1 1 0 1 z z z z z P P 1 0 1 t t t 0 i i i i 1 v v +# +# (v4,10) memh -- "if ( ! Pv4 .new ) memh ( Rz32 ++ #s4:1 ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 1 1 1 0 1 z z z z z P P 1 0 1 t t t 1 i i i i 1 v v + +:memh^PuCond0001_N07_S02 StMemAIS4C10h,Nreg0810 EndPacket is iclass=10 & op2127=0x5d & op1113=5 & Nreg0810 & StMemAIS4C10h & PuCond0001_N07_S02 & $(END_PACKET) [ cond=1; ] { + build PuCond0001_N07_S02; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + StMemAIS4C10h = Nreg0810:2; + +} + +# (v4,10) memh -- "if ( Pv4 .new ) memh ( Rz32 ++ #s4:1 ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 1 1 0 1 0 z z z z z P P 1 t t t t t 1 i i i i 0 v v +# +# (v4,10) memh -- "if ( ! Pv4 .new ) memh ( Rz32 ++ #s4:1 ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 1 1 0 1 0 z z z z z P P 1 t t t t t 1 i i i i 1 v v +# +# (v4,10) memh -- "if ( Pv4 .new ) memh ( Rz32 ++ #s4:1 ) = Rt32.h" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 1 1 0 1 1 z z z z z P P 1 t t t t t 1 i i i i 0 v v +# +# (v4,10) memh -- "if ( ! Pv4 .new ) memh ( Rz32 ++ #s4:1 ) = Rt32.h" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 1 1 0 1 1 z z z z z P P 1 t t t t t 1 i i i i 1 v v +# +# (v2,10) memh -- "if ( Pv4 ) memh ( Rz32 ++ #s4:1 ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 1 1 0 1 0 z z z z z P P 1 t t t t t 0 i i i i 0 v v +# +# (v2,10) memh -- "if ( ! Pv4 ) memh ( Rz32 ++ #s4:1 ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 1 1 0 1 0 z z z z z P P 1 t t t t t 0 i i i i 1 v v +# +# (v2,10) memh -- "if ( Pv4 ) memh ( Rz32 ++ #s4:1 ) = Rt32.h" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 1 1 0 1 1 z z z z z P P 1 t t t t t 0 i i i i 0 v v +# +# (v2,10) memh -- "if ( ! Pv4 ) memh ( Rz32 ++ #s4:1 ) = Rt32.h" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 1 1 0 1 1 z z z z z P P 1 t t t t t 0 i i i i 1 v v +# + +:memh^PuCond0001_N07_S02 StMemAIS4C10h,Rt5HL21 EndPacket is iclass=10 & op2227=0x2d & op13=1 & Rt5HL21 & StMemAIS4C10h & PuCond0001_N07_S02 & $(END_PACKET) [ cond=1; ] { + tmp:2 = Rt5HL21; + build PuCond0001_N07_S02; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + StMemAIS4C10h = tmp; + +} + +# (v4,9) memh_fifo -- "Ryy32 = memh_fifo ( Rf32 = #U6x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 1 0 0 1 0 f f f f f P P 0 1 I I I I + I I y y y y y + +:memh_fifo Rdd5,LdMemRsAssignxC9h EndPacket is iclass=9 & op2127=0x52 & op1213=1 & op7=0 & LdMemRsAssignxC9h & Rdd5 & $(END_PACKET) { + local tmp_hword = LdMemRsAssignxC9h; + Rdd5 = (Rdd5 >> 16) | (zext(tmp_hword) << 48); + build EndPacket; +} + +# (v4,9) memh_fifo -- "Ryy32 = memh_fifo ( Rs32 + #s11:1x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 0 i i 0 0 1 0 s s s s s P P i i i i i i i i i y y y y y + +:memh_fifo Rdd5,LdMemRsRelxC9h EndPacket is iclass=9 & op27=0 & op2124=2 & LdMemRsRelxC9h & Rdd5 & $(END_PACKET) { + local tmp_hword = LdMemRsRelxC9h; + Rdd5 = (Rdd5 >> 16) | (zext(tmp_hword) << 48); + build EndPacket; +} + +# (v4,9) memh_fifo -- "Ryy32 = memh_fifo ( Rt32 << #n2 + #U6x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 1 0 0 0 1 0 t t t t t P P n 1 I I I I n I I y y y y y + +:memh_fifo Rdd5,LdMemRsRelShiftxC9h EndPacket is iclass=9 & op2127=0x62 & op12=1 & LdMemRsRelShiftxC9h & Rdd5 & $(END_PACKET) { + local tmp_hword = LdMemRsRelShiftxC9h; + Rdd5 = (Rdd5 >> 16) | (zext(tmp_hword) << 48); + build EndPacket; +} + +# (v4,9) memh_fifo -- "Ryy32 = memh_fifo ( Rz32 ++ #s4:1 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 1 0 0 1 0 z z z z z P P 0 0 + + + i i i i y y y y y + +:memh_fifo Rdd5,LdMemAIS4C9h EndPacket is iclass=9 & op2127=0x52 & op0913=0 & LdMemAIS4C9h & Rdd5 & $(END_PACKET) { + local tmp_hword = LdMemAIS4C9h; + Rdd5 = (Rdd5 >> 16) | (zext(tmp_hword) << 48); + build EndPacket; +} + +# (v4,9) memh_fifo -- "Ryy32 = memh_fifo ( Rz32 ++ #s4:1 :circ ( Mu2 ) )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 0 0 0 1 0 z z z z z P P u 0 + + 0 i i i i y y y y y + +:memh_fifo Rdd5,LdMemAIS4CircMuC9h EndPacket is iclass=9 & op2127=0x42 & op0912=0 & LdMemAIS4CircMuC9h & Rdd5 & $(END_PACKET) { + local tmp_hword = LdMemAIS4CircMuC9h; + Rdd5 = (Rdd5 >> 16) | (zext(tmp_hword) << 48); + build EndPacket; +} + +# (v4,9) memh_fifo -- "Ryy32 = memh_fifo ( Rz32 ++ Mu2 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 1 0 0 0 1 0 z z z z z P P u 0 + + + + 0 + + y y y y y +# +# (v4,9) memh_fifo -- "Ryy32 = memh_fifo ( Rz32 ++ Mu2 :brev )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 1 1 0 0 1 0 z z z z z P P u 0 + + + + 0 + + y y y y y + +:memh_fifo Rdd5,LdMemAIMuC9h EndPacket is iclass=9 & op2627=3 & op2124=2 & op0512=0 & LdMemAIMuC9h & Rdd5 & $(END_PACKET) { + local tmp_hword = LdMemAIMuC9h; + Rdd5 = (Rdd5 >> 16) | (zext(tmp_hword) << 48); + build EndPacket; +} + +# (v4,9) memh_fifo -- "Ryy32 = memh_fifo ( Rz32 ++I :circ ( Mu2 ) )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 0 0 0 1 0 z z z z z P P u 0 + + 1 + 0 + + y y y y y + +:memh_fifo Rdd5,LdMemAIICircMuC9h EndPacket is iclass=9 & op2127=0x42 & op0512=0x10 & LdMemAIICircMuC9h & Rdd5 & $(END_PACKET) { + local tmp_hword = LdMemAIICircMuC9h; + Rdd5 = (Rdd5 >> 16) | (zext(tmp_hword) << 48); + build EndPacket; +} + +# (v4,9) memub -- "Rd32 = memub ( Rf32 = #U6x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 1 1 0 0 1 f f f f f P P 0 1 I I I I + I I d d d d d + +:memub Rd5,LdMemRsAssignxC9b EndPacket is iclass=9 & op2127=0x59 & op1213=1 & op7=0 & Rd5 & LdMemRsAssignxC9b & $(END_PACKET) { + Rd5 = zext(LdMemRsAssignxC9b); + build EndPacket; +} + +# (v2,9) memub -- "Rd32 = memub ( Rs32 + #s11:0x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 0 i i 1 0 0 1 s s s s s P P i i i i i i i i i d d d d d + +:memub Rd5,LdMemRsRelxC9b0 EndPacket is iclass=9 & op27=0 & op2224=4 & op21=1 & Rd5 & LdMemRsRelxC9b0 & $(END_PACKET) { + Rd5 = zext(LdMemRsRelxC9b0); + build EndPacket; +} + +# (v4,3) memub -- "Rd32 = memub ( Rs32 + Rt32 << #n2 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 1 0 1 0 0 0 1 s s s s s P P n t t t t t n + + d d d d d + +:memub Rd5,MemRsRelShiftC3b EndPacket is iclass=3 & op2127=0x51 & op0506=0 & Rd5 & MemRsRelShiftC3b & $(END_PACKET) { + Rd5 = zext(MemRsRelShiftC3b); + build EndPacket; +} + +# (v4,9) memub -- "Rd32 = memub ( Rt32 << #n2 + #U6x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 1 0 1 0 0 1 t t t t t P P n 1 I I I I n I I d d d d d + +:memub Rd5,LdMemRsRelShiftxC9b EndPacket is iclass=9 & op2127=0x69 & op12=1 & Rd5 & LdMemRsRelShiftxC9b & $(END_PACKET) { + Rd5 = zext(LdMemRsRelShiftxC9b); + build EndPacket; +} + +# (v2,9) memub -- "Rd32 = memub ( Rz32 ++ #s4:0 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 1 1 0 0 1 z z z z z P P 0 0 + + + i i i i d d d d d + +:memub Rd5,LdMemAIS4C9b0 EndPacket is iclass=9 & op2127=0x59 & op0913=0 & Rd5 & LdMemAIS4C9b0 & $(END_PACKET) { + Rd5 = zext(LdMemAIS4C9b0); + build EndPacket; +} + +# (v2,9) memub -- "Rd32 = memub ( Rz32 ++ #s4:0 :circ ( Mu2 ) )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 0 1 0 0 1 z z z z z P P u 0 + + 0 i i i i d d d d d + +:memub Rd5,LdMemAIS4CircMuC9b0 EndPacket is iclass=9 & op2127=0x49 & op0912=0 & Rd5 & LdMemAIS4CircMuC9b0 & $(END_PACKET) { + Rd5 = zext(LdMemAIS4CircMuC9b0); + build EndPacket; +} + +# (v2,9) memub -- "Rd32 = memub ( Rz32 ++ Mu2 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 1 0 1 0 0 1 z z z z z P P u 0 + + + + 0 + + d d d d d +# +# (v2,9) memub -- "Rd32 = memub ( Rz32 ++ Mu2 :brev )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 1 1 1 0 0 1 z z z z z P P u 0 + + + + 0 + + d d d d d + +:memub Rd5,LdMemAIMuC9b EndPacket is iclass=9 & op2627=3 & op2124=9 & op0512=0 & Rd5 & LdMemAIMuC9b & $(END_PACKET) { + Rd5 = zext(LdMemAIMuC9b); + build EndPacket; +} + +# (v2,9) memub -- "Rd32 = memub ( Rz32 ++I :circ ( Mu2 ) )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 0 1 0 0 1 z z z z z P P u 0 + + 1 + 0 + + d d d d d + +:memub Rd5,LdMemAIICircMuC9b EndPacket is iclass=9 & op2127=0x49 & op0512=0x10 & Rd5 & LdMemAIICircMuC9b & $(END_PACKET) { + Rd5 = zext(LdMemAIICircMuC9b); + build EndPacket; +} + +# (v2,4) memub -- "Rd32 = memub ( gp + #u16:0x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 1 i i 1 0 0 1 i i i i i P P i i i i i i i i i d d d d d + +:memub Rd5,LdMemGPRelxC4b EndPacket is iclass=4 & op27=1 & op2224=4 & op21=1 & Rd5 & LdMemGPRelxC4b & $(END_PACKET) { + Rd5 = zext(LdMemGPRelxC4b); + build EndPacket; +} + +# (v4,9) memub -- "if ( Pt4 ) Rd32 = memub ( #u6x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 1 1 1 0 0 1 i i i i i P P 1 0 0 t t i 1 + + d d d d d +# +# (v4,9) memub -- "if ( ! Pt4 ) Rd32 = memub ( #u6x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 1 1 1 0 0 1 i i i i i P P 1 0 1 t t i 1 + + d d d d d +# +# (v4,9) memub -- "if ( Pt4 .new ) Rd32 = memub ( #u6x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 1 1 1 0 0 1 i i i i i P P 1 1 0 t t i 1 + + d d d d d +# +# (v4,9) memub -- "if ( ! Pt4 .new ) Rd32 = memub ( #u6x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 1 1 1 0 0 1 i i i i i P P 1 1 1 t t i 1 + + d d d d d + +:memub^PuCond0910_N12_S11 rd5,LdMemAbsU6xC9b EndPacket is iclass=9 & op2127=0x79 & op13=1 & op0507=4 & rd5 & LdMemAbsU6xC9b & PuCond0910_N12_S11 & $(END_PACKET) { + tmp:4 = 0; + build PuCond0910_N12_S11; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + tmp = zext(LdMemAbsU6xC9b); + + <> + if (ConditionReg == 0) goto ; + rd5 = tmp; + +} + +# (v2,4) memub -- "if ( Pt4 ) Rd32 = memub ( Rs32 + #u6:0x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 0 0 0 1 0 0 1 s s s s s P P 0 t t i i i i i i d d d d d +# +# (v2,4) memub -- "if ( ! Pt4 ) Rd32 = memub ( Rs32 + #u6:0x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 0 1 0 1 0 0 1 s s s s s P P 0 t t i i i i i i d d d d d +# +# (v2,4) memub -- "if ( Pt4 .new ) Rd32 = memub ( Rs32 + #u6:0x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 0 0 1 1 0 0 1 s s s s s P P 0 t t i i i i i i d d d d d +# +# (v2,4) memub -- "if ( ! Pt4 .new ) Rd32 = memub ( Rs32 + #u6:0x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 0 1 1 1 0 0 1 s s s s s P P 0 t t i i i i i i d d d d d + +:memub^PuCond1112_N25_S26 rd5,LdMemRsRelxC4b EndPacket is iclass=4 & op27=0 & op2224=4 & op21=1 & op13=0 & rd5 & LdMemRsRelxC4b & PuCond1112_N25_S26 & $(END_PACKET) { + tmp:4 = 0; + build PuCond1112_N25_S26; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + tmp = zext(LdMemRsRelxC4b); + + <> + if (ConditionReg == 0) goto ; + rd5 = tmp; + +} + +# (v2,9) memub -- "if ( Pt4 ) Rd32 = memub ( Rz32 ++ #s4:0 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 1 1 0 0 1 z z z z z P P 1 0 0 t t i i i i d d d d d +# +# (v2,9) memub -- "if ( ! Pt4 ) Rd32 = memub ( Rz32 ++ #s4:0 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 1 1 0 0 1 z z z z z P P 1 0 1 t t i i i i d d d d d +# +# (v4,9) memub -- "if ( Pt4 .new ) Rd32 = memub ( Rz32 ++ #s4:0 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 1 1 0 0 1 z z z z z P P 1 1 0 t t i i i i d d d d d +# +# (v4,9) memub -- "if ( ! Pt4 .new ) Rd32 = memub ( Rz32 ++ #s4:0 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 1 1 0 0 1 z z z z z P P 1 1 1 t t i i i i d d d d d + +:memub^PuCond0910_N12_S11 rd5,LdMemAIS4C9b0 EndPacket is iclass=9 & op2127=0x59 & op13=1 & rd5 & LdMemAIS4C9b0 & PuCond0910_N12_S11 & $(END_PACKET) [ cond=1; ] { + tmp:4 = 0; + build PuCond0910_N12_S11; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + tmp = zext(LdMemAIS4C9b0); + + <> + if (ConditionReg == 0) goto ; + rd5 = tmp; + +} + +# (v4,3) memub -- "if ( Pv4 ) Rd32 = memub ( Rs32 + Rt32 << #n2 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 0 0 0 0 0 0 1 s s s s s P P n t t t t t n v v d d d d d +# +# (v4,3) memub -- "if ( ! Pv4 ) Rd32 = memub ( Rs32 + Rt32 << #n2 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 0 0 0 1 0 0 1 s s s s s P P n t t t t t n v v d d d d d +# +# (v4,3) memub -- "if ( Pv4 .new ) Rd32 = memub ( Rs32 + Rt32 << #n2 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 0 0 1 0 0 0 1 s s s s s P P n t t t t t n v v d d d d d +# +# (v4,3) memub -- "if ( ! Pv4 .new ) Rd32 = memub ( Rs32 + Rt32 << #n2 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 0 0 1 1 0 0 1 s s s s s P P n t t t t t n v v d d d d d + +:memub^PuCond0506_N25_S24 rd5,MemRsRelShiftC3b EndPacket is iclass=3 & op2627=0 & op2123=1 & rd5 & MemRsRelShiftC3b & PuCond0506_N25_S24 & $(END_PACKET) { + tmp:4 = 0; + build PuCond0506_N25_S24; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + tmp = zext(MemRsRelShiftC3b); + + <> + if (ConditionReg == 0) goto ; + rd5 = tmp; + +} + +# (v4,9) memubh -- "Rd32 = memubh ( Rf32 = #U6x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 1 0 0 1 1 f f f f f P P 0 1 I I I I + I I d d d d d + +macro unpack16to32(src2, dest4) { + hi:2 = src2 & 0xff00; + lo:2 = src2 & 0x00ff; + dest4 = (zext(hi) << 8) + zext(lo); +} + +:memubh Rd5,LdMemRsAssignxC9h EndPacket is iclass=9 & op2127=0x53 & op1213=1 & op7=0 & Rd5 & LdMemRsAssignxC9h & $(END_PACKET) { + unpack16to32(LdMemRsAssignxC9h, Rd5); + build EndPacket; +} + +# (v2,9) memubh -- "Rd32 = memubh ( Rs32 + #s11:1x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 0 i i 0 0 1 1 s s s s s P P i i i i i i i i i d d d d d + +:memubh Rd5,LdMemRsRelxC9h EndPacket is iclass=9 & op27=0 & op2224=1 & op21=1 & Rd5 & LdMemRsRelxC9h & $(END_PACKET) { + unpack16to32(LdMemRsRelxC9h, Rd5); + build EndPacket; +} + +# (v4,9) memubh -- "Rd32 = memubh ( Rt32 << #n2 + #U6x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 1 0 0 0 1 1 t t t t t P P n 1 I I I I n I I d d d d d + +:memubh Rd5,LdMemRsRelShiftxC9h EndPacket is iclass=9 & op2127=0x63 & op12=1 & Rd5 & LdMemRsRelShiftxC9h & $(END_PACKET) { + unpack16to32(LdMemRsRelShiftxC9h, Rd5); + build EndPacket; +} + +# (v2,9) memubh -- "Rd32 = memubh ( Rz32 ++ #s4:1 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 1 0 0 1 1 z z z z z P P 0 0 + + + i i i i d d d d d + +:memubh Rd5,LdMemAIS4C9h EndPacket is iclass=9 & op2127=0x53 & op0913=0 & Rd5 & LdMemAIS4C9h & $(END_PACKET) { + unpack16to32(LdMemAIS4C9h, Rd5); + build EndPacket; +} + +# (v2,9) memubh -- "Rd32 = memubh ( Rz32 ++ #s4:1 :circ ( Mu2 ) )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 0 0 0 1 1 z z z z z P P u 0 + + 0 i i i i d d d d d + +:memubh Rd5,LdMemAIS4CircMuC9h EndPacket is iclass=9 & op2127=0x43 & op0912=0 & Rd5 & LdMemAIS4CircMuC9h & $(END_PACKET) { + unpack16to32(LdMemAIS4CircMuC9h, Rd5); + build EndPacket; +} + +# (v2,9) memubh -- "Rd32 = memubh ( Rz32 ++ Mu2 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 1 0 0 0 1 1 z z z z z P P u 0 + + + + 0 + + d d d d d +# +# (v2,9) memubh -- "Rd32 = memubh ( Rz32 ++ Mu2 :brev )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 1 1 0 0 1 1 z z z z z P P u 0 + + + + 0 + + d d d d d + +:memubh Rd5,LdMemAIMuC9h EndPacket is iclass=9 & op2627=3 & op2124=0x3 & op0512=0 & Rd5 & LdMemAIMuC9h & $(END_PACKET) { + unpack16to32(LdMemAIMuC9h, Rd5); + build EndPacket; +} + +# (v2,9) memubh -- "Rd32 = memubh ( Rz32 ++I :circ ( Mu2 ) )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 0 0 0 1 1 z z z z z P P u 0 + + 1 + 0 + + d d d d d + +:memubh Rd5,LdMemAIICircMuC9h EndPacket is iclass=9 & op2127=0x43 & op0512=0x10 & Rd5 & LdMemAIICircMuC9h & $(END_PACKET) { + unpack16to32(LdMemAIICircMuC9h, Rd5); + build EndPacket; +} + +# (v4,9) memubh -- "Rdd32 = memubh ( Rf32 = #U6x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 1 0 1 0 1 f f f f f P P 0 1 I I I I + I I d d d d d + +macro unpack32to64(src4, dest8) { + hi0:4 = src4 & 0x0000ff00; + lo0:4 = src4 & 0x000000ff; + hi1:4 = src4 & 0xff000000; + lo1:4 = src4 & 0x00ff0000; + dest8 = (zext(hi1) << 32) + (zext(lo1) << 16) + (zext(hi0) << 8) + zext(lo0); +} + +:memubh Rdd5,LdMemRsAssignxC9w EndPacket is iclass=9 & op2127=0x55 & op1213=1 & op7=0 & Rdd5 & LdMemRsAssignxC9w & $(END_PACKET) { + unpack32to64(LdMemRsAssignxC9w, Rdd5); + build EndPacket; +} + +# (v2,9) memubh -- "Rdd32 = memubh ( Rs32 + #s11:2x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 0 i i 0 1 0 1 s s s s s P P i i i i i i i i i d d d d d + +:memubh Rdd5,LdMemRsRelxC9w EndPacket is iclass=9 & op27=0 & op2224=2 & op21=1 & Rdd5 & LdMemRsRelxC9w & $(END_PACKET) { + unpack32to64(LdMemRsRelxC9w, Rdd5); + build EndPacket; +} + +# (v4,9) memubh -- "Rdd32 = memubh ( Rt32 << #n2 + #U6x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 1 0 0 1 0 1 t t t t t P P n 1 I I I I n I I d d d d d + +:memubh Rdd5,LdMemRsRelShiftxC9w EndPacket is iclass=9 & op2127=0x65 & op12=1 & Rdd5 & LdMemRsRelShiftxC9w & $(END_PACKET) { + unpack32to64(LdMemRsRelShiftxC9w, Rdd5); + build EndPacket; +} + +# (v2,9) memubh -- "Rdd32 = memubh ( Rz32 ++ #s4:2 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 1 0 1 0 1 z z z z z P P 0 0 + + + i i i i d d d d d + +:memubh Rdd5,LdMemAIS4C9w EndPacket is iclass=9 & op2127=0x55 & op0913=0 & Rdd5 & LdMemAIS4C9w & $(END_PACKET) { + unpack32to64(LdMemAIS4C9w, Rdd5); + build EndPacket; +} + +# (v2,9) memubh -- "Rdd32 = memubh ( Rz32 ++ #s4:2 :circ ( Mu2 ) )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 0 0 1 0 1 z z z z z P P u 0 + + 0 i i i i d d d d d + +:memubh Rdd5,LdMemAIS4CircMuC9w EndPacket is iclass=9 & op2127=0x45 & op0912=0 & Rdd5 & LdMemAIS4CircMuC9w & $(END_PACKET) { + unpack32to64(LdMemAIS4CircMuC9w, Rdd5); + build EndPacket; +} + +# (v2,9) memubh -- "Rdd32 = memubh ( Rz32 ++ Mu2 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 1 0 0 1 0 1 z z z z z P P u 0 + + + + 0 + + d d d d d +# +# (v2,9) memubh -- "Rdd32 = memubh ( Rz32 ++ Mu2 :brev )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 1 1 0 1 0 1 z z z z z P P u 0 + + + + 0 + + d d d d d + +:memubh Rdd5,LdMemAIMuC9w EndPacket is iclass=9 & op2627=3 & op2124=0x5 & op0512=0 & Rdd5 & LdMemAIMuC9w & $(END_PACKET) { + unpack32to64(LdMemAIMuC9w, Rdd5); + build EndPacket; +} + +# (v2,9) memubh -- "Rdd32 = memubh ( Rz32 ++I :circ ( Mu2 ) )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 0 0 1 0 1 z z z z z P P u 0 + + 1 + 0 + + d d d d d + +:memubh Rdd5,LdMemAIICircMuC9w EndPacket is iclass=9 & op2127=0x45 & op0512=0x10 & Rdd5 & LdMemAIICircMuC9w & $(END_PACKET) { + unpack32to64(LdMemAIICircMuC9w, Rdd5); + build EndPacket; +} + +# (v4,9) memuh -- "Rd32 = memuh ( Rf32 = #U6x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 1 1 0 1 1 f f f f f P P 0 1 I I I I + I I d d d d d + +:memuh Rd5,LdMemRsAssignxC9h EndPacket is iclass=9 & op2127=0x5b & op1213=1 & op7=0 & Rd5 & LdMemRsAssignxC9h & $(END_PACKET) { + Rd5 = zext(LdMemRsAssignxC9h); + build EndPacket; +} + +# (v2,9) memuh -- "Rd32 = memuh ( Rs32 + #s11:1x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 0 i i 1 0 1 1 s s s s s P P i i i i i i i i i d d d d d + +:memuh Rd5,LdMemRsRelxC9h EndPacket is iclass=9 & op27=0 & op2224=5 & op21=1 & Rd5 & LdMemRsRelxC9h & $(END_PACKET) { + Rd5 = zext(LdMemRsRelxC9h); + build EndPacket; +} + +# (v4,3) memuh -- "Rd32 = memuh ( Rs32 + Rt32 << #n2 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 1 0 1 0 0 1 1 s s s s s P P n t t t t t n + + d d d d d + +:memuh Rd5,MemRsRelShiftC3h EndPacket is iclass=3 & op2127=0x53 & op0506=0 & Rd5 & MemRsRelShiftC3h & $(END_PACKET) { + Rd5 = zext(MemRsRelShiftC3h); + build EndPacket; +} + +# (v4,9) memuh -- "Rd32 = memuh ( Rt32 << #n2 + #U6x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 1 0 1 0 1 1 t t t t t P P n 1 I I I I n I I d d d d d + +:memuh Rd5,LdMemRsRelShiftxC9h EndPacket is iclass=9 & op2127=0x6b & op12=1 & Rd5 & LdMemRsRelShiftxC9h & $(END_PACKET) { + Rd5 = zext(LdMemRsRelShiftxC9h); + build EndPacket; +} + +# (v2,9) memuh -- "Rd32 = memuh ( Rz32 ++ #s4:1 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 1 1 0 1 1 z z z z z P P 0 0 + + + i i i i d d d d d + +:memuh Rd5,LdMemAIS4C9h EndPacket is iclass=9 & op2127=0x5b & op0913=0 & Rd5 & LdMemAIS4C9h & $(END_PACKET) { + Rd5 = zext(LdMemAIS4C9h); + build EndPacket; +} + +# (v2,9) memuh -- "Rd32 = memuh ( Rz32 ++ #s4:1 :circ ( Mu2 ) )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 0 1 0 1 1 z z z z z P P u 0 + + 0 i i i i d d d d d + +:memuh Rd5,LdMemAIS4CircMuC9h EndPacket is iclass=9 & op2127=0x4b & op0912=0 & Rd5 & LdMemAIS4CircMuC9h & $(END_PACKET) { + Rd5 = zext(LdMemAIS4CircMuC9h); + build EndPacket; +} + +# (v2,9) memuh -- "Rd32 = memuh ( Rz32 ++ Mu2 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 1 0 1 0 1 1 z z z z z P P u 0 + + + + 0 + + d d d d d +# +# (v2,9) memuh -- "Rd32 = memuh ( Rz32 ++ Mu2 :brev )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 1 1 1 0 1 1 z z z z z P P u 0 + + + + 0 + + d d d d d + +:memuh Rd5,LdMemAIMuC9h EndPacket is iclass=9 & op2627=3 & op2124=0xb & op0512=0 & Rd5 & LdMemAIMuC9h & $(END_PACKET) { + Rd5 = zext(LdMemAIMuC9h); + build EndPacket; +} + +# (v2,9) memuh -- "Rd32 = memuh ( Rz32 ++I :circ ( Mu2 ) )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 0 1 0 1 1 z z z z z P P u 0 + + 1 + 0 + + d d d d d + +:memuh Rd5,LdMemAIICircMuC9h EndPacket is iclass=9 & op2127=0x4b & op0512=0x10 & Rd5 & LdMemAIICircMuC9h & $(END_PACKET) { + Rd5 = zext(LdMemAIICircMuC9h); + build EndPacket; +} + +# (v2,4) memuh -- "Rd32 = memuh ( gp + #u16:1x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 1 i i 1 0 1 1 i i i i i P P i i i i i i i i i d d d d d + +:memuh Rd5,LdMemGPRelxC4h EndPacket is iclass=4 & op27=1 & op2224=5 & op21=1 & Rd5 & LdMemGPRelxC4h & $(END_PACKET) { + Rd5 = zext(LdMemGPRelxC4h); + build EndPacket; +} + +# (v4,9) memuh -- "if ( Pt4 ) Rd32 = memuh ( #u6x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 1 1 1 0 1 1 i i i i i P P 1 0 0 t t i 1 + + d d d d d +# +# (v4,9) memuh -- "if ( ! Pt4 ) Rd32 = memuh ( #u6x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 1 1 1 0 1 1 i i i i i P P 1 0 1 t t i 1 + + d d d d d +# +# (v4,9) memuh -- "if ( Pt4 .new ) Rd32 = memuh ( #u6x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 1 1 1 0 1 1 i i i i i P P 1 1 0 t t i 1 + + d d d d d +# +# (v4,9) memuh -- "if ( ! Pt4 .new ) Rd32 = memuh ( #u6x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 1 1 1 0 1 1 i i i i i P P 1 1 1 t t i 1 + + d d d d d + +:memuh^PuCond0910_N12_S11 rd5,LdMemU6xC9h EndPacket is iclass=9 & op2127=0x7b & op13=1 & op0507=4 & rd5 & LdMemU6xC9h & PuCond0910_N12_S11 & $(END_PACKET) { + tmp:4 = 0; + build PuCond0910_N12_S11; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + tmp = zext(LdMemU6xC9h); + + <> + if (ConditionReg == 0) goto ; + rd5 = tmp; + +} + +# (v2,4) memuh -- "if ( Pt4 ) Rd32 = memuh ( Rs32 + #u6:1x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 0 0 0 1 0 1 1 s s s s s P P 0 t t i i i i i i d d d d d +# +# (v2,4) memuh -- "if ( ! Pt4 ) Rd32 = memuh ( Rs32 + #u6:1x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 0 1 0 1 0 1 1 s s s s s P P 0 t t i i i i i i d d d d d +# +# (v2,4) memuh -- "if ( Pt4 .new ) Rd32 = memuh ( Rs32 + #u6:1x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 0 0 1 1 0 1 1 s s s s s P P 0 t t i i i i i i d d d d d +# +# (v2,4) memuh -- "if ( ! Pt4 .new ) Rd32 = memuh ( Rs32 + #u6:1x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 0 1 1 1 0 1 1 s s s s s P P 0 t t i i i i i i d d d d d + +:memuh^PuCond1112_N25_S26 rd5,LdMemRsRelxC4h EndPacket is iclass=4 & op27=0 & op2224=5 & op21=1 & op13=0 & rd5 & LdMemRsRelxC4h & PuCond1112_N25_S26 & $(END_PACKET) { + tmp:4 = 0; + build PuCond1112_N25_S26; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + tmp = zext(LdMemRsRelxC4h); + + <> + if (ConditionReg == 0) goto ; + rd5 = tmp; + +} + +# (v2,9) memuh -- "if ( Pt4 ) Rd32 = memuh ( Rz32 ++ #s4:1 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 1 1 0 1 1 z z z z z P P 1 0 0 t t i i i i d d d d d +# +# (v2,9) memuh -- "if ( ! Pt4 ) Rd32 = memuh ( Rz32 ++ #s4:1 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 1 1 0 1 1 z z z z z P P 1 0 1 t t i i i i d d d d d +# +# (v4,9) memuh -- "if ( Pt4 .new ) Rd32 = memuh ( Rz32 ++ #s4:1 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 1 1 0 1 1 z z z z z P P 1 1 0 t t i i i i d d d d d +# +# (v4,9) memuh -- "if ( ! Pt4 .new ) Rd32 = memuh ( Rz32 ++ #s4:1 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 1 1 0 1 1 z z z z z P P 1 1 1 t t i i i i d d d d d + +:memuh^PuCond0910_N12_S11 rd5,LdMemAIS4C9h EndPacket is iclass=9 & op2127=0x5b & op13=1 & rd5 & LdMemAIS4C9h & PuCond0910_N12_S11 & $(END_PACKET) [ cond=1; ] { + tmp:4 = 0; + build PuCond0910_N12_S11; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + tmp = zext(LdMemAIS4C9h); + + <> + if (ConditionReg == 0) goto ; + rd5 = tmp; + +} + +# (v4,3) memuh -- "if ( Pv4 ) Rd32 = memuh ( Rs32 + Rt32 << #n2 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 0 0 0 0 0 1 1 s s s s s P P n t t t t t n v v d d d d d +# +# (v4,3) memuh -- "if ( ! Pv4 ) Rd32 = memuh ( Rs32 + Rt32 << #n2 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 0 0 0 1 0 1 1 s s s s s P P n t t t t t n v v d d d d d +# +# (v4,3) memuh -- "if ( Pv4 .new ) Rd32 = memuh ( Rs32 + Rt32 << #n2 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 0 0 1 0 0 1 1 s s s s s P P n t t t t t n v v d d d d d +# +# (v4,3) memuh -- "if ( ! Pv4 .new ) Rd32 = memuh ( Rs32 + Rt32 << #n2 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 0 0 1 1 0 1 1 s s s s s P P n t t t t t n v v d d d d d + +:memuh^PuCond0506_N25_S24 rd5,MemRsRelShiftC3h EndPacket is iclass=3 & op2627=0 & op2123=3 & rd5 & MemRsRelShiftC3h & PuCond0506_N25_S24 & $(END_PACKET) { + tmp:4 = 0; + build PuCond0506_N25_S24; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + tmp = zext(MemRsRelShiftC3h); + + <> + if (ConditionReg == 0) goto ; + rd5 = tmp; + +} + +# (v4,9) memw -- "Rd32 = memw ( Rf32 = #U6x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 1 1 1 0 0 f f f f f P P 0 1 I I I I + I I d d d d d + +:memw Rd5,LdMemRsAssignxC9w EndPacket is iclass=9 & op2127=0x5c & op1213=1 & op7=0 & Rd5 & LdMemRsAssignxC9w & $(END_PACKET) { + Rd5 = LdMemRsAssignxC9w; + build EndPacket; +} + +# (v2,9) memw -- "Rd32 = memw ( Rs32 + #s11:2x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 0 i i 1 1 0 0 s s s s s P P i i i i i i i i i d d d d d + +:memw Rd5,LdMemRsRelxC9w EndPacket is iclass=9 & op27=0 & op2224=6 & op21=0 & Rd5 & LdMemRsRelxC9w & $(END_PACKET) { + Rd5 = LdMemRsRelxC9w; + build EndPacket; +} + +# (v4,3) memw -- "Rd32 = memw ( Rs32 + Rt32 << #n2 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 1 0 1 0 1 0 0 s s s s s P P n t t t t t n + + d d d d d + +:memw Rd5,MemRsRelShiftC3w EndPacket is iclass=3 & op2127=0x54 & op0506=0 & Rd5 & MemRsRelShiftC3w & $(END_PACKET) { + Rd5 = MemRsRelShiftC3w; + build EndPacket; +} + +# (v4,9) memw -- "Rd32 = memw ( Rt32 << #n2 + #U6x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 1 0 1 1 0 0 t t t t t P P n 1 I I I I n I I d d d d d + +:memw Rd5,LdMemRsRelShiftxC9w EndPacket is iclass=9 & op2127=0x6c & op12=1 & Rd5 & LdMemRsRelShiftxC9w & $(END_PACKET) { + Rd5 = LdMemRsRelShiftxC9w; + build EndPacket; +} + +# (v2,9) memw -- "Rd32 = memw ( Rz32 ++ #s4:2 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 1 1 1 0 0 z z z z z P P 0 0 + + + i i i i d d d d d + +:memw Rd5,LdMemAIS4C9w EndPacket is iclass=9 & op2127=0x5c & op0913=0 & Rd5 & LdMemAIS4C9w & $(END_PACKET) { + Rd5 = LdMemAIS4C9w; + build EndPacket; +} + +# (v2,9) memw -- "Rd32 = memw ( Rz32 ++ #s4:2 :circ ( Mu2 ) )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 0 1 1 0 0 z z z z z P P u 0 + + 0 i i i i d d d d d + +:memw Rd5,LdMemAIS4CircMuC9w EndPacket is iclass=9 & op2127=0x4c & op0912=0 & Rd5 & LdMemAIS4CircMuC9w & $(END_PACKET) { + Rd5 = LdMemAIS4CircMuC9w; + build EndPacket; +} + +# (v2,9) memw -- "Rd32 = memw ( Rz32 ++ Mu2 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 1 0 1 1 0 0 z z z z z P P u 0 + + + + 0 + + d d d d d +# +# (v2,9) memw -- "Rd32 = memw ( Rz32 ++ Mu2 :brev )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 1 1 1 1 0 0 z z z z z P P u 0 + + + + 0 + + d d d d d + +:memw Rd5,LdMemAIMuC9w EndPacket is iclass=9 & op2627=3 & op2124=0xc & op0512=0 & Rd5 & LdMemAIMuC9w & $(END_PACKET) { + Rd5 = LdMemAIMuC9w; + build EndPacket; +} + +# (v2,9) memw -- "Rd32 = memw ( Rz32 ++I :circ ( Mu2 ) )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 0 1 1 0 0 z z z z z P P u 0 + + 1 + 0 + + d d d d d + +:memw Rd5,LdMemAIICircMuC9w EndPacket is iclass=9 & op2127=0x4c & op0512=0x10 & Rd5 & LdMemAIICircMuC9w & $(END_PACKET) { + Rd5 = LdMemAIICircMuC9w; + build EndPacket; +} + +# (v2,4) memw -- "Rd32 = memw ( gp + #u16:2x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 1 i i 1 1 0 0 i i i i i P P i i i i i i i i i d d d d d + +:memw Rd5,LdMemGPRelxC4w EndPacket is iclass=4 & op27=1 & op2224=6 & op21=0 & Rd5 & LdMemGPRelxC4w & $(END_PACKET) { + Rd5 = LdMemGPRelxC4w; + build EndPacket; +} + +# (v4,10) memw -- "memw ( Rf32 = #U6x ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 1 1 1 0 1 f f f f f P P 0 1 0 t t t 1 + I I I I I I + +:memw StMemRsAssignxC10w,Nreg0810 EndPacket is iclass=10 & op2127=0x5d & op1113=2 & op0607=2 & Nreg0810 & StMemRsAssignxC10w & $(END_PACKET) { + build EndPacket; + <> + StMemRsAssignxC10w = Nreg0810; +} + +# (v4,10) memw -- "memw ( Rf32 = #U6x ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 1 1 1 0 0 f f f f f P P 0 t t t t t 1 - I I I I I I + +:memw StMemRsAssignxC10w,rt5 EndPacket is iclass=10 & op2127=0x5c & op13=0 & op0607=2 & rt5 & StMemRsAssignxC10w & $(END_PACKET) { + tmp:4 = rt5; + build EndPacket; + <> + StMemRsAssignxC10w = tmp; +} + +# (v4,10) memw -- "memw ( Rs32 + #s11:2x ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 0 i i 1 1 0 1 s s s s s P P i 1 0 t t t i i i i i i i i + +:memw StMemRsRelxC10w,Nreg0810 EndPacket is iclass=10 & op27=0 & op2224=6 & op21=1 & op1112=2 & Nreg0810 & StMemRsRelxC10w & $(END_PACKET) { + build EndPacket; + <> + StMemRsRelxC10w = Nreg0810; +} + +# (v2,10) memw -- "memw ( Rs32 + #s11:2x ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 0 i i 1 1 0 0 s s s s s P P i t t t t t i i i i i i i i + +:memw StMemRsRelxC10w,rt5 EndPacket is iclass=10 & op27=0 & op2224=6 & op21=0 & rt5 & StMemRsRelxC10w & $(END_PACKET) { + tmp:4 = rt5; + build EndPacket; + <> + StMemRsRelxC10w = tmp; +} + +# (v4,3) memw -- "memw ( Rs32 + #u6:2 ) = #S8x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 1 1 0 + + 1 0 s s s s s P P I i i i i i i I I I I I I I + +:memw StMemRsRelC3w,Simm32_13_0006x EndPacket is iclass=3 & op2127=0x62 & StMemRsRelC3w & Simm32_13_0006x & $(END_PACKET) { + build EndPacket; + <> + StMemRsRelC3w = Simm32_13_0006x; +} + +# (v4,3) memw -- "memw ( Rs32 + #u6:2x ) &= Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 1 1 1 0 + 1 0 s s s s s P P 0 i i i i i i 1 0 t t t t t + +:memw&= StMemRsRelxC3w,ru5 EndPacket is iclass=3 & op2127=0x72 & op13=0 & op0506=2 & StMemRsRelxC3w & ru5 & $(END_PACKET) { + tmp:4 = StMemRsRelxC3w & ru5; + build EndPacket; + <> + StMemRsRelxC3w = tmp; +} + +# (v4,3) memw -- "memw ( Rs32 + #u6:2x ) += #U5" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 1 1 1 1 + 1 0 s s s s s P P 0 i i i i i i 0 0 I I I I I + +:memw+= StMemRsRelxC3w,Uimm8_0004 EndPacket is iclass=3 & op2127=0x7a & op13=0 & op0506=0 & StMemRsRelxC3w & Uimm8_0004 & $(END_PACKET) { + tmp:4 = StMemRsRelxC3w + zext(Uimm8_0004); + build EndPacket; + <> + StMemRsRelxC3w = tmp; +} + +# (v4,3) memw -- "memw ( Rs32 + #u6:2x ) += Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 1 1 1 0 + 1 0 s s s s s P P 0 i i i i i i 0 0 t t t t t + +:memw+= StMemRsRelxC3w,ru5 EndPacket is iclass=3 & op2127=0x72 & op13=0 & op0506=0 & StMemRsRelxC3w & ru5 & $(END_PACKET) { + tmp:4 = StMemRsRelxC3w + ru5; + build EndPacket; + <> + StMemRsRelxC3w = tmp; +} + +# (v4,3) memw -- "memw ( Rs32 + #u6:2x ) -= #U5" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 1 1 1 1 + 1 0 s s s s s P P 0 i i i i i i 0 1 I I I I I + +:memw-= StMemRsRelxC3w,Uimm8_0004 EndPacket is iclass=3 & op2127=0x7a & op13=0 & op0506=1 & StMemRsRelxC3w & Uimm8_0004 & $(END_PACKET) { + tmp:4 = StMemRsRelxC3w - zext(Uimm8_0004); + build EndPacket; + <> + StMemRsRelxC3w = tmp; +} + +# (v4,3) memw -- "memw ( Rs32 + #u6:2x ) -= Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 1 1 1 0 + 1 0 s s s s s P P 0 i i i i i i 0 1 t t t t t + +:memw-= StMemRsRelxC3w,ru5 EndPacket is iclass=3 & op2127=0x72 & op13=0 & op0506=1 & StMemRsRelxC3w & ru5 & $(END_PACKET) { + tmp:4 = StMemRsRelxC3w - ru5; + build EndPacket; + <> + StMemRsRelxC3w = tmp; +} + +# (v4,3) memw -- "memw ( Rs32 + #u6:2x ) = clrbit ( #U5 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 1 1 1 1 + 1 0 s s s s s P P 0 i i i i i i 1 0 I I I I I + +:memw StMemRsRelxC3w,ClrBit_0004w EndPacket is iclass=3 & op2127=0x7a & op13=0 & op0506=2 & StMemRsRelxC3w & ClrBit_0004w & $(END_PACKET) { + tmp:4 = StMemRsRelxC3w & ClrBit_0004w; + build EndPacket; + <> + StMemRsRelxC3w = tmp; +} + +# (v4,3) memw -- "memw ( Rs32 + #u6:2x ) = setbit ( #U5 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 1 1 1 1 + 1 0 s s s s s P P 0 i i i i i i 1 1 I I I I I + +:memw StMemRsRelxC3w,SetBit_0004w EndPacket is iclass=3 & op2127=0x7a & op13=0 & op0506=3 & StMemRsRelxC3w & SetBit_0004w & $(END_PACKET) { + tmp:4 = StMemRsRelxC3w | SetBit_0004w; + build EndPacket; + <> + StMemRsRelxC3w = tmp; +} + +# (v4,3) memw -- "memw ( Rs32 + #u6:2x ) |= Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 1 1 1 0 + 1 0 s s s s s P P 0 i i i i i i 1 1 t t t t t + +:memw|= StMemRsRelxC3w,ru5 EndPacket is iclass=3 & op2127=0x72 & op13=0 & op0506=3 & StMemRsRelxC3w & ru5 & $(END_PACKET) { + tmp:4 = StMemRsRelxC3w | ru5; + build EndPacket; + <> + StMemRsRelxC3w = tmp; +} + +# (v4,3) memw -- "memw ( Rs32 + Ru32 << #n2 ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 1 0 1 1 1 0 1 s s s s s P P n u u u u u n + + 1 0 t t t + +:memw MemRsRelShiftC3w,Nreg0002 EndPacket is iclass=3 & op2127=0x5d & op0306=2 & MemRsRelShiftC3w & Nreg0002 & $(END_PACKET) { + build EndPacket; + <> + MemRsRelShiftC3w = Nreg0002; +} + +# (v4,3) memw -- "memw ( Rs32 + Ru32 << #n2 ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 1 0 1 1 1 0 0 s s s s s P P n u u u u u n + + t t t t t + +:memw MemRsRelShiftC3w,ru5 EndPacket is iclass=3 & op2127=0x5c & op0506=0 & MemRsRelShiftC3w & ru5 & $(END_PACKET) { + tmp:4 = ru5; + build EndPacket; + <> + MemRsRelShiftC3w = tmp; +} + +# (v4,10) memw -- "memw ( Ru32 << #n2 + #U6x ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 1 0 1 1 0 1 u u u u u P P n 1 0 t t t 1 n I I I I I I + +:memw StMemRsRelShiftxC10w,Nreg0810 EndPacket is iclass=10 & op2127=0x6d & op1112=2 & op7=1 & Nreg0810 & StMemRsRelShiftxC10w & $(END_PACKET) { + build EndPacket; + <> + StMemRsRelShiftxC10w = Nreg0810; +} + +# (v4,10) memw -- "memw ( Ru32 << #n2 + #U6x ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 1 0 1 1 0 0 u u u u u P P n t t t t t 1 n I I I I I I + +:memw StMemRsRelShiftxC10w,rt5 EndPacket is iclass=10 & op2127=0x6c & op7=1 & rt5 & StMemRsRelShiftxC10w & $(END_PACKET) { + tmp:4 = rt5; + build EndPacket; + <> + StMemRsRelShiftxC10w = tmp; +} + +# (v4,10) memw -- "memw ( Rz32 ++ #s4:2 ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 1 1 1 0 1 z z z z z P P 0 1 0 t t t 0 i i i i + 0 + + +:memw StMemAIS4C10w,Nreg0810 EndPacket is iclass=10 & op2127=0x5d & op1113=2 & op7=0 & op0002=0 & Nreg0810 & StMemAIS4C10w & $(END_PACKET) { + build EndPacket; + <> + StMemAIS4C10w = Nreg0810; +} + +# (v4,10) memw -- "memw ( Rz32 ++ #s4:2 :circ ( Mu2 ) ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 0 1 1 0 1 z z z z z P P u 1 0 t t t 0 i i i i + 0 + + +:memw StMemAIS4CircMuC10w,Nreg0810 EndPacket is iclass=10 & op2127=0x4d & op1112=2 & op7=0 & op0002=0 & Nreg0810 & StMemAIS4CircMuC10w & $(END_PACKET) { + build EndPacket; + <> + StMemAIS4CircMuC10w = Nreg0810; +} + +# (v4,10) memw -- "memw ( Rz32 ++ Mu2 ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 1 0 1 1 0 1 z z z z z P P u 1 0 t t t 0 + + + + + + + +# +# (v4,10) memw -- "memw ( Rz32 ++ Mu2 :brev ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 1 1 1 1 0 1 z z z z z P P u 1 0 t t t 0 + + + + + + + + +:memw StMemAIMuC10w,Nreg0810 EndPacket is iclass=10 & op2627=3 & op2124=0xd & op1112=2 & op0007=0 & Nreg0810 & StMemAIMuC10w & $(END_PACKET) { + build EndPacket; + <> + StMemAIMuC10w = Nreg0810; +} + +# (v4,10) memw -- "memw ( Rz32 ++I :circ ( Mu2 ) ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 0 1 1 0 1 z z z z z P P u 1 0 t t t 0 + + + + + 1 + + +:memw StMemAIICircMuC10w,Nreg0810 EndPacket is iclass=10 & op2127=0x4d & op1112=2 & op0007=2 & Nreg0810 & StMemAIICircMuC10w & $(END_PACKET) { + build EndPacket; + <> + StMemAIICircMuC10w = Nreg0810; +} + +# (v2,10) memw -- "memw ( Rz32 ++ #s4:2 ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 1 1 1 0 0 z z z z z P P 0 t t t t t 0 i i i i - 0 - + +:memw StMemAIS4C10w,rt5 EndPacket is iclass=10 & op2127=0x5c & op13=0 & op7=0 & op0002=0 & rt5 & StMemAIS4C10w & $(END_PACKET) { + tmp:4 = rt5; + build EndPacket; + <> + StMemAIS4C10w = tmp; +} + +# (v2,10) memw -- "memw ( Rz32 ++ #s4:2 :circ ( Mu2 ) ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 0 1 1 0 0 z z z z z P P u t t t t t 0 i i i i + 0 + + +:memw StMemAIS4CircMuC10w,rt5 EndPacket is iclass=10 & op2127=0x4c & op7=0 & op0002=0 & rt5 & StMemAIS4CircMuC10w & $(END_PACKET) { + tmp:4 = rt5; + build EndPacket; + <> + StMemAIS4CircMuC10w = tmp; +} + +# (v2,10) memw -- "memw ( Rz32 ++ Mu2 ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 1 0 1 1 0 0 z z z z z P P u t t t t t 0 + + + + + + + +# +# (v2,10) memw -- "memw ( Rz32 ++ Mu2 :brev ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 1 1 1 1 0 0 z z z z z P P u t t t t t 0 + + + + + + + + +:memw StMemAIMuC10w,rt5 EndPacket is iclass=10 & op2627=3 & op2124=0xc & op0007=0 & rt5 & StMemAIMuC10w & $(END_PACKET) { + tmp:4 = rt5; + build EndPacket; + <> + StMemAIMuC10w = tmp; +} + +# (v2,10) memw -- "memw ( Rz32 ++I :circ ( Mu2 ) ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 0 1 1 0 0 z z z z z P P u t t t t t 0 + + + + + 1 + + +:memw StMemAIICircMuC10w,rt5 EndPacket is iclass=10 & op2127=0x4c & op0007=2 & rt5 & StMemAIICircMuC10w & $(END_PACKET) { + tmp:4 = rt5; + build EndPacket; + <> + StMemAIICircMuC10w = tmp; +} + +# (v4,4) memw -- "memw ( gp + #u16:2x ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 1 i i 0 1 0 1 i i i i i P P i 1 0 t t t i i i i i i i i + +:memw StMemGPRelxC4w,Nreg0810 EndPacket is iclass=4 & op27=1 & op2224=2 & op21=1 & op1112=2 & Nreg0810 & StMemGPRelxC4w & $(END_PACKET) { + build EndPacket; + <> + StMemGPRelxC4w = Nreg0810; +} + +# (v2,4) memw -- "memw ( gp + #u16:2x ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 1 i i 0 1 0 0 i i i i i P P i t t t t t i i i i i i i i + +:memw StMemGPRelxC4w,rt5 EndPacket is iclass=4 & op27=1 & op2224=2 & op21=0 & rt5 & StMemGPRelxC4w & $(END_PACKET) { + tmp:4 = rt5; + build EndPacket; + <> + StMemGPRelxC4w = tmp; +} + +# (v4,9) memw -- "if ( Pt4 ) Rd32 = memw ( #u6x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 1 1 1 1 0 0 i i i i i P P 1 0 0 t t i 1 + + d d d d d +# +# (v4,9) memw -- "if ( ! Pt4 ) Rd32 = memw ( #u6x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 1 1 1 1 0 0 i i i i i P P 1 0 1 t t i 1 + + d d d d d +# +# (v4,9) memw -- "if ( Pt4 .new ) Rd32 = memw ( #u6x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 1 1 1 1 0 0 i i i i i P P 1 1 0 t t i 1 + + d d d d d +# +# (v4,9) memw -- "if ( ! Pt4 .new ) Rd32 = memw ( #u6x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 1 1 1 1 0 0 i i i i i P P 1 1 1 t t i 1 + + d d d d d + +:memw^PuCond0910_N12_S11 rd5,LdMemAbsU6xC9w EndPacket is iclass=9 & op2127=0x7c & op13=1 & op0507=4 & rd5 & LdMemAbsU6xC9w & PuCond0910_N12_S11 & $(END_PACKET) { + tmp:4 = 0; + build PuCond0910_N12_S11; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + tmp = LdMemAbsU6xC9w; + + <> + if (ConditionReg == 0) goto ; + rd5 = tmp; + +} + +# (v2,4) memw -- "if ( Pt4 ) Rd32 = memw ( Rs32 + #u6:2x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 0 0 0 1 1 0 0 s s s s s P P 0 t t i i i i i i d d d d d +# +# (v2,4) memw -- "if ( ! Pt4 ) Rd32 = memw ( Rs32 + #u6:2x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 0 1 0 1 1 0 0 s s s s s P P 0 t t i i i i i i d d d d d +# +# (v2,4) memw -- "if ( Pt4 .new ) Rd32 = memw ( Rs32 + #u6:2x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 0 0 1 1 1 0 0 s s s s s P P 0 t t i i i i i i d d d d d +# +# (v2,4) memw -- "if ( ! Pt4 .new ) Rd32 = memw ( Rs32 + #u6:2x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 0 1 1 1 1 0 0 s s s s s P P 0 t t i i i i i i d d d d d + +:memw^PuCond1112_N25_S26 rd5,LdMemRsRelxC4w EndPacket is iclass=4 & op27=0 & op2224=6 & op21=0 & op13=0 & rd5 & LdMemRsRelxC4w & PuCond1112_N25_S26 & $(END_PACKET) { + tmp:4 = 0; + build PuCond1112_N25_S26; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + tmp = LdMemRsRelxC4w; + + <> + if (ConditionReg == 0) goto ; + rd5 = tmp; + +} + +# (v2,9) memw -- "if ( Pt4 ) Rd32 = memw ( Rz32 ++ #s4:2 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 1 1 1 0 0 z z z z z P P 1 0 0 t t i i i i d d d d d +# +# (v2,9) memw -- "if ( ! Pt4 ) Rd32 = memw ( Rz32 ++ #s4:2 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 1 1 1 0 0 z z z z z P P 1 0 1 t t i i i i d d d d d +# +# (v4,9) memw -- "if ( Pt4 .new ) Rd32 = memw ( Rz32 ++ #s4:2 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 1 1 1 0 0 z z z z z P P 1 1 0 t t i i i i d d d d d +# +# (v4,9) memw -- "if ( ! Pt4 .new ) Rd32 = memw ( Rz32 ++ #s4:2 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 1 1 1 0 0 z z z z z P P 1 1 1 t t i i i i d d d d d + +:memw^PuCond0910_N12_S11 rd5,LdMemAIS4C9w EndPacket is iclass=9 & op2127=0x5c & op13=1 & rd5 & LdMemAIS4C9w & PuCond0910_N12_S11 & $(END_PACKET) [ cond=1; ] { + tmp:4 = 0; + build PuCond0910_N12_S11; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + tmp = LdMemAIS4C9w; + + <> + if (ConditionReg == 0) goto ; + rd5 = tmp; + +} + +# (v4,3) memw -- "if ( Pv4 ) Rd32 = memw ( Rs32 + Rt32 << #n2 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 0 0 0 0 1 0 0 s s s s s P P n t t t t t n v v d d d d d +# +# (v4,3) memw -- "if ( ! Pv4 ) Rd32 = memw ( Rs32 + Rt32 << #n2 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 0 0 0 1 1 0 0 s s s s s P P n t t t t t n v v d d d d d +# +# (v4,3) memw -- "if ( Pv4 .new ) Rd32 = memw ( Rs32 + Rt32 << #n2 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 0 0 1 0 1 0 0 s s s s s P P n t t t t t n v v d d d d d +# +# (v4,3) memw -- "if ( ! Pv4 .new ) Rd32 = memw ( Rs32 + Rt32 << #n2 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 0 0 1 1 1 0 0 s s s s s P P n t t t t t n v v d d d d d + +:memw^PuCond0506_N25_S24 rd5,MemRsRelShiftC3w EndPacket is iclass=3 & op2627=0 & op2123=4 & rd5 & MemRsRelShiftC3w & PuCond0506_N25_S24 & $(END_PACKET) { + tmp:4 = 0; + build PuCond0506_N25_S24; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + tmp = MemRsRelShiftC3w; + + <> + if (ConditionReg == 0) goto ; + rd5 = tmp; + +} + +# (v4,10) memw -- "if ( Pv4 ) memw ( #u6x ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 1 1 1 1 0 1 + + + i i P P 0 1 0 t t t 1 i i i i 0 v v +# +# (v4,10) memw -- "if ( Pv4 .new ) memw ( #u6x ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 1 1 1 1 0 1 + + + i i P P 1 1 0 t t t 1 i i i i 0 v v +# +# (v4,10) memw -- "if ( ! Pv4 ) memw ( #u6x ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 1 1 1 1 0 1 + + + i i P P 0 1 0 t t t 1 i i i i 1 v v +# +# (v4,10) memw -- "if ( ! Pv4 .new ) memw ( #u6x ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 1 1 1 1 0 1 + + + i i P P 1 1 0 t t t 1 i i i i 1 v v + +:memw^PuCond0001_N13_S02 StMemAbsU6xC10w,Nreg0810 EndPacket is iclass=10 & op2127=0x7d & op1820=0 & op1112=2 & op7=1 & Nreg0810 & StMemAbsU6xC10w & PuCond0001_N13_S02 & $(END_PACKET) { + build PuCond0001_N13_S02; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + StMemAbsU6xC10w = Nreg0810; + +} + +# (v4,10) memw -- "if ( Pv4 ) memw ( #u6x ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 1 1 1 1 0 0 - - - i i P P 0 t t t t t 1 i i i i 0 v v +# +# (v4,10) memw -- "if ( ! Pv4 ) memw ( #u6x ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 1 1 1 1 0 0 - - - i i P P 0 t t t t t 1 i i i i 1 v v +# +# (v4,10) memw -- "if ( Pv4 .new ) memw ( #u6x ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 1 1 1 1 0 0 - - - i i P P 1 t t t t t 1 i i i i 0 v v +# +# (v4,10) memw -- "if ( ! Pv4 .new ) memw ( #u6x ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 1 1 1 1 0 0 + + + i i P P 1 t t t t t 1 i i i i 1 v v + +:memw^PuCond0001_N13_S02 StMemAbsU6xC10w,rt5 EndPacket is iclass=10 & op2127=0x7c & op1820=0 & op7=1 & rt5 & StMemAbsU6xC10w & PuCond0001_N13_S02 & $(END_PACKET) { + tmp:4 = rt5; + build PuCond0001_N13_S02; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + StMemAbsU6xC10w = tmp; + +} + +# (v4,3) memw -- "if ( Pv4 ) memw ( Rs32 + #u6:2 ) = #S6x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 1 0 0 0 0 1 0 s s s s s P P I i i i i i i v v I I I I I +# +# (v4,3) memw -- "if ( ! Pv4 ) memw ( Rs32 + #u6:2 ) = #S6x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 1 0 0 0 1 1 0 s s s s s P P I i i i i i i v v I I I I I +# +# (v4,3) memw -- "if ( Pv4 .new ) memw ( Rs32 + #u6:2 ) = #S6x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 1 0 0 1 0 1 0 s s s s s P P I i i i i i i v v I I I I I +# +# (v4,3) memw -- "if ( ! Pv4 .new ) memw ( Rs32 + #u6:2 ) = #S6x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 1 0 0 1 1 1 0 s s s s s P P I i i i i i i v v I I I I I + +:memw^PuCond0506_N24_S23 StMemRsRelC3w,Simm32_13_0004x EndPacket is iclass=3 & op2527=4 & op2122=2 & Simm32_13_0004x & StMemRsRelC3w & PuCond0506_N24_S23 & $(END_PACKET) { + build PuCond0506_N24_S23; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + StMemRsRelC3w = Simm32_13_0004x; + +} + +# (v4,4) memw -- "if ( Pv4 ) memw ( Rs32 + #u6:2x ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 0 0 0 0 1 0 1 s s s s s P P i 1 0 t t t i i i i i 0 v v +# +# (v4,4) memw -- "if ( ! Pv4 ) memw ( Rs32 + #u6:2x ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 0 1 0 0 1 0 1 s s s s s P P i 1 0 t t t i i i i i 0 v v +# +# (v4,4) memw -- "if ( Pv4 .new ) memw ( Rs32 + #u6:2x ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 0 0 1 0 1 0 1 s s s s s P P i 1 0 t t t i i i i i 0 v v +# +# (v4,4) memw -- "if ( ! Pv4 .new ) memw ( Rs32 + #u6:2x ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 0 1 1 0 1 0 1 s s s s s P P i 1 0 t t t i i i i i 0 v v + +:memw^PuCond0001_N25_S26 StMemRsRelxC4w,Nreg0810 EndPacket is iclass=4 & op27=0 & op2224=2 & op21=1 & op1112=2 & op2=0 & Nreg0810 & StMemRsRelxC4w & PuCond0001_N25_S26 & $(END_PACKET) { + build PuCond0001_N25_S26; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + StMemRsRelxC4w = Nreg0810; + +} + +# (v2,4) memw -- "if ( Pv4 ) memw ( Rs32 + #u6:2x ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 0 0 0 0 1 0 0 s s s s s P P i t t t t t i i i i i 0 v v +# +# (v2,4) memw -- "if ( ! Pv4 ) memw ( Rs32 + #u6:2x ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 0 1 0 0 1 0 0 s s s s s P P i t t t t t i i i i i 0 v v +# +# (v4,4) memw -- "if ( Pv4 .new ) memw ( Rs32 + #u6:2x ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 0 0 1 0 1 0 0 s s s s s P P i t t t t t i i i i i 0 v v +# +# (v4,4) memw -- "if ( ! Pv4 .new ) memw ( Rs32 + #u6:2x ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 0 0 1 1 0 1 0 0 s s s s s P P i t t t t t i i i i i 0 v v + +:memw^PuCond0001_N25_S26 StMemRsRelxC4w,rt5 EndPacket is iclass=4 & op27=0 & op2224=2 & op21=0 & op2=0 & rt5 & StMemRsRelxC4w & PuCond0001_N25_S26 & $(END_PACKET) { + tmp:4 = rt5; + build PuCond0001_N25_S26; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + StMemRsRelxC4w = tmp; + +} + +# (v4,3) memw -- "if ( Pv4 ) memw ( Rs32 + Ru32 << #n2 ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 0 1 0 0 1 0 1 s s s s s P P n u u u u u n v v 1 0 t t t +# +# (v4,3) memw -- "if ( Pv4 .new ) memw ( Rs32 + Ru32 << #n2 ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 0 1 1 0 1 0 1 s s s s s P P n u u u u u n v v 1 0 t t t +# +# (v4,3) memw -- "if ( ! Pv4 ) memw ( Rs32 + Ru32 << #n2 ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 0 1 0 1 1 0 1 s s s s s P P n u u u u u n v v 1 0 t t t +# +# (v4,3) memw -- "if ( ! Pv4 .new ) memw ( Rs32 + Ru32 << #n2 ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 0 1 1 1 1 0 1 s s s s s P P n u u u u u n v v 1 0 t t t + +:memw^PuCond0506_N25_S24 MemRsRelShiftC3w,Nreg0002 EndPacket is iclass=3 & op2627=1 & op2123=5 & op0304=2 & Nreg0002 & MemRsRelShiftC3w & PuCond0506_N25_S24 & $(END_PACKET) { + build PuCond0506_N25_S24; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + MemRsRelShiftC3w = Nreg0002; + +} + +# (v4,3) memw -- "if ( Pv4 ) memw ( Rs32 + Ru32 << #n2 ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 0 1 0 0 1 0 0 s s s s s P P n u u u u u n v v t t t t t +# +# (v4,3) memw -- "if ( ! Pv4 ) memw ( Rs32 + Ru32 << #n2 ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 0 1 0 1 1 0 0 s s s s s P P n u u u u u n v v t t t t t +# +# (v4,3) memw -- "if ( Pv4 .new ) memw ( Rs32 + Ru32 << #n2 ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 0 1 1 0 1 0 0 s s s s s P P n u u u u u n v v t t t t t +# +# (v4,3) memw -- "if ( ! Pv4 .new ) memw ( Rs32 + Ru32 << #n2 ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 0 1 1 1 1 0 0 s s s s s P P n u u u u u n v v t t t t t + +:memw^PuCond0506_N25_S24 MemRsRelShiftC3w,ru5 EndPacket is iclass=3 & op2627=1 & op2223=2 & op21=0 & ru5 & MemRsRelShiftC3w & PuCond0506_N25_S24 & $(END_PACKET) { + tmp:4 = ru5; + build PuCond0506_N25_S24; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + MemRsRelShiftC3w = tmp; + +} + +# (v4,10) memw -- "if ( Pv4 ) memw ( Rz32 ++ #s4:2 ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 1 1 1 0 1 z z z z z P P 1 1 0 t t t 0 i i i i 0 v v +# +# (v4,10) memw -- "if ( Pv4 .new ) memw ( Rz32 ++ #s4:2 ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 1 1 1 0 1 z z z z z P P 1 1 0 t t t 1 i i i i 0 v v +# +# (v4,10) memw -- "if ( ! Pv4 ) memw ( Rz32 ++ #s4:2 ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 1 1 1 0 1 z z z z z P P 1 1 0 t t t 0 i i i i 1 v v +# +# (v4,10) memw -- "if ( ! Pv4 .new ) memw ( Rz32 ++ #s4:2 ) = Nt8 .new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 1 1 1 0 1 z z z z z P P 1 1 0 t t t 1 i i i i 1 v v + +:memw^PuCond0001_N07_S02 StMemAIS4C10w,Nreg0810 EndPacket is iclass=10 & op2127=0x5d & op1113=6 & Nreg0810 & StMemAIS4C10w & PuCond0001_N07_S02 & $(END_PACKET) [ cond=1; ] { + build PuCond0001_N07_S02; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + StMemAIS4C10w = Nreg0810; + +} + +# (v4,10) memw -- "if ( Pv4 .new ) memw ( Rz32 ++ #s4:2 ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 1 1 1 0 0 z z z z z P P 1 t t t t t 1 i i i i 0 v v +# +# (v4,10) memw -- "if ( ! Pv4 .new ) memw ( Rz32 ++ #s4:2 ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 1 1 1 0 0 z z z z z P P 1 t t t t t 1 i i i i 1 v v +# +# (v2,10) memw -- "if ( Pv4 ) memw ( Rz32 ++ #s4:2 ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 1 1 1 0 0 z z z z z P P 1 t t t t t 0 i i i i 0 v v +# +# (v2,10) memw -- "if ( ! Pv4 ) memw ( Rz32 ++ #s4:2 ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 1 1 1 0 0 z z z z z P P 1 t t t t t 0 i i i i 1 v v + +:memw^PuCond0001_N07_S02 StMemAIS4C10w,rt5 EndPacket is iclass=10 & op2127=0x5c & op13=1 & rt5 & StMemAIS4C10w & PuCond0001_N07_S02 & $(END_PACKET) [ cond=1; ] { + tmp:4 = rt5; + build PuCond0001_N07_S02; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + StMemAIS4C10w = tmp; + +} + +# memw_rl -- "memw_rl ( Rs32 ):at = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 0 0 0 0 1 0 1 s s s s s P P - t t t t t - - 0 0 1 0 d d + +:memw_rl":at" StMemRsRelPdC9w, rt5 EndPacket is iclass=0xa & op2127=0x05 & op13=0 & rt5 & op0607=0 & op0205=0x2 & StMemRsRelPdC9w & $(END_PACKET) { + tmp:4 = rt5; + build EndPacket; + <> + waitAllThreads(); + StMemRsRelPdC9w = tmp; +} + +# memw_rl -- "memw_rl ( Rs32 ):st = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 0 0 0 0 1 0 1 s s s s s P P - t t t t t - - 1 0 1 0 d d + +:memw_rl":st" StMemRsRelPdC9w, rt5 EndPacket is iclass=0xa & op2127=0x05 & op13=0 & rt5 & op0607=0 & op0205=0xa & StMemRsRelPdC9w & $(END_PACKET) { + tmp:4 = rt5; + build EndPacket; + <> + waitSameDomain(); + StMemRsRelPdC9w = tmp; +} + + +# (v2,9) memw_locked -- "Rd32 = memw_locked ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 0 0 1 0 0 0 0 s s s s s P P 0 0 + + + + + + + d d d d d + +:memw_locked Rd5,LdMemRsRelC9w EndPacket is iclass=9 & op2127=0x10 & op0513=0 & Rd5 & LdMemRsRelC9w & $(END_PACKET) { + # NOTE: Manual does not indicate lock use, cannot be group with other instructions + Rd5 = LdMemRsRelC9w; + build EndPacket; +} + +# (v2,10) memw_locked -- "memw_locked ( Rs32 , Pd4 ) = Rt32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 0 0 0 0 1 0 1 s s s s s P P + t t t t t + + + + + + d d + +:memw_locked StMemRsRelPdC9w,rt5 EndPacket is iclass=10 & op2127=0x05 & op13=0 & op0207=0 & StMemRsRelPdC9w & rt5 & pu0001 & $(END_PACKET) { + # NOTE: cannot be group with other instructions + rc:1 = lock(); + lockOK:1 = rc != 0; + tmp:4 = rt5; + build EndPacket; + <> + pu0001 = lockOK * 0xff; + <> + if (!lockOK) goto ; + StMemRsRelPdC9w = tmp; + unlock(); + +} + +# (v4,9) memw_phys -- "Rd32 = memw_phys ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 0 0 1 0 0 0 0 s s s s s P P 1 t t t t t + + + d d d d d + +define pcodeop memw_phys; + +:memw_phys Rd5,rs5,rt5 EndPacket is iclass=9 & op2127=0x10 & op13=1 & op0507=0 & Rd5 & rs5 & rt5 & $(END_PACKET) { + Rd5 = memw_phys(rs5,rt5); + build EndPacket; +} + +# (v2,13) min -- "Rd32 = min ( Rt32 , Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 1 0 1 1 0 1 s s s s s P P + t t t t t 0 + + d d d d d + +define pcodeop min; + +:min Rd5,rs5,rt5 EndPacket is iclass=13 & op2127=0x2d & op13=0 & op0507=0 & rs5 & rt5 & Rd5 & $(END_PACKET) { + Rd5 = min(rt5,rs5); + build EndPacket; +} + +# (v4,13) min -- "Rdd32 = min ( Rtt32 , Rss32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 1 1 0 1 s s s s s P P + t t t t t 1 1 0 d d d d d + +:min Rdd5,rss5,rtt5 EndPacket is iclass=13 & op2127=0x1d & op13=0 & op0507=6 & rss5 & rtt5 & Rdd5 & $(END_PACKET) { + Rdd5 = min(rtt5,rss5); + build EndPacket; +} + +# (v2,13) minu -- "Rd32 = minu ( Rt32 , Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 1 0 1 1 0 1 s s s s s P P + t t t t t 1 + + d d d d d + +define pcodeop minu; + +:minu Rd5,rs5,rt5 EndPacket is iclass=13 & op2127=0x2d & op13=0 & op0507=4 & rs5 & rt5 & Rd5 & $(END_PACKET) { + Rd5 = minu(rt5,rs5); + build EndPacket; +} + +# (v4,13) minu -- "Rdd32 = minu ( Rtt32 , Rss32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 1 1 0 1 s s s s s P P + t t t t t 1 1 1 d d d d d + +:minu Rdd5,rss5,rtt5 EndPacket is iclass=13 & op2127=0x1d & op13=0 & op0507=7 & rss5 & rtt5 & Rdd5 & $(END_PACKET) { + Rdd5 = minu(rtt5,rss5); + build EndPacket; +} + +# (v4,13) modwrap -- "Rd32 = modwrap ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 1 1 1 1 s s s s s P P + t t t t t 1 1 1 d d d d d +define pcodeop modwrap; +:modwrap Rd5,rs5,rt5 EndPacket is iclass=13 & op2127=0x1f & op13=0 & op0507=7 & rs5 & rt5 & Rd5 & $(END_PACKET) { + Rd5 = modwrap(rs5,rt5); + build EndPacket; +} + +# movlen -- "Rd32 = movlen ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 1 1 1 1 1 1 1 t t t t t P P 0 s s s s s 0 1 0 d d d d d +# (Rs and Rt are swapped in this instruction) +define pcodeop movlen; + +:movlen Rd5,rt5,rs5 EndPacket is iclass=6 & op2127=0x7f & op13=0 & op0507=2 & rs5 & rt5 & Rd5 & $(END_PACKET) { + Rd5 = movlen(rt5,rs5); + build EndPacket; +} + +# (v2,14) mpy -- "Rd32 = mpy ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 0 1 0 0 0 s s s s s P P + t t t t t 0 0 1 d d d d d + +:mpy Rd5,rs5,rt5 EndPacket is iclass=14 & op2127=0x68 & op13=0 & op0507=1 & rs5 & rt5 & Rd5 & $(END_PACKET) { + tmp:8 = sext(rs5) * sext(rt5); + Rd5 = tmp(4); # Use upper 32-bits of result + build EndPacket; +} + +# (v4,14) mpy -- "Rd32 = mpy ( Rs32 , Rt32 ) :<<1" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 0 1 1 0 1 s s s s s P P + t t t t t 0 1 0 d d d d d + +:mpy^":<<1" Rd5,rs5,rt5 EndPacket is iclass=14 & op2127=0x6d & op13=0 & op0507=2 & rs5 & rt5 & Rd5 & $(END_PACKET) { + tmp:8 = (sext(rs5) * sext(rt5)) << 1; + Rd5 = tmp(4); # Use upper 32-bits of result + build EndPacket; +} + +# (v2,14) mpy -- "Rd32 = mpy ( Rs32 , Rt32 ) :rnd" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 0 1 0 0 1 s s s s s P P + t t t t t 0 0 1 d d d d d + +:mpy^":rnd" Rd5,rs5,rt5 EndPacket is iclass=14 & op2127=0x69 & op13=0 & op0507=1 & rs5 & rt5 & Rd5 & $(END_PACKET){ + tmp:8 = (sext(rs5) * sext(rt5)) + 0x80000000; + Rd5 = tmp(4); # Use upper 32-bits of result + build EndPacket; +} + +# (v4,14) mpy -- "Rd32 = mpy ( Rs32 , Rt32 ) :<<1 :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 0 1 1 1 1 s s s s s P P + t t t t t 0 0 0 d d d d d + +# mpyX2SatUpper(a,b,shift) sat_32( ((a * b) << 1) >> shift ) +# Multiply (a * b) with additional x2 multiplier and use shifted result before saturation for a 32-bit result +define pcodeop mpyX2SatUpper; + +:mpy^":<<1:sat" Rd5,rs5,rt5 EndPacket is iclass=14 & op2127=0x6f & op13=0 & op0507=0 & rs5 & rt5 & Rd5 & $(END_PACKET) { + Rd5 = mpyX2SatUpper(rs5, rt5, 32:1); + build EndPacket; +} + +# (v4,14) mpy -- "Rd32 = mpy ( Rs32 , Rt32.h ) :<<1 :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 0 1 1 0 1 s s s s s P P + t t t t t 0 0 0 d d d d d + +:mpy^":<<1:sat" Rd5,rs5,rt5H EndPacket is iclass=14 & op2127=0x6d & op13=0 & op0507=0 & rs5 & rt5H & Rd5 & $(END_PACKET) { + Rd5 = mpyX2SatUpper(rs5, rt5H, 16:1); + build EndPacket; +} + +# (v4,14) mpy -- "Rd32 = mpy ( Rs32 , Rt32.l ) :<<1 :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 0 1 1 0 1 s s s s s P P + t t t t t 0 0 1 d d d d d + +:mpy^":<<1:sat" Rd5,rs5,rt5L EndPacket is iclass=14 & op2127=0x6d & op13=0 & op0507=1 & rs5 & rt5L & Rd5 & $(END_PACKET) { + Rd5 = mpyX2SatUpper(rs5, rt5L, 16:1); + build EndPacket; +} + +# (v2,14) mpy -- "Rd32 = mpy ( Rs32 , Rt32.h ) :<<1 :rnd :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 0 1 1 0 1 s s s s s P P + t t t t t 1 0 0 d d d d d + +# mpyX2RndSatUpper(a,b,shift) sat_32( ( ((a * b) << 1 + (1<<(shift-1)) ) >> shift ) +# Multiply (a * b) with additional x2 multiplier and use shifted and rounded result before saturation for a 32-bit result +define pcodeop mpyX2RndSatUpper; + +:mpy^":<<1:rnd:sat" Rd5,rs5,rt5H EndPacket is iclass=14 & op2127=0x6d & op13=0 & op0507=4 & rs5 & rt5H & Rd5 & $(END_PACKET) { + Rd5 = mpyX2RndSatUpper(rs5, rt5H, 16:1); + build EndPacket; +} + +# (v2,14) mpy -- "Rd32 = mpy ( Rs32 , Rt32.l ) :<<1 :rnd :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 0 1 1 1 1 s s s s s P P + t t t t t 1 0 0 d d d d d + +:mpy^":<<1:rnd:sat" Rd5,rs5,rt5L EndPacket is iclass=14 & op2127=0x6f & op13=0 & op0507=4 & rs5 & rt5L & Rd5 & $(END_PACKET) { + Rd5 = mpyX2RndSatUpper(rs5, rt5L, 16:1); + build EndPacket; +} + +# (v2,14) mpy -- "Rd32 = mpy ( Rs32.h , Rt32.h )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 0 0 0 0 0 s s s s s P P + t t t t t 0 1 1 d d d d d +# +# (v2,14) mpy -- "Rd32 = mpy ( Rs32.h , Rt32.l )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 0 0 0 0 0 s s s s s P P + t t t t t 0 1 0 d d d d d +# +# (v2,14) mpy -- "Rd32 = mpy ( Rs32.l , Rt32.h )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 0 0 0 0 0 s s s s s P P + t t t t t 0 0 1 d d d d d +# +# (v2,14) mpy -- "Rd32 = mpy ( Rs32.l , Rt32.l )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 0 0 0 0 0 s s s s s P P + t t t t t 0 0 0 d d d d d + +:mpy Rd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x60 & op13=0 & op7=0 & Rs5HL06 & Rt5HL05 & Rd5 & $(END_PACKET) { + Rd5 = sext(Rs5HL06) * sext(Rt5HL05); + build EndPacket; +} + +# (v2,14) mpy -- "Rd32 = mpy ( Rs32.h , Rt32.h ) :<<1" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 0 0 1 0 0 s s s s s P P + t t t t t 0 1 1 d d d d d +# +# (v2,14) mpy -- "Rd32 = mpy ( Rs32.h , Rt32.l ) :<<1" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 0 0 1 0 0 s s s s s P P + t t t t t 0 1 0 d d d d d +# +# (v2,14) mpy -- "Rd32 = mpy ( Rs32.l , Rt32.h ) :<<1" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 0 0 1 0 0 s s s s s P P + t t t t t 0 0 1 d d d d d +# +# (v2,14) mpy -- "Rd32 = mpy ( Rs32.l , Rt32.l ) :<<1" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 0 0 1 0 0 s s s s s P P + t t t t t 0 0 0 d d d d d + +:mpy^":<<1" Rd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x64 & op13=0 & op7=0 & Rs5HL06 & Rt5HL05 & Rd5 & $(END_PACKET) { + Rd5 = (sext(Rs5HL06) * sext(Rt5HL05)) << 1; + build EndPacket; +} + +# (v2,14) mpy -- "Rd32 = mpy ( Rs32.h , Rt32.h ) :<<1 :rnd" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 0 0 1 0 1 s s s s s P P + t t t t t 0 1 1 d d d d d +# +# (v2,14) mpy -- "Rd32 = mpy ( Rs32.h , Rt32.l ) :<<1 :rnd" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 0 0 1 0 1 s s s s s P P + t t t t t 0 1 0 d d d d d +# +# (v2,14) mpy -- "Rd32 = mpy ( Rs32.l , Rt32.h ) :<<1 :rnd" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 0 0 1 0 1 s s s s s P P + t t t t t 0 0 1 d d d d d +# +# (v2,14) mpy -- "Rd32 = mpy ( Rs32.l , Rt32.l ) :<<1 :rnd" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 0 0 1 0 1 s s s s s P P + t t t t t 0 0 0 d d d d d + +:mpy^":<<1:rnd" Rd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x65 & op13=0 & op7=0 & Rs5HL06 & Rt5HL05 & Rd5 & $(END_PACKET) { + tmp:4 = ((sext(Rs5HL06) * sext(Rt5HL05)) << 1) + 0x8000; + Rd5 = tmp >> 16; # Use upper 16-bits of result + build EndPacket; +} + +# (v2,14) mpy -- "Rd32 = mpy ( Rs32.h , Rt32.h ) :<<1 :rnd :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 0 0 1 0 1 s s s s s P P + t t t t t 1 1 1 d d d d d +# +# (v2,14) mpy -- "Rd32 = mpy ( Rs32.h , Rt32.l ) :<<1 :rnd :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 0 0 1 0 1 s s s s s P P + t t t t t 1 1 0 d d d d d +# +# (v2,14) mpy -- "Rd32 = mpy ( Rs32.l , Rt32.h ) :<<1 :rnd :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 0 0 1 0 1 s s s s s P P + t t t t t 1 0 1 d d d d d +# +# (v2,14) mpy -- "Rd32 = mpy ( Rs32.l , Rt32.l ) :<<1 :rnd :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 0 0 1 0 1 s s s s s P P + t t t t t 1 0 0 d d d d d + +# mpyX2RndSat(a,b) sat_32( ( ((a * b) << 1 + (1<<(shift-1)) ) ) +# Multiply (a * b) with additional x2 multiplier and use rounded result before saturation for a 32-bit result +define pcodeop mpyX2RndSat; + +:mpy^":<<1:rnd:sat" Rd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x65 & op13=0 & op7=1 & Rs5HL06 & Rt5HL05 & Rd5 & $(END_PACKET) { + Rd5 = mpyX2RndSat(Rs5HL06, Rt5HL05); + build EndPacket; +} + +# (v2,14) mpy -- "Rd32 = mpy ( Rs32.h , Rt32.h ) :<<1 :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 0 0 1 0 0 s s s s s P P + t t t t t 1 1 1 d d d d d +# +# (v2,14) mpy -- "Rd32 = mpy ( Rs32.h , Rt32.l ) :<<1 :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 0 0 1 0 0 s s s s s P P + t t t t t 1 1 0 d d d d d +# +# (v2,14) mpy -- "Rd32 = mpy ( Rs32.l , Rt32.h ) :<<1 :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 0 0 1 0 0 s s s s s P P + t t t t t 1 0 1 d d d d d +# +# (v2,14) mpy -- "Rd32 = mpy ( Rs32.l , Rt32.l ) :<<1 :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 0 0 1 0 0 s s s s s P P + t t t t t 1 0 0 d d d d d + +# mpyX2Sat(a,b) sat_32( ((a * b) << 1 ) +# Multiply (a * b) with additional x2 multiplier before saturation for a 32-bit result +define pcodeop mpyX2Sat; + +:mpy^":<<1:sat" Rd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x64 & op13=0 & op7=1 & Rs5HL06 & Rt5HL05 & Rd5 & $(END_PACKET) { + Rd5 = mpyX2Sat(Rs5HL06, Rt5HL05); + build EndPacket; +} + +# (v2,14) mpy -- "Rd32 = mpy ( Rs32.h , Rt32.h ) :rnd" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 0 0 0 0 1 s s s s s P P + t t t t t 0 1 1 d d d d d +# +# (v2,14) mpy -- "Rd32 = mpy ( Rs32.h , Rt32.l ) :rnd" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 0 0 0 0 1 s s s s s P P + t t t t t 0 1 0 d d d d d +# +# (v2,14) mpy -- "Rd32 = mpy ( Rs32.l , Rt32.h ) :rnd" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 0 0 0 0 1 s s s s s P P + t t t t t 0 0 1 d d d d d +# +# (v2,14) mpy -- "Rd32 = mpy ( Rs32.l , Rt32.l ) :rnd" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 0 0 0 0 1 s s s s s P P + t t t t t 0 0 0 d d d d d + +:mpy^":rnd" Rd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x61 & op13=0 & op7=0 & Rs5HL06 & Rt5HL05 & Rd5 & $(END_PACKET) { + tmp:4 = (sext(Rs5HL06) * sext(Rt5HL05)) + 0x8000; + Rd5 = tmp >> 16; # Use upper 16-bits of result + build EndPacket; +} + +# (v2,14) mpy -- "Rd32 = mpy ( Rs32.h , Rt32.h ) :rnd :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 0 0 0 0 1 s s s s s P P + t t t t t 1 1 1 d d d d d +# +# (v2,14) mpy -- "Rd32 = mpy ( Rs32.h , Rt32.l ) :rnd :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 0 0 0 0 1 s s s s s P P + t t t t t 1 1 0 d d d d d +# +# (v2,14) mpy -- "Rd32 = mpy ( Rs32.l , Rt32.h ) :rnd :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 0 0 0 0 1 s s s s s P P + t t t t t 1 0 1 d d d d d +# +# (v2,14) mpy -- "Rd32 = mpy ( Rs32.l , Rt32.l ) :rnd :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 0 0 0 0 1 s s s s s P P + t t t t t 1 0 0 d d d d d + +# mpyRndSat(a,b) sat_32( ( ((a * b) + (1<<(shift-1)) ) ) +# Multiply (a * b) and use rounded result before saturation for a 32-bit result +define pcodeop mpyRndSat; + +:mpy^":rnd:sat" Rd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x61 & op13=0 & op7=1 & Rs5HL06 & Rt5HL05 & Rd5 & $(END_PACKET) { + Rd5 = mpyRndSat(Rs5HL06, Rt5HL05); + build EndPacket; +} + +# (v2,14) mpy -- "Rd32 = mpy ( Rs32.h , Rt32.h ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 0 0 0 0 0 s s s s s P P + t t t t t 1 1 1 d d d d d +# +# (v2,14) mpy -- "Rd32 = mpy ( Rs32.h , Rt32.l ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 0 0 0 0 0 s s s s s P P + t t t t t 1 1 0 d d d d d +# +# (v2,14) mpy -- "Rd32 = mpy ( Rs32.l , Rt32.h ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 0 0 0 0 0 s s s s s P P + t t t t t 1 0 1 d d d d d +# +# (v2,14) mpy -- "Rd32 = mpy ( Rs32.l , Rt32.l ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 0 0 0 0 0 s s s s s P P + t t t t t 1 0 0 d d d d d + +# mpySat(a,b) sat_32( a * b ) +# Multiply (a * b) with saturation for a 32-bit result +define pcodeop mpySat; + +:mpy^":sat" Rd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x60 & op13=0 & op7=1 & Rs5HL06 & Rt5HL05 & Rd5 & $(END_PACKET) { + Rd5 = mpySat(Rs5HL06, Rt5HL05); + build EndPacket; +} + +# (v2,14) mpy -- "Rdd32 = mpy ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 0 1 0 0 0 s s s s s P P + t t t t t 0 0 0 d d d d d + +:mpy Rdd5,rs5,rt5 EndPacket is iclass=14 & op2127=0x28 & op13=0 & op0507=0 & rs5 & rt5 & Rdd5 & $(END_PACKET) { + Rdd5 = sext(rs5) * sext(rt5); + build EndPacket; +} + +# (v2,14) mpy -- "Rdd32 = mpy ( Rs32.h , Rt32.h )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 0 0 0 0 0 s s s s s P P + t t t t t + 1 1 d d d d d +# +# (v2,14) mpy -- "Rdd32 = mpy ( Rs32.h , Rt32.l )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 0 0 0 0 0 s s s s s P P + t t t t t + 1 0 d d d d d +# +# (v2,14) mpy -- "Rdd32 = mpy ( Rs32.l , Rt32.h )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 0 0 0 0 0 s s s s s P P + t t t t t + 0 1 d d d d d +# +# (v2,14) mpy -- "Rdd32 = mpy ( Rs32.l , Rt32.l )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 0 0 0 0 0 s s s s s P P + t t t t t + 0 0 d d d d d + +:mpy Rdd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x20 & op13=0 & op7=0 & Rs5HL06 & Rt5HL05 & Rdd5 & $(END_PACKET) { + Rdd5 = sext(Rs5HL06) * sext(Rt5HL05); + build EndPacket; +} + +# (v2,14) mpy -- "Rdd32 = mpy ( Rs32.h , Rt32.h ) :<<1" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 0 0 1 0 0 s s s s s P P + t t t t t + 1 1 d d d d d +# +# (v2,14) mpy -- "Rdd32 = mpy ( Rs32.h , Rt32.l ) :<<1" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 0 0 1 0 0 s s s s s P P + t t t t t + 1 0 d d d d d +# +# (v2,14) mpy -- "Rdd32 = mpy ( Rs32.l , Rt32.h ) :<<1" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 0 0 1 0 0 s s s s s P P + t t t t t + 0 1 d d d d d +# +# (v2,14) mpy -- "Rdd32 = mpy ( Rs32.l , Rt32.l ) :<<1" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 0 0 1 0 0 s s s s s P P + t t t t t + 0 0 d d d d d + +:mpy^":<<1" Rdd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x24 & op13=0 & op7=0 & Rs5HL06 & Rt5HL05 & Rdd5 & $(END_PACKET) { + Rdd5 = (sext(Rs5HL06) * sext(Rt5HL05)) << 1; + build EndPacket; +} + +# (v2,14) mpy -- "Rdd32 = mpy ( Rs32.h , Rt32.h ) :<<1 :rnd" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 0 0 1 0 1 s s s s s P P + t t t t t + 1 1 d d d d d +# +# (v2,14) mpy -- "Rdd32 = mpy ( Rs32.h , Rt32.l ) :<<1 :rnd" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 0 0 1 0 1 s s s s s P P + t t t t t + 1 0 d d d d d +# +# (v2,14) mpy -- "Rdd32 = mpy ( Rs32.l , Rt32.h ) :<<1 :rnd" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 0 0 1 0 1 s s s s s P P + t t t t t + 0 1 d d d d d +# +# (v2,14) mpy -- "Rdd32 = mpy ( Rs32.l , Rt32.l ) :<<1 :rnd" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 0 0 1 0 1 s s s s s P P + t t t t t + 0 0 d d d d d + +:mpy^":<<1:rnd" Rdd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x25 & op13=0 & op7=0 & Rs5HL06 & Rt5HL05 & Rdd5 & $(END_PACKET) { + tmp:8 = ((sext(Rs5HL06) * sext(Rt5HL05)) << 1) + 0x80000000; + Rdd5 = tmp >> 32; + build EndPacket; +} + +# (v2,14) mpy -- "Rdd32 = mpy ( Rs32.h , Rt32.h ) :rnd" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 0 0 0 0 1 s s s s s P P + t t t t t + 1 1 d d d d d +# +# (v2,14) mpy -- "Rdd32 = mpy ( Rs32.h , Rt32.l ) :rnd" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 0 0 0 0 1 s s s s s P P + t t t t t + 1 0 d d d d d +# +# (v2,14) mpy -- "Rdd32 = mpy ( Rs32.l , Rt32.h ) :rnd" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 0 0 0 0 1 s s s s s P P + t t t t t + 0 1 d d d d d +# +# (v2,14) mpy -- "Rdd32 = mpy ( Rs32.l , Rt32.l ) :rnd" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 0 0 0 0 1 s s s s s P P + t t t t t + 0 0 d d d d d + +:mpy^":rnd" Rdd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x21 & op13=0 & op7=0 & Rs5HL06 & Rt5HL05 & Rdd5 & $(END_PACKET) { + tmp:8 = (sext(Rs5HL06) * sext(Rt5HL05)) + 0x80000000; + Rdd5 = tmp >> 32; + build EndPacket; +} + +# (v4,14) mpy -- "Rx32 += mpy ( Rs32 , Rt32 ) :<<1 :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 1 0 1 1 s s s s s P P + t t t t t + 0 0 x x x x x + +# mpyX2SatAddUpper(a,b,shift,accumulator) sat_32( ((a * b) << 1) >> shift + accumulator ) +# Multiply (a * b) with additional x2 multiplier and shifted result added to accumulator before saturation for a 32-bit result +define pcodeop mpyX2SatAddUpper; + +:mpy+=^":<<1:sat" Rd5,rs5,rt5 EndPacket is iclass=14 & op2127=0x7b & op13=0 & op0507=0 & rs5 & rt5 & rd5 & Rd5 & $(END_PACKET) { + Rd5 = mpyX2SatAddUpper(rs5, rt5, 32:1, rd5); + build EndPacket; +} + +# (v2,14) mpy -- "Rx32 += mpy ( Rs32.h , Rt32.h ) :<<1 :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 0 1 0 0 s s s s s P P + t t t t t 1 1 1 x x x x x +# +# (v2,14) mpy -- "Rx32 += mpy ( Rs32.h , Rt32.l ) :<<1 :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 0 1 0 0 s s s s s P P + t t t t t 1 1 0 x x x x x +# +# (v2,14) mpy -- "Rx32 += mpy ( Rs32.l , Rt32.h ) :<<1 :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 0 1 0 0 s s s s s P P + t t t t t 1 0 1 x x x x x +# +# (v2,14) mpy -- "Rx32 += mpy ( Rs32.l , Rt32.l ) :<<1 :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 0 1 0 0 s s s s s P P + t t t t t 1 0 0 x x x x x + +# mpyX2SatAdd(a,b,accumulator) sat_32( ((a * b) << 1) + accumulator ) +# Multiply (a * b) with additional x2 multiplier and add to accumulator before saturation for a 32-bit result +define pcodeop mpyX2SatAdd; + +:mpy+=^":<<1:sat" Rd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x74 & op13=0 & op7=1 & Rs5HL06 & Rt5HL05 & rd5 & Rd5 & $(END_PACKET) { + Rd5 = mpyX2SatAdd(Rs5HL06, Rt5HL05, rd5); + build EndPacket; +} + +# (v2,14) mpy -- "Rx32 += mpy ( Rs32.h , Rt32.h )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 0 0 0 0 s s s s s P P + t t t t t 0 1 1 x x x x x +# +# (v2,14) mpy -- "Rx32 += mpy ( Rs32.h , Rt32.l )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 0 0 0 0 s s s s s P P + t t t t t 0 1 0 x x x x x +# +# (v2,14) mpy -- "Rx32 += mpy ( Rs32.l , Rt32.h )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 0 0 0 0 s s s s s P P + t t t t t 0 0 1 x x x x x +# +# (v2,14) mpy -- "Rx32 += mpy ( Rs32.l , Rt32.l )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 0 0 0 0 s s s s s P P + t t t t t 0 0 0 x x x x x + +:mpy+= Rd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x70 & op13=0 & op7=0 & Rs5HL06 & Rt5HL05 & Rd5 & rd5 & $(END_PACKET) { + Rd5 = rd5 + (sext(Rs5HL06) * sext(Rt5HL05)); + build EndPacket; +} + +# (v2,14) mpy -- "Rx32 += mpy ( Rs32.h , Rt32.h ) :<<1" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 0 1 0 0 s s s s s P P + t t t t t 0 1 1 x x x x x +# +# (v2,14) mpy -- "Rx32 += mpy ( Rs32.h , Rt32.l ) :<<1" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 0 1 0 0 s s s s s P P + t t t t t 0 1 0 x x x x x +# +# (v2,14) mpy -- "Rx32 += mpy ( Rs32.l , Rt32.h ) :<<1" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 0 1 0 0 s s s s s P P + t t t t t 0 0 1 x x x x x +# +# (v2,14) mpy -- "Rx32 += mpy ( Rs32.l , Rt32.l ) :<<1" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 0 1 0 0 s s s s s P P + t t t t t 0 0 0 x x x x x + +:mpy+=^":<<1" Rd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x74 & op13=0 & op7=0 & Rs5HL06 & Rt5HL05 & Rd5 & rd5 & $(END_PACKET) { + tmp:4 = sext(Rs5HL06) * sext(Rt5HL05); + Rd5 = rd5 + (tmp << 1); + build EndPacket; +} + +# (v2,14) mpy -- "Rx32 += mpy ( Rs32.h , Rt32.h ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 0 0 0 0 s s s s s P P + t t t t t 1 1 1 x x x x x +# +# (v2,14) mpy -- "Rx32 += mpy ( Rs32.h , Rt32.l ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 0 0 0 0 s s s s s P P + t t t t t 1 1 0 x x x x x +# +# (v2,14) mpy -- "Rx32 += mpy ( Rs32.l , Rt32.h ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 0 0 0 0 s s s s s P P + t t t t t 1 0 1 x x x x x +# +# (v2,14) mpy -- "Rx32 += mpy ( Rs32.l , Rt32.l ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 0 0 0 0 s s s s s P P + t t t t t 1 0 0 x x x x x + +# mpySatAdd(a,b,accumulator) sat_32( (a * b) + accumulator ) +# Multiply (a * b) with additional x2 multiplier and add to accumulator before saturation for a 32-bit result +define pcodeop mpySatAdd; + +:mpy+=^":sat" Rd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x70 & op13=0 & op7=1 & Rs5HL06 & Rt5HL05 & rd5 & Rd5 & $(END_PACKET) { + Rd5 = mpySatAdd(Rs5HL06, Rt5HL05, rd5); + build EndPacket; +} + +# (v4,14) mpy -- "Rx32 -= mpy ( Rs32 , Rt32 ) :<<1 :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 1 0 1 1 s s s s s P P + t t t t t + 0 1 x x x x x + +# mpyX2SatSubUpper(a,b,shift,accumulator) sat_32( accumulator - ((a * b) << 1) >> shift ) +# Multiply (a * b) with additional x2 multiplier and shifted result subtracted from accumulator before saturation for a 32-bit result +define pcodeop mpyX2SatSubUpper; + +:mpy-=^":<<1:sat" Rd5,rs5,rt5 EndPacket is iclass=14 & op2127=0x7b & op13=0 & op0507=1 & rs5 & rt5 & rd5 & Rd5 & $(END_PACKET) { + Rd5 = mpyX2SatSubUpper(rs5, rt5, rd5); + build EndPacket; +} + +# (v2,14) mpy -- "Rx32 -= mpy ( Rs32.h , Rt32.h ) :<<1 :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 0 1 0 1 s s s s s P P + t t t t t 1 1 1 x x x x x +# +# (v2,14) mpy -- "Rx32 -= mpy ( Rs32.h , Rt32.l ) :<<1 :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 0 1 0 1 s s s s s P P + t t t t t 1 1 0 x x x x x +# +# (v2,14) mpy -- "Rx32 -= mpy ( Rs32.l , Rt32.h ) :<<1 :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 0 1 0 1 s s s s s P P - t t t t t 1 0 1 x x x x x +# +# (v2,14) mpy -- "Rx32 -= mpy ( Rs32.l , Rt32.l ) :<<1 :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 0 1 0 1 s s s s s P P + t t t t t 1 0 0 x x x x x + +# mpyX2SatSub(a,b,accumulator) sat_32( accumulator - ((a * b) << 1) ) +# Multiply (a * b) with additional x2 multiplier and subtract from accumulator before saturation for a 32-bit result +define pcodeop mpyX2SatSub; + +:mpy-=^":<<1:sat" Rd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x75 & op13=0 & op7=1 & Rs5HL06 & Rt5HL05 & rd5 & Rd5 & $(END_PACKET) { + Rd5 = mpyX2SatSub(Rs5HL06, Rt5HL05, rd5); + build EndPacket; +} + +# (v2,14) mpy -- "Rx32 -= mpy ( Rs32.h , Rt32.h )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 0 0 0 1 s s s s s P P + t t t t t 0 1 1 x x x x x +# +# (v2,14) mpy -- "Rx32 -= mpy ( Rs32.h , Rt32.l )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 0 0 0 1 s s s s s P P + t t t t t 0 1 0 x x x x x +# +# (v2,14) mpy -- "Rx32 -= mpy ( Rs32.l , Rt32.h )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 0 0 0 1 s s s s s P P + t t t t t 0 0 1 x x x x x +# +# (v2,14) mpy -- "Rx32 -= mpy ( Rs32.l , Rt32.l )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 0 0 0 1 s s s s s P P + t t t t t 0 0 0 x x x x x + +:mpy-= Rd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x71 & op13=0 & op7=0 & Rs5HL06 & Rt5HL05 & Rd5 & rd5 & $(END_PACKET) { + Rd5 = rd5 - (sext(Rs5HL06) * sext(Rt5HL05)); + build EndPacket; +} + +# (v2,14) mpy -- "Rx32 -= mpy ( Rs32.h , Rt32.h ) :<<1" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 0 1 0 1 s s s s s P P + t t t t t 0 1 1 x x x x x +# +# (v2,14) mpy -- "Rx32 -= mpy ( Rs32.h , Rt32.l ) :<<1" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 0 1 0 1 s s s s s P P + t t t t t 0 1 0 x x x x x +# +# (v2,14) mpy -- "Rx32 -= mpy ( Rs32.l , Rt32.h ) :<<1" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 0 1 0 1 s s s s s P P + t t t t t 0 0 1 x x x x x +# +# (v2,14) mpy -- "Rx32 -= mpy ( Rs32.l , Rt32.l ) :<<1" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 0 1 0 1 s s s s s P P + t t t t t 0 0 0 x x x x x + +:mpy-=^":<<1" Rd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x75 & op13=0 & op7=0 & Rs5HL06 & Rt5HL05 & Rd5 & rd5 & $(END_PACKET) { + # TODO: is only upper 16-bits of mpy result used? + tmp:4 = sext(Rs5HL06) * sext(Rt5HL05); + Rd5 = rd5 - (tmp << 1); + build EndPacket; +} + +# (v2,14) mpy -- "Rx32 -= mpy ( Rs32.h , Rt32.h ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 0 0 0 1 s s s s s P P + t t t t t 1 1 1 x x x x x +# +# (v2,14) mpy -- "Rx32 -= mpy ( Rs32.h , Rt32.l ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 0 0 0 1 s s s s s P P + t t t t t 1 1 0 x x x x x +# +# (v2,14) mpy -- "Rx32 -= mpy ( Rs32.l , Rt32.h ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 0 0 0 1 s s s s s P P + t t t t t 1 0 1 x x x x x +# +# (v2,14) mpy -- "Rx32 -= mpy ( Rs32.l , Rt32.l ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 0 0 0 1 s s s s s P P + t t t t t 1 0 0 x x x x x + +# mpySatSub(a,b,accumulator) sat_32( accumulator - (a * b) ) +# Multiply (a * b) and subtract from accumulator before saturation for a 32-bit result +define pcodeop mpySatSub; + +:mpy-=^":sat" Rd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x71 & op13=0 & op7=1 & Rs5HL06 & Rt5HL05 & rd5 & Rd5 & $(END_PACKET) { + Rd5 = mpySatSub(Rs5HL06, Rt5HL05, rd5); + build EndPacket; +} + +# (v2,14) mpy -- "Rxx32 += mpy ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 1 1 0 0 0 s s s s s P P + t t t t t 0 0 0 x x x x x + +:mpy+= Rdd5,rs5,rt5 EndPacket is iclass=14 & op2127=0x38 & op13=0 & op0507=0 & rs5 & rt5 & Rdd5 & rdd5 & $(END_PACKET) { + tmp:8 = sext(rs5) * sext(rt5); + Rdd5 = rdd5 + tmp; + build EndPacket; +} + +# (v2,14) mpy -- "Rxx32 += mpy ( Rs32.h , Rt32.h )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 1 0 0 0 0 s s s s s P P + t t t t t 0 1 1 x x x x x +# +# (v2,14) mpy -- "Rxx32 += mpy ( Rs32.h , Rt32.l )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 1 0 0 0 0 s s s s s P P + t t t t t 0 1 0 x x x x x +# +# (v2,14) mpy -- "Rxx32 += mpy ( Rs32.l , Rt32.h )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 1 0 0 0 0 s s s s s P P + t t t t t 0 0 1 x x x x x +# +# (v2,14) mpy -- "Rxx32 += mpy ( Rs32.l , Rt32.l )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 1 0 0 0 0 s s s s s P P + t t t t t 0 0 0 x x x x x + +:mpy+= Rdd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x30 & op13=0 & op7=0 & Rs5HL06 & Rt5HL05 & Rdd5 & rdd5 & $(END_PACKET) { + tmp:8 = sext(Rs5HL06) * sext(Rt5HL05); + Rdd5 = rdd5 + tmp; + build EndPacket; +} + +# (v2,14) mpy -- "Rxx32 += mpy ( Rs32.h , Rt32.h ) :<<1" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 1 0 1 0 0 s s s s s P P + t t t t t 0 1 1 x x x x x +# +# (v2,14) mpy -- "Rxx32 += mpy ( Rs32.h , Rt32.l ) :<<1" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 1 0 1 0 0 s s s s s P P + t t t t t 0 1 0 x x x x x +# +# (v2,14) mpy -- "Rxx32 += mpy ( Rs32.l , Rt32.h ) :<<1" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 1 0 1 0 0 s s s s s P P + t t t t t 0 0 1 x x x x x +# +# (v2,14) mpy -- "Rxx32 += mpy ( Rs32.l , Rt32.l ) :<<1" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 1 0 1 0 0 s s s s s P P + t t t t t 0 0 0 x x x x x + +:mpy+=^":<<1" Rdd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x34 & op13=0 & op7=0 & Rs5HL06 & Rt5HL05 & Rdd5 & rdd5 & $(END_PACKET) { + tmp:8 = sext(Rs5HL06) * sext(Rt5HL05); + Rdd5 = rdd5 + (tmp << 1); + build EndPacket; +} + +# (v2,14) mpy -- "Rxx32 -= mpy ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 1 1 0 0 1 s s s s s P P + t t t t t 0 0 0 x x x x x + +:mpy-= Rdd5,rs5,rt5 EndPacket is iclass=14 & op2127=0x39 & op13=0 & op0507=0 & rs5 & rt5 & Rdd5 & rdd5 & $(END_PACKET) { + Rdd5 = rdd5 - (sext(rs5) * sext(rt5)); + build EndPacket; +} + +# (v2,14) mpy -- "Rxx32 -= mpy ( Rs32.h , Rt32.h )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 1 0 0 0 1 s s s s s P P + t t t t t 0 1 1 x x x x x +# +# (v2,14) mpy -- "Rxx32 -= mpy ( Rs32.h , Rt32.l )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 1 0 0 0 1 s s s s s P P + t t t t t 0 1 0 x x x x x +# +# (v2,14) mpy -- "Rxx32 -= mpy ( Rs32.l , Rt32.h )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 1 0 0 0 1 s s s s s P P + t t t t t 0 0 1 x x x x x +# +# (v2,14) mpy -- "Rxx32 -= mpy ( Rs32.l , Rt32.l )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 1 0 0 0 1 s s s s s P P + t t t t t 0 0 0 x x x x x + +:mpy-= Rdd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x31 & op13=0 & op7=0 & Rs5HL06 & Rt5HL05 & Rdd5 & rdd5 & $(END_PACKET) { + tmp:8 = sext(Rs5HL06) * sext(Rt5HL05); + Rdd5 = rdd5 - tmp; + build EndPacket; +} + +# (v2,14) mpy -- "Rxx32 -= mpy ( Rs32.h , Rt32.h ) :<<1" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 1 0 1 0 1 s s s s s P P + t t t t t 0 1 1 x x x x x +# +# (v2,14) mpy -- "Rxx32 -= mpy ( Rs32.h , Rt32.l ) :<<1" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 1 0 1 0 1 s s s s s P P + t t t t t 0 1 0 x x x x x +# +# (v2,14) mpy -- "Rxx32 -= mpy ( Rs32.l , Rt32.h ) :<<1" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 1 0 1 0 1 s s s s s P P + t t t t t 0 0 1 x x x x x +# +# (v2,14) mpy -- "Rxx32 -= mpy ( Rs32.l , Rt32.l ) :<<1" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 1 0 1 0 1 s s s s s P P + t t t t t 0 0 0 x x x x x + +:mpy-=^":<<1" Rdd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x35 & op13=0 & op7=0 & Rs5HL06 & Rt5HL05 & Rdd5 & rdd5 & $(END_PACKET) { + tmp:8 = sext(Rs5HL06) * sext(Rt5HL05); + Rdd5 = rdd5 - (tmp << 1); + build EndPacket; +} + +# (v2,14) mpyi -- "Rd32 = + mpyi ( Rs32 , #u8x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 0 0 0 0 + + s s s s s P P + i i i i i i i i d d d d d + +:"+mpyi" Rd5,rs5,Uimm32_0512x EndPacket is iclass=14 &op2127=0x00 & op13=0 & rs5 & Rd5 & Uimm32_0512x & $(END_PACKET) { + Rd5 = rs5 * Uimm32_0512x; + build EndPacket; +} + +# (v2,14) mpyi -- "Rd32 = - mpyi ( Rs32 , #u8 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 0 0 0 1 + + s s s s s P P + i i i i i i i i d d d d d + +:"-mpyi" Rd5,rs5,Uimm8_0512 EndPacket is iclass=14 &op2127=0x04 & op13=0 & rs5 & Rd5 & Uimm8_0512 & $(END_PACKET) { + Rd5 = rs5 * sext(-Uimm8_0512); + build EndPacket; +} + +# (v2,14) mpyi -- "Rd32 = mpyi ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 0 1 0 0 0 s s s s s P P - t t t t t 0 0 0 d d d d d + +:mpyi Rd5,rs5,rt5 EndPacket is iclass=14 &op2127=0x68 & op13=0 & rs5 & rt5 & op0507=0 & Rd5 & $(END_PACKET) { + Rd5 = rs5 * rt5; + build EndPacket; +} + +# (v2,14) mpyi -- "Rx32 += mpyi ( Rs32 , #u8x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 0 0 1 0 + + s s s s s P P + i i i i i i i i x x x x x + +:mpyi+= Rd5,rs5,Uimm32_0512x EndPacket is iclass=14 &op2127=0x08 & op13=0 & rs5 & Rd5 & rd5 & Uimm32_0512x & $(END_PACKET) { + Rd5 = rd5 + (rs5 * Uimm32_0512x); + build EndPacket; +} + +# (v2,14) mpyi -- "Rx32 += mpyi ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 1 0 0 0 s s s s s P P + t t t t t + 0 0 x x x x x + +:mpyi+= Rd5,rs5,rt5 EndPacket is iclass=14 &op2127=0x78 & op13=0 & op0507=0 & rs5 & Rd5 & rd5 & rt5 & $(END_PACKET) { + Rd5 = rd5 + (rs5 * rt5); + build EndPacket; +} + +# (v2,14) mpyi -- "Rx32 -= mpyi ( Rs32 , #u8x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 0 0 1 1 + + s s s s s P P + i i i i i i i i x x x x x + +:mpyi-= Rd5,rs5,Uimm32_0512x EndPacket is iclass=14 &op2127=0x0c & op13=0 & rs5 & Rd5 & rd5 & Uimm32_0512x & $(END_PACKET) { + Rd5 = rd5 - (rs5 * Uimm32_0512x); + build EndPacket; +} + +# (v2,14) mpyi -- "Rx32 -= mpyi ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 1 0 0 0 s s s s s P P + t t t t t + 0 0 x x x x x + +:mpyi-= Rd5,rs5,rt5 EndPacket is iclass=14 &op2127=0x7c & op13=0 & op0507=0 & rs5 & Rd5 & rd5 & rt5 & $(END_PACKET) { + Rd5 = rd5 - (rs5 * rt5); + build EndPacket; +} + +# (v4,14) mpysu -- "Rd32 = mpysu ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 0 1 0 1 1 s s s s s P P + t t t t t 0 0 1 d d d d d + +:mpysu Rd5,rs5,rt5 EndPacket is iclass=14 & op2127=0x6b & op13=0 & op0507=1 & rs5 & rt5 & Rd5 & $(END_PACKET) { + tmp:8 = sext(rs5) * zext(rt5); + Rd5 = tmp(4); # use upper 32-bits of result + build EndPacket; +} + +# (v2,14) mpyu -- "Rd32 = mpyu ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 0 1 0 1 0 s s s s s P P + t t t t t 0 0 1 d d d d d + +:mpyu Rd5,rs5,rt5 EndPacket is iclass=14 & op2127=0x6a & op13=0 & op0507=1 & rs5 & rt5 & Rd5 & $(END_PACKET) { + tmp:8 = zext(rs5) * zext(rt5); + Rd5 = tmp(4); # use upper 32-bits of result + build EndPacket; +} + +# (v2,14) mpyu -- "Rd32 = mpyu ( Rs32.h , Rt32.l )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 0 0 0 1 0 s s s s s P P + t t t t t 0 1 0 d d d d d +# +# (v2,14) mpyu -- "Rd32 = mpyu ( Rs32.l , Rt32.h )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 0 0 0 1 0 s s s s s P P + t t t t t 0 0 1 d d d d d +# +# (v2,14) mpyu -- "Rd32 = mpyu ( Rs32.h , Rt32.h )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 0 0 0 1 0 s s s s s P P + t t t t t 0 1 1 d d d d d +# +# (v2,14) mpyu -- "Rd32 = mpyu ( Rs32.l , Rt32.l )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 0 0 0 1 0 s s s s s P P + t t t t t 0 0 0 d d d d d + +:mpyu Rd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x62 & op13=0 & op7=0 & Rs5HL06 & Rt5HL05 & Rd5 & $(END_PACKET) { + Rd5 = zext(Rs5HL06) * zext(Rt5HL05); + build EndPacket; +} + +# (v2,14) mpyu -- "Rd32 = mpyu ( Rs32.h , Rt32.h ) :<<1" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 0 0 1 1 0 s s s s s P P + t t t t t 0 1 1 d d d d d +# +# (v2,14) mpyu -- "Rd32 = mpyu ( Rs32.h , Rt32.l ) :<<1" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 0 0 1 1 0 s s s s s P P + t t t t t 0 1 0 d d d d d +# +# (v2,14) mpyu -- "Rd32 = mpyu ( Rs32.l , Rt32.h ) :<<1" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 0 0 1 1 0 s s s s s P P + t t t t t 0 0 1 d d d d d +# +# (v2,14) mpyu -- "Rd32 = mpyu ( Rs32.l , Rt32.l ) :<<1" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 0 0 1 1 0 s s s s s P P + t t t t t 0 0 0 d d d d d + +:mpyu^":<<1" Rd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x66 & op13=0 & op7=0 & Rs5HL06 & Rt5HL05 & Rd5 & $(END_PACKET) { + Rd5 = zext(Rs5HL06) * zext(Rs5HL06); + Rd5 = Rd5 << 1; + build EndPacket; +} + +# (v2,14) mpyu -- "Rdd32 = mpyu ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 0 1 0 1 0 s s s s s P P + t t t t t 0 0 0 d d d d d + +:mpyu Rdd5,rs5,rt5 EndPacket is iclass=14 & op2127=0x2a & op13=0 & op0507=0 & rs5 & rt5 & Rdd5 & $(END_PACKET) { + Rdd5 = zext(rs5) * zext(rt5); + build EndPacket; +} + +# (v2,14) mpyu -- "Rdd32 = mpyu ( Rs32.h , Rt32.h )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 0 0 0 1 0 s s s s s P P + t t t t t + 1 1 d d d d d +# +# (v2,14) mpyu -- "Rdd32 = mpyu ( Rs32.h , Rt32.l )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 0 0 0 1 0 s s s s s P P + t t t t t + 1 0 d d d d d +# +# (v2,14) mpyu -- "Rdd32 = mpyu ( Rs32.l , Rt32.h )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 0 0 0 1 0 s s s s s P P + t t t t t + 0 1 d d d d d +# +# (v2,14) mpyu -- "Rdd32 = mpyu ( Rs32.l , Rt32.l )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 0 0 0 1 0 s s s s s P P + t t t t t + 0 0 d d d d d + +:mpyu Rdd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x22 & op13=0 & op7=0 & Rs5HL06 & Rt5HL05 & Rdd5 & $(END_PACKET) { + Rdd5 = zext(Rs5HL06) * zext(Rt5HL05); + build EndPacket; +} + +# (v2,14) mpyu -- "Rdd32 = mpyu ( Rs32.h , Rt32.h ) :<<1" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 0 0 1 1 0 s s s s s P P + t t t t t + 1 1 d d d d d +# +# (v2,14) mpyu -- "Rdd32 = mpyu ( Rs32.h , Rt32.l ) :<<1" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 0 0 1 1 0 s s s s s P P + t t t t t + 1 0 d d d d d +# +# (v2,14) mpyu -- "Rdd32 = mpyu ( Rs32.l , Rt32.h ) :<<1" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 0 0 1 1 0 s s s s s P P + t t t t t + 0 1 d d d d d +# +# (v2,14) mpyu -- "Rdd32 = mpyu ( Rs32.l , Rt32.l ) :<<1" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 0 0 1 1 0 s s s s s P P + t t t t t + 0 0 d d d d d + +:mpyu^":<<1" Rdd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x26 & op13=0 & op7=0 & Rs5HL06 & Rt5HL05 & Rdd5 & $(END_PACKET) { + Rdd5 = zext(Rs5HL06) * zext(Rt5HL05); + Rdd5 = Rdd5 << 1; + build EndPacket; +} + +# (v2,14) mpyu -- "Rx32 += mpyu ( Rs32.h , Rt32.h )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 0 0 1 0 s s s s s P P + t t t t t 0 1 1 x x x x x +# +# (v2,14) mpyu -- "Rx32 += mpyu ( Rs32.h , Rt32.l )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 0 0 1 0 s s s s s P P + t t t t t 0 1 0 x x x x x +# +# (v2,14) mpyu -- "Rx32 += mpyu ( Rs32.l , Rt32.h )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 0 0 1 0 s s s s s P P + t t t t t 0 0 1 x x x x x +# +# (v2,14) mpyu -- "Rx32 += mpyu ( Rs32.l , Rt32.l )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 0 0 1 0 s s s s s P P + t t t t t 0 0 0 x x x x x + +:mpyu+= Rd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x72 & op13=0 & op7=0 & Rs5HL06 & Rt5HL05 & Rd5 & rd5 & $(END_PACKET) { + Rd5 = rd5 + (zext(Rs5HL06) * zext(Rt5HL05)); + build EndPacket; +} + +# (v2,14) mpyu -- "Rx32 += mpyu ( Rs32.h , Rt32.h ) :<<1" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 0 1 1 0 s s s s s P P + t t t t t 0 1 1 x x x x x +# +# (v2,14) mpyu -- "Rx32 += mpyu ( Rs32.h , Rt32.l ) :<<1" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 0 1 1 0 s s s s s P P + t t t t t 0 1 0 x x x x x +# +# (v2,14) mpyu -- "Rx32 += mpyu ( Rs32.l , Rt32.h ) :<<1" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 0 1 1 0 s s s s s P P + t t t t t 0 0 1 x x x x x +# +# (v2,14) mpyu -- "Rx32 += mpyu ( Rs32.l , Rt32.l ) :<<1" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 0 1 1 0 s s s s s P P + t t t t t 0 0 0 x x x x x + +:mpyu+=^":<<1" Rd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x76 & op13=0 & op7=0 & Rs5HL06 & Rt5HL05 & Rd5 & rd5 & $(END_PACKET) { + tmp:4 = zext(Rs5HL06) * zext(Rt5HL05); + Rd5 = rd5 + (tmp << 1); + build EndPacket; +} + +# (v2,14) mpyu -- "Rx32 -= mpyu ( Rs32.h , Rt32.h )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 0 0 1 1 s s s s s P P + t t t t t 0 1 1 x x x x x +# +# (v2,14) mpyu -- "Rx32 -= mpyu ( Rs32.h , Rt32.l )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 0 0 1 1 s s s s s P P + t t t t t 0 1 0 x x x x x +# +# (v2,14) mpyu -- "Rx32 -= mpyu ( Rs32.l , Rt32.h )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 0 0 1 1 s s s s s P P + t t t t t 0 0 1 x x x x x +# +# (v2,14) mpyu -- "Rx32 -= mpyu ( Rs32.l , Rt32.l )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 0 0 1 1 s s s s s P P + t t t t t 0 0 0 x x x x x + +:mpyu-= Rd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x73 & op13=0 & op7=0 & Rs5HL06 & Rt5HL05 & Rd5 & rd5 & $(END_PACKET) { + Rd5 = rd5 - (zext(Rs5HL06) * zext(Rt5HL05)); + build EndPacket; +} + +# (v2,14) mpyu -- "Rx32 -= mpyu ( Rs32.h , Rt32.h ) :<<1" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 0 1 1 1 s s s s s P P + t t t t t 0 1 1 x x x x x +# +# (v2,14) mpyu -- "Rx32 -= mpyu ( Rs32.h , Rt32.l ) :<<1" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 0 1 1 1 s s s s s P P + t t t t t 0 1 0 x x x x x +# +# (v2,14) mpyu -- "Rx32 -= mpyu ( Rs32.l , Rt32.h ) :<<1" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 0 1 1 1 s s s s s P P + t t t t t 0 0 1 x x x x x +# +# (v2,14) mpyu -- "Rx32 -= mpyu ( Rs32.l , Rt32.l ) :<<1" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 0 1 1 1 s s s s s P P + t t t t t 0 0 0 x x x x x + +:mpyu-=^":<<1" Rd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x77 & op13=0 & op7=0 & Rs5HL06 & Rt5HL05 & Rd5 & rd5 & $(END_PACKET) { + tmp:4 = zext(Rs5HL06) * zext(Rt5HL05); + Rd5 = rd5 - (tmp << 1); + build EndPacket; +} + +# (v2,14) mpyu -- "Rxx32 += mpyu ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 1 1 0 1 0 s s s s s P P + t t t t t 0 0 0 x x x x x + +:mpyu+= Rdd5,rs5,rt5 EndPacket is iclass=14 & op2127=0x3a & op13=0 & op0507=0 & rs5 & rt5 & Rdd5 & rdd5 & $(END_PACKET) { + tmp:8 = zext(rs5) * zext(rt5); + Rdd5 = rdd5 + tmp; + build EndPacket; +} + +# (v2,14) mpyu -- "Rxx32 += mpyu ( Rs32.h , Rt32.h )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 1 0 0 1 0 s s s s s P P + t t t t t 0 1 1 x x x x x +# +# (v2,14) mpyu -- "Rxx32 += mpyu ( Rs32.h , Rt32.l )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 1 0 0 1 0 s s s s s P P + t t t t t 0 1 0 x x x x x +# +# (v2,14) mpyu -- "Rxx32 += mpyu ( Rs32.l , Rt32.h )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 1 0 0 1 0 s s s s s P P + t t t t t 0 0 1 x x x x x +# +# (v2,14) mpyu -- "Rxx32 += mpyu ( Rs32.l , Rt32.l )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 1 0 0 1 0 s s s s s P P + t t t t t 0 0 0 x x x x x + +:mpyu+= Rdd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x32 & op13=0 & op7=0 & Rs5HL06 & Rt5HL05 & Rdd5 & rdd5 & $(END_PACKET) { + tmp:8 = zext(Rs5HL06) * zext(Rt5HL05); + Rdd5 = rdd5 + tmp; + build EndPacket; +} + +# (v2,14) mpyu -- "Rxx32 += mpyu ( Rs32.h , Rt32.h ) :<<1" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 1 0 1 1 0 s s s s s P P + t t t t t 0 1 1 x x x x x +# +# (v2,14) mpyu -- "Rxx32 += mpyu ( Rs32.h , Rt32.l ) :<<1" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 1 0 1 1 0 s s s s s P P + t t t t t 0 1 0 x x x x x +# +# (v2,14) mpyu -- "Rxx32 += mpyu ( Rs32.l , Rt32.h ) :<<1" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 1 0 1 1 0 s s s s s P P + t t t t t 0 0 1 x x x x x +# +# (v2,14) mpyu -- "Rxx32 += mpyu ( Rs32.l , Rt32.l ) :<<1" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 1 0 1 1 0 s s s s s P P + t t t t t 0 0 0 x x x x x + +:mpyu+=^":<<1" Rdd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x36 & op13=0 & op7=0 & Rs5HL06 & Rt5HL05 & Rdd5 & rdd5 & $(END_PACKET) { + tmp:8 = zext(Rs5HL06) * zext(Rs5HL06); + Rdd5 = rdd5 + (tmp << 1); + build EndPacket; +} + +# (v2,14) mpyu -- "Rxx32 -= mpyu ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 1 1 0 1 1 s s s s s P P + t t t t t 0 0 0 x x x x x + +:mpyu-= Rdd5,rs5,rt5 EndPacket is iclass=14 & op2127=0x3b & op13=0 & op0507=0 & rs5 & rt5 & Rdd5 & rdd5 & $(END_PACKET) { + tmp:8 = zext(rs5) * zext(rt5); + Rdd5 = rdd5 - tmp; + build EndPacket; +} + +# (v2,14) mpyu -- "Rxx32 -= mpyu ( Rs32.h , Rt32.h )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 1 0 0 1 1 s s s s s P P + t t t t t 0 1 1 x x x x x +# +# (v2,14) mpyu -- "Rxx32 -= mpyu ( Rs32.h , Rt32.l )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 1 0 0 1 1 s s s s s P P + t t t t t 0 1 0 x x x x x +# +# (v2,14) mpyu -- "Rxx32 -= mpyu ( Rs32.l , Rt32.h )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 1 0 0 1 1 s s s s s P P + t t t t t 0 0 1 x x x x x +# +# (v2,14) mpyu -- "Rxx32 -= mpyu ( Rs32.l , Rt32.l )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 1 0 0 1 1 s s s s s P P + t t t t t 0 0 0 x x x x x + +:mpyu-= Rdd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x33 & op13=0 & op7=0 & Rs5HL06 & Rt5HL05 & Rdd5 & rdd5 & $(END_PACKET) { + tmp:8 = zext(Rs5HL06) * zext(Rt5HL05); + Rdd5 = rdd5 - tmp; + build EndPacket; +} + +# (v2,14) mpyu -- "Rxx32 -= mpyu ( Rs32.h , Rt32.h ) :<<1" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 1 0 1 1 1 s s s s s P P + t t t t t 0 1 1 x x x x x +# +# (v2,14) mpyu -- "Rxx32 -= mpyu ( Rs32.h , Rt32.l ) :<<1" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 1 0 1 1 1 s s s s s P P + t t t t t 0 1 0 x x x x x +# +# (v2,14) mpyu -- "Rxx32 -= mpyu ( Rs32.l , Rt32.h ) :<<1" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 1 0 1 1 1 s s s s s P P + t t t t t 0 0 1 x x x x x +# +# (v2,14) mpyu -- "Rxx32 -= mpyu ( Rs32.l , Rt32.l ) :<<1" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 1 0 1 1 1 s s s s s P P + t t t t t 0 0 0 x x x x x + +:mpyu-=^":<<1" Rdd5,Rs5HL06,Rt5HL05 EndPacket is iclass=14 & op2127=0x37 & op13=0 & op7=0 & Rs5HL06 & Rt5HL05 & Rdd5 & rdd5 & $(END_PACKET) { + tmp:8 = zext(Rs5HL06) * zext(Rt5HL05); + Rdd5 = rdd5 - (tmp << 1); + build EndPacket; +} + +# (v2,7) mux -- "Rd32 = mux ( Pu4 , #s8x , #S8 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 1 1 0 1 u u I I I I I I I P P I i i i i i i i i d d d d d + +:mux Rd5,pu2324,Simm32_0512x,Simm8_1622_13 EndPacket is iclass=7 & op2527=5 & Rd5 & pu2324 & Simm32_0512x & Simm8_1622_13 & $(END_PACKET) { + if ((pu2324 & 1) != 0) goto ; + Rd5 = sext(Simm8_1622_13); + goto ; + + Rd5 = Simm32_0512x; + + build EndPacket; +} + +# (v2,7) mux -- "Rd32 = mux ( Pu4 , #s8x , Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 1 0 0 1 1 1 u u s s s s s P P 0 i i i i i i i i d d d d d + +:mux Rd5,pu2122,Simm32_0512x,rs5 EndPacket is iclass=7 & op2327=7 & op13=0 & Rd5 & pu2122 & Simm32_0512x & rs5 & $(END_PACKET) { + if ((pu2122 & 1) != 0) goto ; + Rd5 = rs5; + goto ; + + Rd5 = Simm32_0512x; + + build EndPacket; +} + +# (v2,7) mux -- "Rd32 = mux ( Pu4 , Rs32 , #s8x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 1 0 0 1 1 0 u u s s s s s P P 0 i i i i i i i i d d d d d + +:mux Rd5,pu2122,rs5,Simm32_0512x EndPacket is iclass=7 & op2327=6 & op13=0 & Rd5 & pu2122 & Simm32_0512x & rs5 & $(END_PACKET) { + if ((pu2122 & 1) != 0) goto ; + Rd5 = Simm32_0512x; + goto ; + + Rd5 = rs5; + + build EndPacket; +} + +# (v2,15) mux -- "Rd32 = mux ( Pu4 , Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 1 0 1 0 0 + + + s s s s s P P + t t t t t + u u d d d d d + +# Sleigh can't distinguish the two simplification cases when -l option is used with compiler +#:mux Rd5,pu0506,rs5,rt5 EndPacket is iclass=15 & op2127=0x20 & op13=0 & op7=0 & Rd5 & rd5=op1620 & rs5 & rt5 & pu0506 & $(END_PACKET) { +# if ((pu0506 & 1) == 0) goto ; +# Rd5 = rs5; +# goto ; +# +# build EndPacket; +#} +#:mux Rd5,pu0506,rs5,rt5 EndPacket is iclass=15 & op2127=0x20 & op13=0 & op7=0 & Rd5 & rd5=op0812 & rs5 & rt5 & pu0506 & $(END_PACKET) { +# if ((pu0506 & 1) != 0) goto ; +# Rd5 = rt5; +# goto ; +# +# build EndPacket; +#} + +:mux Rd5,pu0506,rs5,rt5 EndPacket is iclass=15 & op2127=0x20 & op13=0 & op7=0 & Rd5 & rs5 & rt5 & pu0506 & $(END_PACKET) { + if ((pu0506 & 1) != 0) goto ; + Rd5 = rt5; + goto ; + + Rd5 = rs5; + + build EndPacket; +} + +# (v2,8) neg -- "Rd32 = neg ( Rs32 ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 1 0 0 1 0 0 s s s s s P P + + + + + + 1 1 0 d d d d d + +:neg":sat" Rd5,rs5 EndPacket is iclass=0x8 & op2127=0x64 & op0513=0x06 & Rd5 & rs5 & $(END_PACKET) +{ + tmp:8 = -sext(rs5); + Rd5 = saturate32(tmp); + sat:1 = sborrow(0:4, rs5); + build EndPacket; + <> + $(OVF) = $(OVF) | sat; +} + +# (v2,8) neg -- "Rdd32 = neg ( Rss32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 0 0 0 1 0 + s s s s s P P + + + + + + 1 0 1 d d d d d + +:neg Rdd5,rss5 EndPacket is iclass=0x8 & op2127=0x04 & op0513=0x05 & Rdd5 & rss5 & $(END_PACKET) +{ + Rdd5 = -rss5; + build EndPacket; +} + +# (v4,6) nmi -- "nmi ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 0 1 0 0 0 1 1 s s s s s P P + + + + + + 0 1 0 + + + + + + +define pcodeop nmi; # TODO: Need to determine what is affected + +:nmi rs5 EndPacket is iclass=0x6 & op2127=0x23 & op0013=0x40 & rs5 & $(END_PACKET) +{ + nmi(rs5); + build EndPacket; +} + +# (v2,7) nop -- "nop" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 1 1 1 1 1 - - - - - - - - P P - - - - - - - - - - - - - - + +:nop EndPacket is iclass=0x7 & op2427=0xf & $(END_PACKET) { + build EndPacket; +} + +# (v2,8) normamt -- "Rd32 = normamt ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 1 0 0 0 0 0 s s s s s P P + + + + + + 1 1 1 d d d d d + +:normamt Rd5,rs5 EndPacket is iclass=0x8 & op2127=0x60 & op0513=0x07 & Rd5 & rs5 & $(END_PACKET) +{ + if (rs5 != 0) goto ; + Rd5 = 0; + goto ; + + Rd5 = countLeadingBits(rs5); + + build EndPacket; +} + +# (v4,8) normamt -- "Rd32 = normamt ( Rss32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 0 0 0 0 1 1 s s s s s P P + + + + + + 0 0 + d d d d d + +:normamt Rd5,rss5 EndPacket is iclass=0x8 & op2127=0x43 & op0513=0x0 & Rd5 & rss5 & $(END_PACKET) +{ + if (rss5 != 0) goto ; + Rd5 = 0; + goto ; + + Rd5 = countLeadingBits(rss5); + + build EndPacket; +} + +# (v2,6) not -- "Pd4 = not ( Ps4 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 1 0 1 1 1 1 0 0 - - s s P P 0 - - - - - - - - - - - d d + +:not Pd2,pu1617 EndPacket is iclass=6 & op2127=0x5e & op1820=0 & op0213=0 & pu1617 & Pd2 & $(END_PACKET) { + Pd2 = Pd2 & ~pu1617; # NOTE: Implemented as full byte logic instead of single-bit boolean logic + build EndPacket; +} + +# (v2,8) not -- "Rdd32 = not ( Rss32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 0 0 0 1 0 + s s s s s P P - - - - - - 1 0 0 d d d d d + +:not Rdd5,rss5 EndPacket is iclass=8 & op2127=0x04 & op0507=4 & Rdd5 & rss5 & $(END_PACKET) { + Rdd5 = ~rss5; + build EndPacket; +} + +# (v4,6) or -- "Pd4 = or ( Ps4 , and ( Pt4 , Pu4 ) )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 1 0 1 1 0 1 0 1 + + s s P P 0 - - - t t u u - - - - d d +# +# (v4,6) or -- "Pd4 = or ( Ps4 , and ( Pt4 , ! Pu4 ) )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 1 0 1 1 1 1 0 1 + + s s P P 0 - - - t t u u - - - - d d +# +# (v4,6) or -- "Pd4 = or ( Ps4 , or ( Pt4 , Pu4 ) )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 1 0 1 1 0 1 1 1 + + s s P P 0 - - - t t u u - - - - d d +# +# (v4,6) or -- "Pd4 = or ( Ps4 , or ( Pt4 , ! Pu4 ) )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 1 0 1 1 1 1 1 1 + + s s P P 0 - - - t t u u - - - - d d + +:or Pd2,pu1617,PredLogic_L21_S23_P0809_P0607 EndPacket is iclass=6 & op2427=0xb & op22=1 & op1820=4 & pu1617 & Pd2 & PredLogic_L21_S23_P0809_P0607 & $(END_PACKET) { + Pd2 = Pd2 & (pu1617 | PredLogic_L21_S23_P0809_P0607); + build EndPacket; +} + +# (v2,6) or -- "Pd4 = or ( Pt4 , Ps4 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 1 0 1 1 0 0 1 0 - - s s P P 0 - - - t t - - - - - - d d + +:or Pd2,pu0809,pu1617 EndPacket is iclass=6 & op2127=0x59 & op1820=0 & op1013=0 & op0207=0 & pu0809 & pu1617 & Pd2 & $(END_PACKET) { + Pd2 = Pd2 & (pu1617 | pu0809); + build EndPacket; +} + +# Pd=Pd ( simplification of Pd=or(Ps,Pt) ) +:assign Pd2,pu1617 EndPacket is iclass=6 & op2127=0x59 & op1820=0 & op1013=0 & op0207=0 & pu0809=op1617 & pu1617 & Pd2 & $(END_PACKET) { + Pd2 = Pd2 & pu1617; + build EndPacket; +} + +# (v2,6) or -- "Pd4 = or ( Pt4 , ! Ps4 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 1 0 1 1 1 1 1 0 - - s s P P 0 - - - t t - - - - - - d d + +:or Pd2,pu0809,NotPs2 EndPacket is iclass=6 & op2127=0x5f & op1820=0 & op1013=0 & op0207=0 & pu0809 & NotPs2 & Pd2 & $(END_PACKET) { + Pd2 = Pd2 & (NotPs2 | pu0809); + build EndPacket; +} + +# (v2,7) or -- "Rd32 = or ( Rs32 , #s10x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 1 0 1 1 0 1 0 i s s s s s P P i i i i i i i i i d d d d d + +:or Rd5,rs5,Simm32_21_0513x EndPacket is iclass=7 & op2227=0x1a & Rd5 & rs5 & Simm32_21_0513x & $(END_PACKET) { + Rd5 = rs5 | Simm32_21_0513x; + build EndPacket; +} + +# (v2,15) or -- "Rd32 = or ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 1 0 0 0 1 0 0 1 s s s s s P P - t t t t t - - - d d d d d + +:or Rd5,rs5,rt5 EndPacket is iclass=15 & op2127=0x09 & Rd5 & rs5 & rt5 & $(END_PACKET) { + Rd5 = rs5 | rt5; + build EndPacket; +} + +# (v4,15) or -- "Rd32 = or ( Rt32 , ~ Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 1 0 0 0 1 1 0 1 s s s s s P P - t t t t t - - - d d d d d + +:or Rd5,rt5,OnesCompRs5 EndPacket is iclass=15 & op2127=0x0d & Rd5 & OnesCompRs5 & rt5 & $(END_PACKET) { + Rd5 = rt5 | OnesCompRs5; + build EndPacket; +} + +# (v2,13) or -- "Rdd32 = or ( Rss32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 1 1 1 1 s s s s s P P - t t t t t 0 1 0 d d d d d + +:or Rdd5,rss5,rtt5 EndPacket is iclass=13 & op2127=0x1f & op0507=2 & Rdd5 & rss5 & rtt5 & $(END_PACKET) { + Rdd5 = rss5 | rtt5; + build EndPacket; +} + +# (v4,13) or -- "Rdd32 = or ( Rtt32 , ~ Rss32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 1 1 1 1 s s s s s P P - t t t t t 0 1 1 d d d d d + +:or Rdd5,rtt5,OnesCompRss5 EndPacket is iclass=13 & op2127=0x1f & op0507=3 & Rdd5 & OnesCompRss5 & rtt5 & $(END_PACKET) { + Rdd5 = rtt5 | OnesCompRss5; + build EndPacket; +} + +# (v4,14) or -- "Rx32 &= or ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 1 0 1 0 s s s s s P P + t t t t t + 0 1 x x x x x + +:or&= Rd5,rs5,rt5 EndPacket is iclass=0xe & op2127=0x7a & op13=0 & op0507=1 & rs5 & rt5 & rd5 & Rd5 & $(END_PACKET) +{ + Rd5 = rd5 & (rs5 | rt5); + build EndPacket; +} + +# (v4,13) or -- "Rx32 = or ( #u8x , asl ( Rx32 , #U5 ) )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 1 1 1 0 i i i x x x x x P P i I I I I I i i i 0 i 0 1 + +# +# (v4,13) or -- "Rx32 = or ( #u8x , lsr ( Rx32 , #U5 ) )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 1 1 1 0 i i i x x x x x P P i I I I I I i i i 1 i 0 1 + + +:or Rx5,Uimm32_2123_13_0507_03x,ShiftRx_D04_I0812 EndPacket is iclass=13 & op2427=14 & op0002=2 & Uimm32_2123_13_0507_03x & ShiftRx_D04_I0812 & Rx5 & $(END_PACKET) +{ + Rx5 = Uimm32_2123_13_0507_03x & ShiftRx_D04_I0812; + build EndPacket; +} + +# (v4,13) or -- "Rx32 = or ( Ru32 , and ( Rx32 , #s10x ) )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 1 0 1 0 0 1 i x x x x x P P i i i i i i i i i u u u u u + +AndRx_21_0513: "and("^rx5,Simm32_21_0513x^")" is rx5 & Simm32_21_0513x { + tmp:4 = rx5 & Simm32_21_0513x; + export tmp; +} + +:or Rx5,ru5,AndRx_21_0513 EndPacket is iclass=13 & op2227=0x29 & AndRx_21_0513 & Rx5 & ru5 & $(END_PACKET) +{ + Rx5 = ru5 | AndRx_21_0513; + build EndPacket; +} + +# (v4,14) or -- "Rx32 ^= or ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 1 1 1 0 s s s s s P P + t t t t t + 1 1 x x x x x + +:or"^=" Rd5,rs5,rt5 EndPacket is iclass=0xe & op2127=0x7e & op13=0 & op0507=3 & rs5 & rt5 & rd5 & Rd5 & $(END_PACKET) +{ + Rd5 = rd5 ^ (rs5 | rt5); + build EndPacket; +} + +# (v4,13) or -- "Rx32 |= or ( Rs32 , #s10x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 1 0 1 0 1 0 i s s s s s P P i i i i i i i i i x x x x x + +:or|= Rd5,rs5,Simm32_21_0513x EndPacket is iclass=13 & op2227=0x2a & Rd5 & rd5 & Simm32_21_0513x & rs5 & $(END_PACKET) { + Rd5 = rd5 | (rs5 | Simm32_21_0513x); + build EndPacket; +} + +# (v4,14) or -- "Rx32 |= or ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 1 1 1 0 s s s s s P P + t t t t t + 0 0 x x x x x + +:or|= Rd5,rs5,rt5 EndPacket is iclass=0xe & op2127=0x7e & op13=0 & op0507=0 & rs5 & rt5 & rd5 & Rd5 & $(END_PACKET) +{ + Rd5 = rd5 | rs5 | rt5; + build EndPacket; +} + +# (v2,15) or -- "if ( Pu4 ) Rd32 = or ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 1 1 0 0 1 + 0 1 s s s s s P P 0 t t t t t 0 u u d d d d d +# +# (v2,15) or -- "if ( ! Pu4 ) Rd32 = or ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 1 1 0 0 1 + 0 1 s s s s s P P 0 t t t t t 1 u u d d d d d +# +# (v2,15) or -- "if ( Pu4 .new ) Rd32 = or ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 1 1 0 0 1 + 0 1 s s s s s P P 1 t t t t t 0 u u d d d d d +# +# (v2,15) or -- "if ( ! Pu4 .new ) Rd32 = or ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 1 1 0 0 1 + 0 1 s s s s s P P 1 t t t t t 1 u u d d d d d + +:or^PuCond0506_N13_S07 rd5,rs5,rt5 EndPacket is iclass=15 & op2327=0x12 & op22=0 & op21=1 & PuCond0506_N13_S07 & rs5 & rt5 & rd5 & rd5_ & SetNRegRd5 & $(END_PACKET) { + build PuCond0506_N13_S07; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + rd5_ = rs5 | rt5; + + <> + if (ConditionReg == 0) goto ; + rd5 = rd5_; + +} + +# (v4,15) packhl -- "Rdd32 = packhl ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 1 0 1 0 1 1 + + s s s s s P P + t t t t t + + + d d d d d + +:packhl Rdd5,rs5,rt5 EndPacket is iclass=0xf & op2127=0x2c & op13=0 & op0507=0 & rs5 & rt5 & Rdd5 & $(END_PACKET) +{ + Rdd5 = (zext(rs5 & 0xff00) << 32) + (zext(rt5 & 0xff00) << 16) + (zext(rs5 & 0xff) << 8) + zext(rt5 & 0xff); + build EndPacket; +} + +# (v2,13) packhl -- "Rdd32 = packhl ( Rs32 , Rt32 ) :deprecated" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 1 0 0 + + 0 s s s s s P P + t t t t t + + + d d d d d + +:packhl^":deprecated" Rdd5,rs5,rt5 EndPacket is iclass=0xd & op2127=0x20 & op13=0 & op0507=0 & rs5 & rt5 & Rdd5 & $(END_PACKET) +{ + Rdd5 = (zext(rs5 & 0xff00) << 32) + (zext(rt5 & 0xff00) << 16) + (zext(rs5 & 0xff) << 8) + zext(rt5 & 0xff); + build EndPacket; +} + +# (v4,13) parity -- "Rd32 = parity ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 1 0 1 1 1 1 s s s s s P P + t t t t t + + + d d d d d + +define pcodeop parity; + +:parity Rd5,rs5,rt5 EndPacket is iclass=0xd & op2127=0x2f & op13=0 & op0507=0 & rs5 & rt5 & Rd5 & $(END_PACKET) +{ + Rd5 = parity(rs5,rt5); + build EndPacket; +} + +# (v2,13) parity -- "Rd32 = parity ( Rss32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 0 0 + + + s s s s s P P + t t t t t + + + d d d d d + +:parity Rd5,rss5,rtt5 EndPacket is iclass=0xd & op2127=0x0 & op13=0 & op0507=0 & rss5 & rtt5 & Rd5 & $(END_PACKET) +{ + Rd5 = parity(rss5,rtt5); + build EndPacket; +} + +# (v4,5) pause -- "pause ( #u10 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 1 0 1 0 0 0 1 - - - - i i P P - i i i i i - - - i i i - - + +define pcodeop pause; + +:pause Uimm10_1617_0812_0204 EndPacket is iclass=0x5 & op2127=0x22 & op1820=0 & op13=0 & op0507=0 & op0001=0 & Uimm10_1617_0812_0204 & $(END_PACKET) +{ + pause(Uimm10_1617_0812_0204); + build EndPacket; +} + +# unpause -- "unpause" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 1 0 1 1 1 1 1 1 - - - - - P P 0 1 - - - - 0 0 0 - - - - - + +define pcodeop unpause; + +:unpause EndPacket is iclass=0x5 & op2127=0x3f & op1620=0 & op0213=0x400 & op0001=0 & $(END_PACKET) +{ + unpause(); + build EndPacket; +} + +# pmemcpy -- "Rdd32 = pmemcpy ( Rx32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 1 0 0 1 1 1 1 t t t t t P P 0 x x x x x 0 0 0 d d d d d + +define pcodeop pmemcpy; + +:pmemcpy Rdd5,rt5,rss5 EndPacket is iclass=0x9 & op2127=0x4f & op13=0 & op0507=0 & rss5 & rt5 & Rdd5 & $(END_PACKET) +{ + Rdd5 = pmemcpy(rt5,rss5); + build EndPacket; +} + +# (v4,14) pmpyw -- "Rdd32 = pmpyw ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 0 1 0 1 0 s s s s s P P + t t t t t 1 1 1 d d d d d + +define pcodeop pmpyw; + +:pmpyw Rdd5,rs5,rt5 EndPacket is iclass=0xe & op2127=0x2a & op13=0 & op0507=7 & rs5 & rt5 & Rdd5 & $(END_PACKET) +{ + Rdd5 = pmpyw(rs5,rt5); + build EndPacket; +} + +# (v4,14) pmpyw -- "Rxx32 ^= pmpyw ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 1 1 0 0 1 s s s s s P P + t t t t t 1 1 1 x x x x x + +:pmpyw"^=" Rdd5,rs5,rt5 EndPacket is iclass=0xe & op2127=0x39 & op13=0 & op0507=7 & rs5 & rt5 & rdd5 & Rdd5 & $(END_PACKET) +{ + Rdd5 = rdd5 ^ pmpyw(rs5,rt5); + build EndPacket; +} + +# (v2,6) resume -- "resume ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 0 1 0 0 0 1 0 s s s s s P P + + + + + + 0 0 1 + + + + + + +# (v5,8) popcount -- "Rd32 = popcount ( Rss32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 0 0 0 0 1 1 s s s s s P P + + + + + + 0 1 1 d d d d d + +:popcount Rd5,rss5 EndPacket is iclass=8 & op2127=0x43 & op0513=0x03 & rss5 & Rd5 & $(END_PACKET) { + Rd5 = popcount(rss5); + build EndPacket; +} + +# (v68,10) release -- "release ( Rs32 ) :at" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 0 0 0 0 1 1 1 s s s s s P P 0 t t t t t - - 0 0 1 1 d d + +define pcodeop releaseAllThreads; +:release^":at" rs5 EndPacket is iclass=10 & op2127=0x07 & op13=0 & op0205=3 & rs5 & $(END_PACKET) { + releaseAllThreads(rs5); # release_at(rs5); # encoded rt5 and rd2 not used ?? +} + +# (v68,10) release -- "release ( Rs32 ) :st" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 0 0 0 0 1 1 1 s s s s s P P 0 t t t t t - - 1 0 1 1 d d + +define pcodeop releaseSameDomain; +:release^":st" rs5 EndPacket is iclass=10 & op2127=0x07 & op13=0 & op0205=0xb & rs5 & $(END_PACKET) { + releaseSameDomain(rs5); # release_st(rs5); # encoded rt5 and rd2 not used ?? +} + +# (v4,6) resume -- "resume ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 0 1 0 0 0 1 0 s s s s s P P + + + + + + 0 0 1 + + + + + + +define pcodeop resume; +:resume rs5 EndPacket is iclass=0x6 & op2127=0x22 & op0507=1 & rs5 & $(END_PACKET) +{ + resume(rs5); + build EndPacket; +} + +# (v4,8) round -- "Rd32 = round ( Rs32 , #u5 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 1 0 0 1 1 1 s s s s s P P 0 i i i i i 1 0 + d d d d d + +:round Rd5,rs5,Uimm8_0812 EndPacket is iclass=8 & op2127=0x67 & op13=0 & op0507=4 & Rd5 & rs5 & Uimm8_0812 & $(END_PACKET) { + Rd5 = roundArithmetic(rs5, Uimm8_0812); + build EndPacket; +} + +# (v4,8) round -- "Rd32 = round ( Rs32 , #u5 ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 1 0 0 1 1 1 s s s s s P P 0 i i i i i 1 1 + d d d d d + +:round":sat" Rd5,rs5,Uimm8_0812 EndPacket is iclass=0x8 & op2127=0x67 & op13=0 & op0507=6 & Uimm8_0812 & Rd5 & rs5 & $(END_PACKET) { + Rd5 = roundArithmeticSaturate(rs5, Uimm8_0812); + build EndPacket; +} + +# (v4,12) round -- "Rd32 = round ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 1 1 0 1 1 + s s s s s P P + t t t t t 1 0 + d d d d d + +:round Rd5,rs5,rt5 EndPacket is iclass=12 & op2127=0x36 & op13=0 & op0507=4 & Rd5 & rs5 & rt5 & $(END_PACKET) { + Rd5 = roundArithmetic(rs5, rt5); + build EndPacket; +} + +# (v4,12) round -- "Rd32 = round ( Rs32 , Rt32 ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 1 1 0 1 1 + s s s s s P P + t t t t t 1 1 + d d d d d + +:round":sat" Rd5,rs5,rt5 EndPacket is iclass=12 & op2127=0x36 & op13=0 & op0507=6 & rt5 & Rd5 & rs5 & $(END_PACKET) { + Rd5 = roundArithmeticSaturate(rs5, rt5); + build EndPacket; +} + +# (v5,8) round -- "Rd32 = round ( Rss32 ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 0 0 0 1 1 0 s s s s s P P + + + + + + 0 0 1 d d d d d + +define pcodeop roundArithmeticPSat; +:round":sat" Rd5,rss5 EndPacket is iclass=8 & op2127=0x46 & op0513=1 & Rd5 & rss5 & $(END_PACKET) { + Rd5 = roundArithmeticPSat(rss5); + build EndPacket; +} + +# (v2,5) rte -- "rte" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 1 0 1 1 1 1 1 1 + + + + + P P 0 0 + + + + 0 0 0 + + + + + + +:rte EndPacket is iclass=5 & op2127=0x3f & op1620=0 & op0013=0 & $(END_PACKET) { + # Treat as return + dest:4 = $(ELR); + build EndPacket; + <> + return [dest]; +} + + +# (v2,8) sat -- "Rd32 = sat ( Rss32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 0 0 0 1 1 0 s s s s s P P + + + + + + 0 0 + d d d d d + +:sat Rd5,rss5 EndPacket is iclass=8 & op2127=0x46 & op0513=0 & Rd5 & rss5 & $(END_PACKET) { + Rd5 = saturate32(rss5); + sat:1 = (rss5 s< 0xffffffff80000000) || (rss5 s> 0x7fffffff); + build EndPacket; + <> + $(OVF) = $(OVF) | sat; +} + +# (v2,8) satb -- "Rd32 = satb ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 1 0 0 1 1 0 s s s s s P P + + + + + + 1 1 1 d d d d d + +:satb Rd5,rs5 EndPacket is iclass=8 & op2127=0x66 & op0513=7 & Rd5 & rs5 & $(END_PACKET) { + byte:1 = saturate8(rs5); + Rd5 = sext(byte); + sat:1 = (rs5 s< 0xffffff80) || (rs5 s> 0x7f); + build EndPacket; + <> + $(OVF) = $(OVF) | sat; +} + +# (v2,8) sath -- "Rd32 = sath ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 1 0 0 1 1 0 s s s s s P P + + + + + + 1 0 0 d d d d d + +:sath Rd5,rs5 EndPacket is iclass=8 & op2127=0x66 & op0513=4 & Rd5 & rs5 & $(END_PACKET) { + half:2 = saturate16(rs5); + Rd5 = sext(half); + sat:1 = (rs5 s< 0xffff8000) || (rs5 s> 0x7fff); + build EndPacket; + <> + $(OVF) = $(OVF) | sat; +} + +# (v2,8) satub -- "Rd32 = satub ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 1 0 0 1 1 0 s s s s s P P + + + + + + 1 1 0 d d d d d + +:satub Rd5,rs5 EndPacket is iclass=8 & op2127=0x66 & op0513=6 & Rd5 & rs5 & $(END_PACKET) { + byte:1 = usaturate8(rs5); + Rd5 = zext(byte); + sat:1 = (rs5 > 0x7f); + build EndPacket; + <> + $(OVF) = $(OVF) | sat; +} + +# (v2,8) satuh -- "Rd32 = satuh ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 1 0 0 1 1 0 s s s s s P P + + + + + + 1 0 1 d d d d d + +:satuh Rd5,rs5 EndPacket is iclass=8 & op2127=0x66 & op0513=5 & Rd5 & rs5 & $(END_PACKET) { + half:2 = usaturate16(rs5); + Rd5 = zext(half); + sat:1 = (rs5 > 0x7fff); + build EndPacket; + <> + $(OVF) = $(OVF) | sat; +} + +# (v2,8) setbit -- "Rd32 = setbit ( Rs32 , #u5 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 1 0 0 1 1 0 s s s s s P P 0 i i i i i 0 0 0 d d d d d + +:setbit Rd5,rs5,Uimm8_0812 EndPacket is iclass=8 & op2127=0x66 & op13=0 & op0507=0 & Rd5 & rs5 & Uimm8_0812 & $(END_PACKET) { + mask:4 = 1 << Uimm8_0812; + Rd5 = rs5 | mask; + build EndPacket; +} + +# (v2,12) setbit -- "Rd32 = setbit ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 1 1 0 1 0 + s s s s s P P + t t t t t 0 0 + d d d d d + +:setbit Rd5,rs5,rt5 EndPacket is iclass=12 & op2127=0x34 & op13=0 & op0507=0 & Rd5 & rs5 & rt5 & $(END_PACKET) { + mask:4 = 1 << rt5; + Rd5 = rs5 | mask; + build EndPacket; +} + +# (v4,6) setimask -- "setimask ( Pt4 , Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 0 1 0 0 1 0 0 s s s s s P P + + + + t t 0 0 0 + + + + + + +define pcodeop setimask; # TODO: Determine what is affected by this instruction + +:setimask pu0809,rs5 EndPacket is iclass=6 & op2127=0x24 & op1013=0 & op0007=0 & pu0809 & rs5 & $(END_PACKET) { + setimask(pu0809,rs5); + build EndPacket; +} + +# (v66,6) or -- "setprio ( Pt4 , Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 0 1 0 0 1 0 0 s s s s s P P - - - - t t 0 0 1 - - - - - + +define pcodeop setprio; +:setprio pu0809,rs5 EndPacket is iclass=6 & op2127=0x24 & op0507=1 & pu0809 & rs5 & $(END_PACKET) { + setprio(pu0809, rs5); + build EndPacket; +} + +# (v2,12) shuffeb -- "Rdd32 = shuffeb ( Rss32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 0 0 1 0 0 + s s s s s P P + t t t t t 0 1 + d d d d d + +define pcodeop shuffeb; + +:shuffeb Rdd5,rss5,rtt5 EndPacket is iclass=12 & op2127=0x08 & op13=0 & op0507=2 & Rdd5 & rss5 & rtt5 & $(END_PACKET) { + Rdd5 = shuffeb(rss5,rtt5); + build EndPacket; +} + +# (v2,12) shuffeh -- "Rdd32 = shuffeh ( Rss32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 0 0 1 0 0 + s s s s s P P + t t t t t 1 1 + d d d d d + +define pcodeop shuffeh; + +:shuffeh Rdd5,rss5,rtt5 EndPacket is iclass=12 & op2127=0x08 & op13=0 & op0507=6 & Rdd5 & rss5 & rtt5 & $(END_PACKET) { + Rdd5 = shuffeh(rss5,rtt5); + build EndPacket; +} + +# (v2,12) shuffob -- "Rdd32 = shuffob ( Rtt32 , Rss32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 0 0 1 0 0 + s s s s s P P + t t t t t 1 0 + d d d d d + +define pcodeop shuffob; + +:shuffob Rdd5,rss5,rtt5 EndPacket is iclass=12 & op2127=0x08 & op13=0 & op0507=4 & Rdd5 & rss5 & rtt5 & $(END_PACKET) { + Rdd5 = shuffob(rss5,rtt5); + build EndPacket; +} + +# (v2,12) shuffoh -- "Rdd32 = shuffoh ( Rtt32 , Rss32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 0 0 1 1 0 + s s s s s P P + t t t t t 0 0 + d d d d d + +define pcodeop shuffoh; + +:shuffoh Rdd5,rss5,rtt5 EndPacket is iclass=12 & op2127=0x0c & op13=0 & op0507=0 & Rdd5 & rss5 & rtt5 & $(END_PACKET) { + Rdd5 = shuffoh(rss5,rtt5); + build EndPacket; +} + +# (v4,6) siad -- "siad ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 0 1 0 0 1 0 0 s s s s s P P + + + + + + 0 1 1 + + + + + + +:siad rs5 EndPacket is iclass=6 & op2127=0x24 & op0013=0x60 & rs5 & $(END_PACKET) { + S22 = S22 | rs5; + build EndPacket; +} + +# (v2,6) sp1loop0 -- "p3 = sp1loop0 ( #r7:2x , #U10 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 1 0 0 1 1 0 1 I I I I I P P - i i i i i I I I i i - I I + +:sp1loop0 P3,LoopRelMem7x,LoopUimm10 EndPacket is iclass=6 & op2127=0x4d & op13=0 & op2=0 & P3 & LoopRelMem7x & LoopRelAddr7x & LoopUimm10 & $(END_PACKET) [ useLoopCfg=1; ] { + SA0_ = LoopRelAddr7x; + LC0_ = LoopUimm10; + build EndPacket; + <> + SA0 = SA0_; + LC0 = LC0_; + $(LPCFG) = 1; + P3 = 0; +} + +# (v2,6) sp1loop0 -- "p3 = sp1loop0 ( #r7:2x , Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 0 0 0 0 1 0 1 s s s s s P P - i i i i i - - - i i - - - + +:sp1loop0 P3,LoopRelMem7x,rs5 EndPacket is iclass=6 & op2127=5 & op13=0 & op0507=0 & op0002=0 & P3 & LoopRelMem7x & LoopRelAddr7x & rs5 & $(END_PACKET) [ useLoopCfg=1; ] { + SA0_ = LoopRelAddr7x; + LC0_ = rs5; + build EndPacket; + <> + SA0 = SA0_; + LC0 = LC0_; + $(LPCFG) = 1; + P3 = 0; +} + +# (v2,6) sp2loop0 -- "p3 = sp2loop0 ( #r7:2x , #U10 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 1 0 0 1 1 1 0 I I I I I P P - i i i i i I I I i i - I I + +:sp2loop0 P3,LoopRelMem7x,LoopUimm10 EndPacket is iclass=6 & op2127=0x4e & op13=0 & op2=0 & P3 & LoopRelMem7x & LoopRelAddr7x & LoopUimm10 & $(END_PACKET) [ useLoopCfg=1; ] { + SA0_ = LoopRelAddr7x; + LC0_ = LoopUimm10; + build EndPacket; + <> + SA0 = SA0_; + LC0 = LC0_; + $(LPCFG) = 2; + P3 = 0; +} + +# (v2,6) sp2loop0 -- "p3 = sp2loop0 ( #r7:2x , Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 0 0 0 0 1 1 0 s s s s s P P - i i i i i - - - i i - - - + +:sp2loop0 P3,LoopRelMem7x,rs5 EndPacket is iclass=6 & op2127=6 & op13=0 & op0507=0 & op0002=0 & P3 & LoopRelMem7x & LoopRelAddr7x & rs5 & $(END_PACKET) [ useLoopCfg=1; ] { + SA0_ = LoopRelAddr7x; + LC0_ = rs5; + build EndPacket; + <> + SA0 = SA0_; + LC0 = LC0_; + $(LPCFG) = 2; + P3 = 0; +} + +# (v2,6) sp3loop0 -- "p3 = sp3loop0 ( #r7:2x , #U10 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 1 0 0 1 1 1 1 I I I I I P P - i i i i i I I I i i - I I + +:sp3loop0 P3,LoopRelMem7x,LoopUimm10 EndPacket is iclass=6 & op2127=0x4f & op13=0 & op2=0 & P3 & LoopRelMem7x & LoopRelAddr7x & LoopUimm10 & $(END_PACKET) [ useLoopCfg=1; ] { + SA0_ = LoopRelAddr7x; + LC0_ = LoopUimm10; + build EndPacket; + <> + SA0 = SA0_; + LC0 = LC0_; + $(LPCFG) = 3; + P3 = 0; +} + +# (v2,6) sp3loop0 -- "p3 = sp3loop0 ( #r7:2x , Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 0 0 0 0 1 1 1 s s s s s P P - i i i i i - - - i i - - - + +:sp3loop0 P3,LoopRelMem7x,rs5 EndPacket is iclass=6 & op2127=7 & op13=0 & op0507=0 & op0002=0 & P3 & LoopRelMem7x & LoopRelAddr7x & rs5 & $(END_PACKET) [ useLoopCfg=1; ] { + SA0_ = LoopRelAddr7x; + LC0_ = rs5; + build EndPacket; + <> + SA0 = SA0_; + LC0 = LC0_; + $(LPCFG) = 3; + P3 = 0; +} + +# (v2,6) start -- "start ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 0 1 0 0 0 1 1 s s s s s P P - - - - - - 0 0 1 - - - - - + +define pcodeop start; + +:start rs5 EndPacket is iclass=6 & op2127=0x23 & op0507=1 & rs5 & packetOffset=0 & $(END_PACKET) { # solo instruction + start(rs5); # resets threads specified by rs5 + build EndPacket; +} + +# (v2,6) stop -- "stop ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 0 1 0 0 0 1 1 s s s s s P P - - - - - - 0 0 0 - - - - - + +define pcodeop stop; + +:stop rs5 EndPacket is iclass=6 & op2127=0x23 & op0507=0 & rs5 & packetOffset=0 & $(END_PACKET) { # solo instruction + build EndPacket; + <> + stop(rs5); # cause calling thread to enter stop mode + goto inst_start; # we loop on instruction to simulate but this may not emulate well +} + +# (v2,13) sub -- "Rd32 = sub ( Rt32.h , Rs32.h ) :sat :<<16" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 1 0 1 0 1 1 s s s s s P P + t t t t t 1 1 1 d d d d d +# +# (v2,13) sub -- "Rd32 = sub ( Rt32.l , Rs32.h ) :sat :<<16" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 1 0 1 0 1 1 s s s s s P P + t t t t t 1 0 1 d d d d d +# +# (v2,13) sub -- "Rd32 = sub ( Rt32.h , Rs32.l ) :sat :<<16" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 1 0 1 0 1 1 s s s s s P P + t t t t t 1 1 0 d d d d d +# +# (v2,13) sub -- "Rd32 = sub ( Rt32.l , Rs32.l ) :sat :<<16" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 1 0 1 0 1 1 s s s s s P P + t t t t t 1 0 0 d d d d d + +:sub^":sat:<<16" Rd5,Rt5HL06,Rs5HL05 EndPacket is iclass=0xd & op2127=0x2b & op13=0 & op7=1 & Rs5HL05 & Rt5HL06 & Rd5 & $(END_PACKET) +unimpl + +# (v2,13) sub -- "Rd32 = sub ( Rt32.l , Rs32.h )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 1 0 1 0 0 1 s s s s s P P + t t t t t 0 1 + d d d d d +# +# (v2,13) sub -- "Rd32 = sub ( Rt32.l , Rs32.l )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 1 0 1 0 0 1 s s s s s P P + t t t t t 0 0 + d d d d d + +:sub Rd5,rt5L,Rs5HL06 EndPacket is iclass=0xd & op2127=0x29 & op13=0 & op7=0 & op5=0 & rt5L & Rs5HL06 & Rd5 & $(END_PACKET) +{ + Rd5 = sext(rt5L - Rs5HL06); + build EndPacket; +} + +# (v2,13) sub -- "Rd32 = sub ( Rt32.h , Rs32.h ) :<<16" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 1 0 1 0 1 1 s s s s s P P + t t t t t 0 1 1 d d d d d +# +# (v2,13) sub -- "Rd32 = sub ( Rt32.h , Rs32.l ) :<<16" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 1 0 1 0 1 1 s s s s s P P + t t t t t 0 1 0 d d d d d +# +# (v2,13) sub -- "Rd32 = sub ( Rt32.l , Rs32.h ) :<<16" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 1 0 1 0 1 1 s s s s s P P + t t t t t 0 0 1 d d d d d +# +# (v2,13) sub -- "Rd32 = sub ( Rt32.l , Rs32.l ) :<<16" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 1 0 1 0 1 1 s s s s s P P + t t t t t 0 0 0 d d d d d + +:sub^":<<16" Rd5,Rt5HL06,Rs5HL05 EndPacket is iclass=0xd & op2127=0x2b & op13=0 & op7=0 & Rs5HL05 & Rt5HL06 & Rd5 & $(END_PACKET) +{ + Rd5 = zext(Rt5HL06 - Rs5HL05) << 16; + build EndPacket; +} + +# (v2,13) sub -- "Rd32 = sub ( Rt32.l , Rs32.h ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 1 0 1 0 0 1 s s s s s P P + t t t t t 1 1 + d d d d d +# +# (v2,13) sub -- "Rd32 = sub ( Rt32.l , Rs32.l ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 1 0 1 0 0 1 s s s s s P P + t t t t t 1 0 + d d d d d + +:sub^":sat" Rd5,rt5L,Rs5HL06 EndPacket is iclass=0xd & op2127=0x29 & rs5 & op13=0 & op7=1 & op5=0 & rt5L & Rs5HL06 & Rd5 & $(END_PACKET) +{ + subSat16(Rd5, rt5L, Rs5HL06); + sat:1 = sborrow(rt5L, Rs5HL06); + build EndPacket; + <> + $(OVF) = $(OVF) | sat; +} + +# (v2,7) sub -- "Rd32 = sub ( #s10x , Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 1 0 1 1 0 0 1 i s s s s s P P i i i i i i i i i d d d d d + +:sub Rd5,Simm32_21_0513x,rs5 EndPacket is iclass=0x7 & op2227=0x19 & rs5 & Rd5 & Simm32_21_0513x & $(END_PACKET) +{ + Rd5 = Simm32_21_0513x - rs5; + build EndPacket; +} + +# Special case for sub(#-1,Rs) +:not Rd5,rs5 EndPacket is iclass=0x7 & op2227=0x19 & s21=1 & i0513=0x1ff & immexted=0 & rs5 & Rd5 & $(END_PACKET) +{ + Rd5 = ~rs5; + build EndPacket; +} + +# (v2,15) sub -- "Rd32 = sub ( Rt32 , Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 1 0 0 1 1 0 0 1 s s s s s P P + t t t t t + + + d d d d d + +:sub Rd5,rt5,rs5 EndPacket is iclass=15 & op2127=0x19 & op13=0 & op0507=0 & rs5 & rt5 & Rd5 & $(END_PACKET) +{ + Rd5 = rt5 - rs5; + build EndPacket; +} + +# (v4,15) sub -- "Rd32 = sub ( Rt32 , Rs32 ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 1 0 1 1 0 1 1 0 s s s s s P P + t t t t t + + + d d d d d + +:sub":sat" Rd5,rt5,rs5 EndPacket is iclass=15 & op2127=0x36 & op13=0 & op0507=0 & rs5 & rt5 & Rd5 & $(END_PACKET) { + subSat32(Rd5, rt5, rs5); + sat:1 = sborrow(rt5, rs5); + build EndPacket; + <> + $(OVF) = $(OVF) | sat; +} + +# (v2,13) sub -- "Rd32 = sub ( Rt32 , Rs32 ) :sat :deprecated" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 1 0 1 1 0 0 s s s s s P P + t t t t t 1 + + d d d d d + +:sub":sat:deprecated" Rd5,rt5,rs5 EndPacket is iclass=13 & op2127=0x2c & op13=0 & op0507=4 & rs5 & rt5 & Rd5 & $(END_PACKET) { + subSat32(Rd5, rt5, rs5); + sat:1 = sborrow(rt5, rs5); + build EndPacket; + <> + $(OVF) = $(OVF) | sat; +} + +# (v4,12) sub -- "Rdd32 = sub ( Rss32 , Rtt32 , Px4 ) :carry" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 0 1 0 1 1 1 s s s s s P P + t t t t t + x x d d d d d + +:sub":carry" Rdd5,rss5,rtt5,pu0506 EndPacket is iclass=12 & op2127=0x17 & op13=0 & op7=0 & Rdd5 & rss5 & rtt5 & pu0506 & pu0506_ & $(END_PACKET) { + prevCarry:8 = zext(pu0506); + pu0506_ = (rss5 < rtt5) | carry(rtt5,prevCarry); # compute new carry + Rdd5 = rss5 - rtt5 - prevCarry; + build EndPacket; + <> + pu0506 = pu0506_; +} + +# (v2,13) sub -- "Rdd32 = sub ( Rtt32 , Rss32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 1 0 0 1 s s s s s P P + t t t t t 1 1 1 d d d d d + +:sub Rdd5,rtt5,rss5 EndPacket is iclass=0xd & op2127=0x19 & rss5 & op13=0 & rtt5 & op0507=0x7 & Rdd5 & $(END_PACKET) +{ + Rdd5 = rtt5 - rss5; + build EndPacket; +} + +# (v2,14) sub -- "Rx32 += sub ( Rt32 , Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 1 0 0 0 s s s s s P P + t t t t t + 1 1 x x x x x + +:sub+= Rd5,rt5,rs5 EndPacket is iclass=0xe & op2127=0x78 & rs5 & op13=0 & op0507=0x3 & rt5 & rd5 & Rd5 & $(END_PACKET) +{ + Rd5 = rd5 + (rt5 - rs5); + build EndPacket; +} + +# (v4,13) sub -- "Rx32 = sub ( #u8x , asl ( Rx32 , #U5 ) )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 1 1 1 0 i i i x x x x x P P i I I I I I i i i 0 i 1 1 + +# +# (v4,13) sub -- "Rx32 = sub ( #u8x , lsr ( Rx32 , #U5 ) )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 1 1 1 0 i i i x x x x x P P i I I I I I i i i 1 i 1 1 + + +:sub Rx5,Uimm32_2123_13_0507_03x,ShiftRx_D04_I0812 EndPacket is iclass=13 & op2427=14 & op0002=6 & Uimm32_2123_13_0507_03x & ShiftRx_D04_I0812 & Rx5 & $(END_PACKET) +{ + Rx5 = Uimm32_2123_13_0507_03x - ShiftRx_D04_I0812; + build EndPacket; +} + +# (v2,15) sub -- "if ( Pu4 ) Rd32 = sub ( Rt32 , Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 1 1 0 1 1 0 + 1 s s s s s P P 0 t t t t t 0 u u d d d d d +# +# (v2,15) sub -- "if ( ! Pu4 ) Rd32 = sub ( Rt32 , Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 1 1 0 1 1 0 + 1 s s s s s P P 0 t t t t t 1 u u d d d d d +# +# (v2,15) sub -- "if ( Pu4 .new ) Rd32 = sub ( Rt32 , Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 1 1 0 1 1 0 + 1 s s s s s P P 1 t t t t t 0 u u d d d d d +# +# (v2,15) sub -- "if ( ! Pu4 .new ) Rd32 = sub ( Rt32 , Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 1 1 0 1 1 0 + 1 s s s s s P P 1 t t t t t 1 u u d d d d d + +:sub^PuCond0506_N13_S07 rd5,rt5,rs5 EndPacket is iclass=15 & op2327=0x16 & op22=0 & op21=1 & PuCond0506_N13_S07 & rs5 & rt5 & rd5 & rd5_ & SetNRegRd5 & $(END_PACKET) { + build PuCond0506_N13_S07; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + rd5_ = rt5 - rs5; + + <> + if (ConditionReg == 0) goto ; + rd5 = rd5_; + +} + +# (v2,6) swi -- "swi ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 0 1 0 0 0 0 0 s s s s s P P + + + + + + 0 0 0 + + + + + + +define pcodeop swi; + +:swi rs5 EndPacket is iclass=6 & op2127=0x20 & op0013=0x00 & rs5 & $(END_PACKET) { + swi(rs5); + build EndPacket; +} + +# (v2,8) swiz -- "Rd32 = swiz ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 1 0 0 1 0 0 s s s s s P P + + + + + + 1 1 1 d d d d d + +define pcodeop swizzle; + +:swiz Rd5,rs5 EndPacket is iclass=8 & op2127=0x64 & op0513=0x07 & rs5 & Rd5 & $(END_PACKET) { + Rd5 = swizzle(rs5); + build EndPacket; +} + +# (v2,7) sxtb -- "Rd32 = sxtb ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 1 0 0 0 0 1 0 1 s s s s s P P 0 + + + + + + + + d d d d d + +:sxtb Rd5,rs5 EndPacket is iclass=7 & op2127=0x05 & op0513=0 & rs5 & Rd5 & $(END_PACKET) +{ + Rd5 = sext(rs5:1); + build EndPacket; +} + +# (v4,7) sxtb -- "if ( Pu4 ) Rd32 = sxtb ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 1 0 0 0 0 1 0 1 s s s s s P P 1 + 0 0 u u + + + d d d d d +# +# (v4,7) sxtb -- "if ( ! Pu4 ) Rd32 = sxtb ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 1 0 0 0 0 1 0 1 s s s s s P P 1 + 1 0 u u + + + d d d d d +# +# (v4,7) sxtb -- "if ( Pu4 .new ) Rd32 = sxtb ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 1 0 0 0 0 1 0 1 s s s s s P P 1 + 0 1 u u + + + d d d d d +# +# (v4,7) sxtb -- "if ( ! Pu4 .new ) Rd32 = sxtb ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 1 0 0 0 0 1 0 1 s s s s s P P 1 + 1 1 u u + + + d d d d d + +:sxtb^PuCond0809_N10_S11 rd5,rs5 EndPacket is iclass=7 & op2127=0x05 & op1213=2 & op0507=0 & rs5 & rd5 & rd5_ & SetNRegRd5 & PuCond0809_N10_S11 & $(END_PACKET) +{ + build PuCond0809_N10_S11; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + rd5_ = sext(rs5:1); + + <> + if (ConditionReg == 0) goto ; + rd5 = rd5_; + +} + +# (v2,7) sxth -- "Rd32 = sxth ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 1 0 0 0 0 1 1 1 s s s s s P P 0 + + + + + + + + d d d d d + +:sxth Rd5,rs5 EndPacket is iclass=7 & op2127=0x07 & op0513=0 & rs5 & Rd5 & $(END_PACKET) +{ + Rd5 = sext(rs5:2); + build EndPacket; +} + +# (v4,7) sxth -- "if ( Pu4 ) Rd32 = sxth ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 1 0 0 0 0 1 1 1 s s s s s P P 1 + 0 0 u u + + + d d d d d +# +# (v4,7) sxth -- "if ( ! Pu4 ) Rd32 = sxth ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 1 0 0 0 0 1 1 1 s s s s s P P 1 + 1 0 u u + + + d d d d d +# +# (v4,7) sxth -- "if ( Pu4 .new ) Rd32 = sxth ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 1 0 0 0 0 1 1 1 s s s s s P P 1 + 0 1 u u + + + d d d d d +# +# (v4,7) sxth -- "if ( ! Pu4 .new ) Rd32 = sxth ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 1 0 0 0 0 1 1 1 s s s s s P P 1 + 1 1 u u + + + d d d d d + +:sxth^PuCond0809_N10_S11 rd5,rs5 EndPacket is iclass=7 & op2127=0x07 & op1213=2 & op0507=0 & rs5 & rd5 & rd5_ & SetNRegRd5 & PuCond0809_N10_S11 & $(END_PACKET) +{ + build PuCond0809_N10_S11; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + rd5_ = sext(rs5:2); + + <> + if (ConditionReg == 0) goto ; + rd5 = rd5_; + +} + +# (v2,8) sxtw -- "Rdd32 = sxtw ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 1 0 0 0 1 + s s s s s P P + + + + + + 0 0 + d d d d d + +:sxtw Rdd5,rs5 EndPacket is iclass=8 & op2127=0x22 & op0513=0 & rs5 & Rdd5 & $(END_PACKET) +{ + Rdd5 = sext(rs5); + build EndPacket; +} + +# (v2,10) syncht -- "syncht" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 1 0 0 0 0 1 0 - - - - - P P - - - - - - - - - - - - - - + +define pcodeop syncht; + +:syncht EndPacket is iclass=10 & op2127=0x42 & $(END_PACKET) { + syncht(); + build EndPacket; +} + +# (v2,8) tableidxb -- "Rx32 = tableidxb ( Rs32 , #u4 , #S6 ) :raw" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 1 1 1 0 0 i s s s s s P P I I I I I I i i i x x x x x + +:tableidxb^":raw" Rd5,rs5,Uimm8_21_0507,Simm8_0813 EndPacket is iclass=8 & op2227=0x1c & rs5 & Uimm8_21_0507 & Simm8_0813 & Rd5 & rd5 & $(END_PACKET) { + local width = Uimm8_21_0507; + local offs = Simm8_0813; + fieldMask:4 = (-1 << width); + tmp:4 = rd5 & fieldMask; # clear dest field + src:4 = (rs5 >> offs) & (~fieldMask); + Rd5 = tmp | src; + build EndPacket; +} + +# (v2,8) tableidxd -- "Rx32 = tableidxd ( Rs32 , #u4 , #S6 ) :raw" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 1 1 1 1 1 i s s s s s P P I I I I I I i i i x x x x x + +:tableidxd^":raw" Rd5,rs5,Uimm8_21_0507,Simm8_0813 EndPacket is iclass=8 & op2227=0x1f & rs5 & Uimm8_21_0507 & Simm8_0813 & Rd5 & rd5 & $(END_PACKET) { + local width = Uimm8_21_0507; + local offs = Simm8_0813 + 3; + fieldMask:4 = (-1 << width); + tmp:4 = rd5 & (fieldMask << 3); # clear dest field + src:4 = ((rs5 & (~fieldMask << offs)) >> offs) << 3; + Rd5 = tmp | src; + build EndPacket; +} + +# (v2,8) tableidxh -- "Rx32 = tableidxh ( Rs32 , #u4 , #S6 ) :raw" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 1 1 1 0 1 i s s s s s P P I I I I I I i i i x x x x x + +:tableidxh^":raw" Rd5,rs5,Uimm8_21_0507,Simm8_0813 EndPacket is iclass=8 & op2227=0x1d & rs5 & Uimm8_21_0507 & Simm8_0813 & Rd5 & rd5 & $(END_PACKET) { + local width = Uimm8_21_0507; + local offs = Simm8_0813 + 1; + fieldMask:4 = (-1 << width); + tmp:4 = rd5 & (fieldMask << 1); # clear dest field + src:4 = ((rs5 & (~fieldMask << offs)) >> offs) << 1; + Rd5 = tmp | src; + build EndPacket; +} + +# (v2,8) tableidxw -- "Rx32 = tableidxw ( Rs32 , #u4 , #S6 ) :raw" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 1 1 1 1 0 i s s s s s P P I I I I I I i i i x x x x x + +:tableidxw^":raw" Rd5,rs5,Uimm8_21_0507,Simm8_0813 EndPacket is iclass=8 & op2227=0x1e & rs5 & Uimm8_21_0507 & Simm8_0813 & Rd5 & rd5 & $(END_PACKET) { + local width = Uimm8_21_0507; + local offs = Simm8_0813 + 2; + fieldMask:4 = (-1 << width); + tmp:4 = rd5 & (fieldMask << 2); # clear dest field + src:4 = ((rs5 & (~fieldMask << offs)) >> offs) << 2; + Rd5 = tmp | src; + build EndPacket; +} + +# (v65,6) tlbinvasid -- "tlbinvasid( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 1 1 0 0 1 0 1 s s s s s P P + + + + + + + + + + + + + + + +define pcodeop tlbinvasid; + +:tlbinvasid rs5 EndPacket is iclass=6 & op2127=0x65 & rs5 & $(END_PACKET) { + tlbinvasid(rs5); + build EndPacket; +} + +# (v4,6) tlblock -- "tlblock" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 1 1 0 0 0 0 1 + + + + + P P + + + + + + 0 0 1 + + + + + + +define pcodeop tlblock; + +:tlblock EndPacket is iclass=6 & op2127=0x61 & op1620=0 & op0013=0x20 & $(END_PACKET) { + tlblock(); + build EndPacket; +} + +# (v4,13) tlbmatch -- "Pd4 = tlbmatch ( Rss32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 0 0 + + s s s s s P P 1 t t t t t 0 1 1 + + + d d + +define pcodeop tlbmatch; + +:tlbmatch Pd2,rss5,rt5 EndPacket is iclass=13 & op2127=0x10 & op13=1 & op0207=0x18 & Pd2 & rss5 & rt5 & $(END_PACKET) { + Pd2 = tlbmatch(rss5,rt5); + build EndPacket; +} + +# (v65,6) tlboc -- "Rd32 = tlboc( Rss32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 1 1 0 0 1 1 1 s s s s s P P + + + + + + + + + d d d d d + +define pcodeop tlboc; + +:tlboc Rd5,rss5 EndPacket is iclass=6 & op2127=0x67 & Rd5 & rss5 & $(END_PACKET) { + Rd5 = tlboc(rss5); + build EndPacket; +} + +# (v2,6) tlbp -- "Rd32 = tlbp ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 1 1 0 0 1 0 0 s s s s s P P + + + + + + + + + d d d d d + +define pcodeop tlbp; + +:tlbp Rd5,rs5 EndPacket is iclass=6 & op2127=0x64 & op0513=0 & Rd5 & rs5 & $(END_PACKET) { + Rd5 = tlbp(rs5); + build EndPacket; +} + +# (v2,6) tlbr -- "Rdd32 = tlbr ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 1 1 0 0 0 1 0 s s s s s P P + + + + + + + + + d d d d d + +define pcodeop tlbr; + +:tlbr Rdd5,rs5 EndPacket is iclass=6 & op2127=0x62 & op0513=0 & Rdd5 & rs5 & $(END_PACKET) { + Rdd5 = tlbr(rs5); + build EndPacket; +} + +# (v4,6) tlbunlock -- "tlbunlock" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 1 1 0 0 0 0 1 + + + + + P P + + + + + + 0 1 0 + + + + + + +define pcodeop tlbunlock; + +:tlbunlock EndPacket is iclass=6 & op2127=0x61 & op1620=0 & op0013=0x40 & $(END_PACKET) { + tlbunlock(); + build EndPacket; +} + +# (v2,6) tlbw -- "tlbw ( Rss32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 1 1 0 0 0 0 0 s s s s s P P 0 t t t t t + + + + + + + + + +define pcodeop tlbw; + +:tlbw rss5,rt5 EndPacket is iclass=6 & op2127=0x60 & op13=0 & op0007=0 & rss5 & rt5 & $(END_PACKET) { + tlbw(rss5, rt5); + build EndPacket; +} + +# (v2,8) togglebit -- "Rd32 = togglebit ( Rs32 , #u5 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 1 0 0 1 1 0 s s s s s P P 0 i i i i i 0 1 0 d d d d d + +:togglebit Rd5,rs5,Uimm8_0812 EndPacket is iclass=8 & op2127=0x66 & op13=0 & op0507=2 & Rd5 & rs5 & Uimm8_0812 & $(END_PACKET) { + mask:4 = 1 << Uimm8_0812; + Rd5 = rs5 ^ mask; + build EndPacket; +} + +# (v2,12) togglebit -- "Rd32 = togglebit ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 1 1 0 1 0 + s s s s s P P + t t t t t 1 0 + d d d d d + +:togglebit Rd5,rs5,rt5 EndPacket is iclass=12 & op2127=0x34 & op13=0 & op0507=4 & Rd5 & rs5 & rt5 & $(END_PACKET) { + if (rt5 > 31) goto ; + mask:4 = 1 << rt5; + Rd5 = rs5 ^ mask; + + build EndPacket; +} + +# (v4,6) trace -- "trace ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 0 0 1 0 0 1 0 s s s s s P P + + + + + + + + + + + + + + + +define pcodeop trace; + +:trace rs5 EndPacket is iclass=6 & op2127=0x12 & op0013=0 & rs5 & $(END_PACKET) { + trace(rs5); + build EndPacket; +} + +# (v2,5) trap0 -- "trap0 ( #u8 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 1 0 1 0 0 0 0 + + + + + + P P - i i i i i - - - i i i - - + +define pcodeop getTrap0Vector; + +:trap0 Uimm8_0812_0204 EndPacket is iclass=5 & op2127=0x20 & op1620=0 & op13=0 & op0507=0 & op0001=0 & Uimm8_0812_0204 & $(END_PACKET) { + dest:4 = getTrap0Vector(); + build EndPacket; + <> + $(CAUSE) = Uimm8_0812_0204; + # $(ELR) = ReturnAddr; + call [dest]; +} + +# (v2,5) trap1 -- "trap1 ( Rx32, #u8 )" +# trap1(#u8) Assembler mapped to: "trap1(R0,#u8)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 0 1 0 1 0 0 1 0 - x x x x x P P - i i i i i - - - i i i - - + +define pcodeop getTrap1Vector; + +:trap1 rx5, Uimm8_0812_0204 EndPacket is iclass=5 & op2127=0x24 & rx5 & op13=0 & op0507=0 & op0001=0 & Uimm8_0812_0204 & $(END_PACKET) { + # TODO: Instruction manual does not specify the behavior of the Rx register in this instruction + dest:4 = getTrap1Vector(); + build EndPacket; + <> + $(CAUSE) = Uimm8_0812_0204; + # $(ELR) = ReturnAddr; + call [dest]; +} + +:trap1 Uimm8_0812_0204 EndPacket is iclass=5 & op2127=0x24 & op1620=0 & op13=0 & op0507=0 & op0001=0 & Uimm8_0812_0204 & $(END_PACKET) { + dest:4 = getTrap1Vector(); + build EndPacket; + <> + $(CAUSE) = Uimm8_0812_0204; + # $(ELR) = ReturnAddr; + call [dest]; +} + +# (v2,8) tstbit -- "Pd4 = tstbit ( Rs32 , #u5 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 1 0 1 0 0 0 s s s s s P P 0 i i i i i - - - - - - d d + +:tstbit Pd2,rs5,Uimm8_0812 EndPacket is iclass=8 & op2127=0x28 & rs5 & Uimm8_0812 & Pd2 & $(END_PACKET) { + mask:4 = 1 << Uimm8_0812; + bool:1 = (rs5 & mask) != 0; + Pd2 = Pd2 & (bool * 0xff); + build EndPacket; +} + +# (v4,8) tstbit -- "Pd4 = ! tstbit ( Rs32 , #u5 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 1 0 1 0 0 1 s s s s s P P 0 i i i i i - - - - - - d d + +:"!tstbit" Pd2,rs5,Uimm8_0812 EndPacket is iclass=8 & op2127=0x29 & rs5 & Uimm8_0812 & Pd2 & $(END_PACKET) { + mask:4 = 1 << Uimm8_0812; + bool:1 = (rs5 & mask) == 0; + Pd2 = Pd2 & (bool * 0xff); + build EndPacket; +} + +# (v2,12) tstbit -- "Pd4 = tstbit ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 1 1 1 0 0 0 s s s s s P P + t t t t t + + + + + + d d + +:tstbit Pd2,rs5,rt5 EndPacket is iclass=12 & op2127=0x38 & op13=0 & op0207=0 & rs5 & rt5 & Pd2 & $(END_PACKET) { + mask:4 = 1 << rt5; + bool:1 = (rs5 & mask) != 0; + Pd2 = Pd2 & (bool * 0xff); + build EndPacket; +} + +# (v4,12) tstbit -- "Pd4 = ! tstbit ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 1 1 1 0 0 1 s s s s s P P + t t t t t + + + + + + d d + +:"!tstbit" Pd2,rs5,rt5 EndPacket is iclass=12 & op2127=0x39 & op13=0 & op0207=0 & rs5 & rt5 & Pd2 & $(END_PACKET) { + mask:4 = 1 << rt5; + bool:1 = (rs5 & mask) == 0; + Pd2 = Pd2 & (bool * 0xff); + build EndPacket; +} + +# (v65,14) vabsdiffb -- "Rdd32 = vabsdiffb ( Rtt32 , Rss32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 0 1 1 1 s s s s s P P 0 t t t t t 0 0 0 d d d d d + +define pcodeop vabsdiffb; + +:vabsdiffb Rdd5,rtt5,rss5 EndPacket is iclass=14 & op2127=0x47 & op13=0 & op0507=0 & rss5 & rtt5 & Rdd5 & $(END_PACKET) { + Rdd5 = vabsdiffb(rtt5,rss5); + build EndPacket; +} + +# (v65,14) vabsdiffub -- "Rdd32 = vabsdiffub ( Rtt32 , Rss32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 0 1 0 1 s s s s s P P 0 t t t t t 0 0 0 d d d d d + +define pcodeop vabsdiffub; + +:vabsdiffub Rdd5,rtt5,rss5 EndPacket is iclass=14 & op2127=0x45 & op13=0 & op0507=0 & rss5 & rtt5 & Rdd5 & $(END_PACKET) { + Rdd5 = vabsdiffub(rtt5,rss5); + build EndPacket; +} + +# (v2,14) vabsdiffh -- "Rdd32 = vabsdiffh ( Rtt32 , Rss32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 0 0 1 1 s s s s s P P + t t t t t 0 0 0 d d d d d + +define pcodeop vabsdiffh; + +:vabsdiffh Rdd5,rtt5,rss5 EndPacket is iclass=14 & op2127=0x43 & op13=0 & op0507=0 & rss5 & rtt5 & Rdd5 & $(END_PACKET) { + Rdd5 = vabsdiffh(rtt5,rss5); + build EndPacket; +} + +# (v2,14) vabsdiffw -- "Rdd32 = vabsdiffw ( Rtt32 , Rss32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 0 0 0 1 s s s s s P P + t t t t t 0 0 0 d d d d d + +define pcodeop vabsdiffw; + +:vabsdiffw Rdd5,rtt5,rss5 EndPacket is iclass=14 & op2127=0x41 & op13=0 & op0507=0 & rss5 & rtt5 & Rdd5 & $(END_PACKET) { + Rdd5 = vabsdiffw(rtt5,rss5); + build EndPacket; +} + +# (v2,8) vabsh -- "Rdd32 = vabsh ( Rss32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 0 0 0 0 1 + s s s s s P P + + + + + + 1 0 0 d d d d d + +define pcodeop vabsh; + +:vabsh Rdd5,rss5 EndPacket is iclass=8 & op2127=0x02 & op0513=4 & rss5 & Rdd5 & $(END_PACKET) { + Rdd5 = vabsh(rss5); + build EndPacket; +} + +# (v2,8) vabsh -- "Rdd32 = vabsh ( Rss32 ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 0 0 0 0 1 + s s s s s P P + + + + + + 1 0 1 d d d d d + +define pcodeop vabshSat; + +:vabsh":sat" Rdd5,rss5 EndPacket is iclass=8 & op2127=0x02 & op0513=5 & rss5 & Rdd5 & $(END_PACKET) { + Rdd5 = vabshSat(rss5); + build EndPacket; +} + +# (v2,8) vabsw -- "Rdd32 = vabsw ( Rss32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 0 0 0 0 1 + s s s s s P P + + + + + + 1 1 0 d d d d d + +define pcodeop vabsw; + +:vabsw Rdd5,rss5 EndPacket is iclass=8 & op2127=0x02 & op0513=6 & rss5 & Rdd5 & $(END_PACKET) { + Rdd5 = vabsw(rss5); + build EndPacket; +} + +# (v2,8) vabsw -- "Rdd32 = vabsw ( Rss32 ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 0 0 0 0 1 + s s s s s P P + + + + + + 1 1 1 d d d d d + +define pcodeop vabswSat; + +:vabsw":sat" Rdd5,rss5 EndPacket is iclass=8 & op2127=0x02 & op0513=7 & rss5 & Rdd5 & $(END_PACKET) { + Rdd5 = vabswSat(rss5); + build EndPacket; +} + +# (v55,14) vacsh -- "Rxx,Pe = vacsh ( Rss, Rtt )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 1 0 1 0 1 s s s s s P P 0 t t t t t 0 e e x x x x x + +:vacsh Rdd5,pu0506,rss5,rtt5 EndPacket is iclass=14 & op2127=0x55 & op13=0 & op7=0 & rss5 & rtt5 & pu0506 & Rdd5 & $(END_PACKET) +unimpl + +# (v2,15) vaddh -- "Rd32 = vaddh ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 1 0 1 1 0 0 0 0 s s s s s P P + t t t t t + + + d d d d d + +:vaddh Rd5,rs5,rt5 EndPacket is iclass=15 & op2127=0x30 & op13=0 & op0507=0 & rs5 & rt5 & Rd5 & $(END_PACKET) { + Rd5[0,16] = rs5[0,16] + rt5[0,16]; + Rd5[16,16] = rs5[16,16] + rt5[16,16]; + build EndPacket; +} + +# (v2,15) vaddh -- "Rd32 = vaddh ( Rs32 , Rt32 ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 1 0 1 1 0 0 0 1 s s s s s P P + t t t t t + + + d d d d d + +:vaddh":sat" Rd5,rs5,rt5 EndPacket is iclass=15 & op2127=0x31 & op13=0 & op0507=0 & rs5 & rt5 & Rd5 & $(END_PACKET) { + h:2 = 0; + addSat16(h, rt5[0,16], rs5[0,16]); + Rd5[0,16] = h; + addSat16(h, rt5[16,16], rs5[16,16]); + Rd5[16,16] = h; + build EndPacket; +} + +# (v2,13) vaddh -- "Rdd32 = vaddh ( Rss32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 1 0 0 0 s s s s s P P + t t t t t 0 1 0 d d d d d + +:vaddh Rdd5,rss5,rtt5 EndPacket is iclass=13 & op2127=0x18 & op13=0 & op0507=2 & rss5 & rtt5 & Rdd5 & $(END_PACKET) { + Rdd5[0,16] = rss5[0,16] + rtt5[0,16]; + Rdd5[16,16] = rss5[16,16] + rtt5[16,16]; + Rdd5[32,16] = rss5[32,16] + rtt5[32,16]; + Rdd5[48,16] = rss5[48,16] + rtt5[48,16]; + build EndPacket; +} + +# (v2,13) vaddh -- "Rdd32 = vaddh ( Rss32 , Rtt32 ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 1 0 0 0 s s s s s P P + t t t t t 0 1 1 d d d d d + +:vaddh":sat" Rdd5,rss5,rtt5 EndPacket is iclass=13 & op2127=0x18 & op13=0 & op0507=3 & rss5 & rtt5 & Rdd5 & $(END_PACKET) { + h:2 = 0; + addSat16(h, rtt5[0,16], rss5[0,16]); + Rdd5[0,16] = h; + addSat16(h, rtt5[16,16], rss5[16,16]); + Rdd5[16,16] = h; + addSat16(h, rtt5[32,16], rss5[32,16]); + Rdd5[32,16] = h; + addSat16(h, rtt5[48,16], rss5[48,16]); + Rdd5[48,16] = h; + build EndPacket; +} + +# (v?,12) vaddhub -- "Rd32 = vaddhub ( Rss32 , Rtt32 ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 0 0 1 0 1 0 s s s s s P P + t t t t t 0 0 1 d d d d d + +define pcodeop vaddhub_sat; + +:vaddhub":sat" Rd5,rss5,rtt5 EndPacket is iclass=12 & op2127=0x0a & op13=0 & op0507=1 & rss5 & rtt5 & Rd5 & $(END_PACKET) { + Rd5 = vaddhub_sat(rss5, rtt5); + build EndPacket; +} + +# (v2,13) vaddub -- "Rdd32 = vaddub ( Rss32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 1 0 0 0 s s s s s P P + t t t t t 0 0 0 d d d d d + +define pcodeop vaddub; + +:vaddub Rdd5,rss5,rtt5 EndPacket is iclass=13 & op2127=0x18 & op13=0 & op0507=0 & rss5 & rtt5 & Rdd5 & $(END_PACKET) { + Rdd5 = vaddub(rss5,rtt5); + build EndPacket; +} + +# (v2,13) vaddub -- "Rdd32 = vaddub ( Rss32 , Rtt32 ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 1 0 0 0 s s s s s P P + t t t t t 0 0 1 d d d d d + +define pcodeop vaddubSat; + +:vaddub":sat" Rdd5,rss5,rtt5 EndPacket is iclass=13 & op2127=0x18 & op13=0 & op0507=1 & rss5 & rtt5 & Rdd5 & $(END_PACKET) +{ + Rdd5 = vaddubSat(rss5,rtt5); + build EndPacket; +} + +# (v2,15) vadduh -- "Rd32 = vadduh ( Rs32 , Rt32 ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 1 0 1 1 0 0 1 1 s s s s s P P + t t t t t + + + d d d d d + +:vadduh":sat" Rd5,rs5,rt5 EndPacket is iclass=15 & op2127=0x33 & op13=0 & op0507=0 & rs5 & rt5 & Rd5 & $(END_PACKET) +{ + h:2 = 0; + adduSat16(h, rt5[0,16], rs5[0,16]); + Rd5[0,16] = h; + adduSat16(h, rt5[16,16], rs5[16,16]); + Rd5[16,16] = h; + build EndPacket; +} + +# (v2,13) vadduh -- "Rdd32 = vadduh ( Rss32 , Rtt32 ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 1 0 0 0 s s s s s P P + t t t t t 1 0 0 d d d d d + +:vadduh":sat" Rdd5,rss5,rtt5 EndPacket is iclass=0xd & op2127=0x18 & op13=0 & op0507=4 & rss5 & rtt5 & Rdd5 & $(END_PACKET) +{ + h:2 = 0; + adduSat16(h, rtt5[0,16], rss5[0,16]); + Rdd5[0,16] = h; + adduSat16(h, rtt5[16,16], rss5[16,16]); + Rdd5[16,16] = h; + adduSat16(h, rtt5[32,16], rss5[32,16]); + Rdd5[32,16] = h; + adduSat16(h, rtt5[48,16], rss5[48,16]); + Rdd5[48,16] = h; + build EndPacket; +} + +# (v2,13) vaddw -- "Rdd32 = vaddw ( Rss32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 1 0 0 0 s s s s s P P + t t t t t 1 0 1 d d d d d + +:vaddw Rdd5,rtt5,rss5 EndPacket is iclass=0xd & op2127=0x18 & op13=0 & op0507=5 & rss5 & rtt5 & Rdd5 & $(END_PACKET) +{ + Rdd5[0,32] = rtt5[0,32] + rss5[0,32]; + Rdd5[32,32] = rtt5[32,32] + rss5[32,32]; + build EndPacket; +} + +# (v2,13) vaddw -- "Rdd32 = vaddw ( Rss32 , Rtt32 ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 1 0 0 0 s s s s s P P + t t t t t 1 1 0 d d d d d + +:vaddw":sat" Rdd5,rtt5,rss5 EndPacket is iclass=0xd & op2127=0x18 & op13=0 & op0507=6 & rss5 & rtt5 & Rdd5 & $(END_PACKET) +{ + w:4 = 0; + addSat32(w, rtt5[0,32], rss5[0,32]); + Rdd5[0,32] = w; + addSat32(w, rtt5[32,32], rss5[32,32]); + Rdd5[32,32] = w; + build EndPacket; +} + +# (v2,12) valignb -- "Rdd32 = valignb ( Rtt32 , Rss32 , #u3 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 0 0 0 0 + + s s s s s P P + t t t t t i i i d d d d d + +macro valignb(d, s, t, align) { + d = (s >> (align * 8)) | (t << ((8-align)*8)); +} + +:valignb Rdd5,rtt5,rss5,Uimm8_0507 EndPacket is iclass=0xc & op2127=0 & rss5 & op13=0 & rtt5 & Rdd5 & Uimm8_0507 & $(END_PACKET) +{ + valignb(Rdd5, rss5, rtt5, Uimm8_0507); + build EndPacket; +} + +# (v2,12) valignb -- "Rdd32 = valignb ( Rtt32 , Rss32 , Pu4 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 0 1 0 0 + + s s s s s P P + t t t t t + u u d d d d d + +:valignb Rdd5,rtt5,rss5,pu0506 EndPacket is iclass=0xc & op2127=0x10 & rss5 & op13=0 & op7=0 & rtt5 & Rdd5 & pu0506 & $(END_PACKET) +{ + valignb(Rdd5, rss5, rtt5, pu0506 & 0x7); + build EndPacket; +} + +# (v2,8) vaslh -- "Rdd32 = vaslh ( Rss32 , #u4 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 0 0 0 1 0 + s s s s s P P 0 0 i i i i 0 1 0 d d d d d + +:vaslh Rdd5,rss5,Uimm8_0811 EndPacket is iclass=8 & op2127=0x04 & op1213=0 & op0507=2 & rss5 & Uimm8_0811 & Rdd5 & $(END_PACKET) +{ + Rdd5[0,16] = rss5[0,16] << Uimm8_0811; + Rdd5[16,16] = rss5[16,16] << Uimm8_0811; + Rdd5[32,16] = rss5[32,16] << Uimm8_0811; + Rdd5[48,16] = rss5[48,16] << Uimm8_0811; + build EndPacket; +} + +# (v2,12) vaslh -- "Rdd32 = vaslh ( Rss32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 0 1 1 0 1 + s s s s s P P + t t t t t 1 0 + d d d d d + +:vaslh Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x1a & op13=0 & op0507=4 & rss5 & rt5 & Rdd5 & $(END_PACKET) +{ + # TODO: should we assume positive shift amount to avoid conditional ? + right:1 = rt5 s< 0; + h:2 = rss5[0,16]; + Rdd5[0,16] = (zext(right) * (h s>> -rt5)) + (zext(!right) * (h << rt5)); + h = rss5[16,16]; + Rdd5[16,16] = (zext(right) * (h s>> -rt5)) + (zext(!right) * (h << rt5)); + h = rss5[32,16]; + Rdd5[32,16] = (zext(right) * (h s>> -rt5)) + (zext(!right) * (h << rt5)); + h = rss5[48,16]; + Rdd5[48,16] = (zext(right) * (h s>> -rt5)) + (zext(!right) * (h << rt5)); + build EndPacket; +} + +# (v2,8) vaslw -- "Rdd32 = vaslw ( Rss32 , #u5 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 0 0 0 0 1 + s s s s s P P 0 i i i i i 0 1 0 d d d d d + +:vaslw Rdd5,rss5,Uimm8_0812 EndPacket is iclass=8 & op2127=0x02 & op13=0 & op0507=2 & rss5 & Uimm8_0812 & Rdd5 & $(END_PACKET) +{ + Rdd5[0,32] = rss5[0,32] << Uimm8_0812; + Rdd5[32,32] = rss5[32,32] << Uimm8_0812; + build EndPacket; +} + +# (v2,12) vaslw -- "Rdd32 = vaslw ( Rss32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 0 1 1 0 0 + s s s s s P P + t t t t t 1 0 + d d d d d + +:vaslw Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x18 & op13=0 & op0507=4 & rss5 & rt5 & Rdd5 & $(END_PACKET) +{ + # TODO: should we assume positive shift amount to avoid conditional ? + right:1 = rt5 s< 0; + w:4 = rss5[0,32]; + Rdd5[0,32] = (zext(right) * (w s>> -rt5)) + (zext(!right) * (w << rt5)); + w = rss5[32,32]; + Rdd5[32,32] = (zext(right) * (w s>> -rt5)) + (zext(!right) * (w << rt5)); + build EndPacket; +} + +# (v2,8) vasrh -- "Rdd32 = vasrh ( Rss32 , #u4 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 0 0 0 1 0 + s s s s s P P 0 0 i i i i 0 0 0 d d d d d + +:vasrh Rdd5,rss5,Uimm8_0811 EndPacket is iclass=8 & op2127=0x04 & op1213=0 & op0507=0 & rss5 & Uimm8_0811 & Rdd5 & $(END_PACKET) +{ + Rdd5[0,16] = rss5[0,16] s>> Uimm8_0811; + Rdd5[16,16] = rss5[16,16] s>> Uimm8_0811; + Rdd5[32,16] = rss5[32,16] s>> Uimm8_0811; + Rdd5[48,16] = rss5[48,16] s>> Uimm8_0811; + build EndPacket; +} + +# (v?,8) vasrh -- "Rdd32 = vasrh ( Rss32 , #u4 ):raw" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 0 0 0 0 0 1 s s s s s P P 0 0 i i i i 0 0 0 d d d d d + +:vasrh":raw" Rdd5,rss5,Uimm8_0811 EndPacket is iclass=8 & op2127=0x01 & op1213=0 & op0507=0 & rss5 & Uimm8_0811 & Rdd5 & $(END_PACKET) +{ + Rdd5[0,16] = ((rss5[0,16] s>> Uimm8_0811) + 1) >> 1; + Rdd5[16,16] = ((rss5[16,16] s>> Uimm8_0811) + 1) >> 1; + Rdd5[32,16] = ((rss5[32,16] s>> Uimm8_0811) + 1) >> 1; + Rdd5[48,16] = ((rss5[48,16] s>> Uimm8_0811) + 1) >> 1; + build EndPacket; +} + +# (v2,12) vasrh -- "Rdd32 = vasrh ( Rss32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 0 1 1 0 1 + s s s s s P P + t t t t t 0 0 + d d d d d + +:vasrh Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x1a & op13=0 & op0507=0 & rss5 & rt5 & Rdd5 & $(END_PACKET) +{ + # TODO: should we assume positive shift amount to avoid conditional ? + right:1 = rt5 s>= 0; + h:2 = rss5[0,16]; + Rdd5[0,16] = (zext(right) * (h s>> -rt5)) + (zext(!right) * (h << rt5)); + h = rss5[16,16]; + Rdd5[16,16] = (zext(right) * (h s>> -rt5)) + (zext(!right) * (h << rt5)); + h = rss5[32,16]; + Rdd5[32,16] = (zext(right) * (h s>> -rt5)) + (zext(!right) * (h << rt5)); + h = rss5[48,16]; + Rdd5[48,16] = (zext(right) * (h s>> -rt5)) + (zext(!right) * (h << rt5)); + build EndPacket; +} + + +# (v?,8) vasrhub -- "Rd32 = vasrhub ( Rss32 , #u4 ):raw" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 0 0 0 0 1 1 s s s s s P P 0 0 i i i i 0 0 0 d d d d d + +define pcodeop vasrhub_raw; + +:vasrhub":raw" Rd5,rss5,Uimm8_0811 EndPacket is iclass=8 & op2127=0x43 & op1213=0 & op0507=4 & rss5 & rt5 & Rd5 & Uimm8_0811 & $(END_PACKET) +{ + Rd5 = vasrhub_raw(rss5, Uimm8_0811); + build EndPacket; +} + +# (v?,8) vasrhub -- "Rd32 = vasrhub ( Rss32 , #u4 ):sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 0 0 0 0 1 1 s s s s s P P 0 0 i i i i 0 0 0 d d d d d + +define pcodeop vasrhub_sat; + +:vasrhub":sat" Rd5,rss5,Uimm8_0811 EndPacket is iclass=8 & op2127=0x43 & op1213=0 & op0507=5 & rss5 & rt5 & Rd5 & Uimm8_0811 & $(END_PACKET) +{ + Rd5 = vasrhub_sat(rss5, Uimm8_0811); + build EndPacket; +} + +# (v2,8) vasrw -- "Rd32 = vasrw ( Rss32 , #u5 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 0 0 0 1 1 0 s s s s s P P 0 i i i i i 0 1 + d d d d d + +:vasrw Rd5,rss5,Uimm8_0812 EndPacket is iclass=8 & op2127=0x46 & op13=0 & op0507=2 & rss5 & Uimm8_0812 & Rd5 & $(END_PACKET) +{ + res:4 = rss5[0,32] s>> Uimm8_0812; + Rd5[0,16] = res:2; + res = rss5[32,32] s>> Uimm8_0812; + Rd5[16,16] = res:2; + build EndPacket; +} + +# (v2,12) vasrw -- "Rd32 = vasrw ( Rss32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 1 0 1 - - - s s s s s P P - t t t t t 0 1 0 d d d d d + +:vasrw Rd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x28 & op13=0 & op0507=2 & rss5 & rt5 & Rd5 & $(END_PACKET) +{ + # TODO: should we assume positive shift amount to avoid conditional ? + right:1 = rt5 s>= 0; + w:4 = rss5[0,32]; + res:4 = (zext(right) * (w s>> -rt5)) + (zext(!right) * (w << rt5)); + Rd5[0,16] = res:2; + w = rss5[32,32]; + res = (zext(right) * (w s>> -rt5)) + (zext(!right) * (w << rt5)); + Rd5[16,16] = res:2; + build EndPacket; +} + +# (v2,8) vasrw -- "Rdd32 = vasrw ( Rss32 , #u5 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 0 0 0 0 1 + s s s s s P P 0 i i i i i 0 0 0 d d d d d + +:vasrw Rdd5,rss5,Uimm8_0812 EndPacket is iclass=8 & op2127=0x02 & op13=0 & op0507=0 & rss5 & Uimm8_0812 & Rdd5 & $(END_PACKET) +{ + Rdd5[0,32] = rss5[0,32] s>> Uimm8_0812; + Rdd5[32,32] = rss5[32,32] s>> Uimm8_0812; + build EndPacket; +} + +# (v2,12) vasrw -- "Rdd32 = vasrw ( Rss32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 0 1 1 0 0 + s s s s s P P + t t t t t 0 0 + d d d d d + +:vasrw Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x18 & op13=0 & op0507=0 & rss5 & rt5 & Rdd5 & $(END_PACKET) +{ + # TODO: should we assume positive shift amount to avoid conditional ? + right:1 = rt5 s>= 0; + w:4 = rss5[0,32]; + Rdd5[0,32] = (zext(right) * (w s>> -rt5)) + (zext(!right) * (w << rt5)); + w = rss5[32,32]; + Rdd5[32,32] = (zext(right) * (w s>> -rt5)) + (zext(!right) * (w << rt5)); + build EndPacket; +} + +# (v2,15) vavgh -- "Rd32 = vavgh ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 1 0 1 1 1 + 0 0 s s s s s P P + t t t t t + + + d d d d d + +:vavgh Rd5,rs5,rt5 EndPacket is iclass=15 & op2127=0x38 & op13=0 & op0507=0 & rs5 & rt5 & Rd5 & $(END_PACKET) +{ + Rd5[0,16] = (rs5[0,16] + rt5[0,16]) >> 1; + Rd5[16,16] = (rs5[16,16] + rt5[16,16]) >> 1; + build EndPacket; +} + +# (v2,15) vavgh -- "Rd32 = vavgh ( Rs32 , Rt32 ) :rnd" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 1 0 1 1 1 + 0 1 s s s s s P P + t t t t t + + + d d d d d + +:vavgh":rnd" Rd5,rs5,rt5 EndPacket is iclass=15 & op2127=0x39 & op13=0 & op0507=0 & rs5 & rt5 & Rd5 & $(END_PACKET) +{ + Rd5[0,16] = (rs5[0,16] + rt5[0,16] + 1) >> 1; + Rd5[16,16] = (rs5[16,16] + rt5[16,16] + 1) >> 1; + build EndPacket; +} + +# (v2,13) vavgh -- "Rdd32 = vavgh ( Rss32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 1 0 1 0 s s s s s P P + t t t t t 0 1 0 d d d d d + +:vavgh Rdd5,rss5,rtt5 EndPacket is iclass=13 & op2127=0x1a & op13=0 & op0507=2 & rss5 & rtt5 & Rdd5 & $(END_PACKET) +{ + Rdd5[0,16] = (rss5[0,16] + rtt5[0,16]) >> 1; + Rdd5[16,16] = (rss5[16,16] + rtt5[16,16]) >> 1; + Rdd5[32,16] = (rss5[32,16] + rtt5[32,16]) >> 1; + Rdd5[48,16] = (rss5[48,16] + rtt5[48,16]) >> 1; + build EndPacket; +} + +# (v2,13) vavgh -- "Rdd32 = vavgh ( Rss32 , Rtt32 ) :crnd" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 1 0 1 0 s s s s s P P + t t t t t 1 0 0 d d d d d + +:vavgh":crnd" Rdd5,rss5,rtt5 EndPacket is iclass=13 & op2127=0x1a & op13=0 & op0507=4 & rss5 & rtt5 & Rdd5 & $(END_PACKET) +{ + Rdd5[0,16] = roundConvergent(rss5[0,16] + rtt5[0,16] + 1, 1:1) >> 1; + Rdd5[16,16] = roundConvergent(rss5[16,16] + rtt5[16,16] + 1, 1:1) >> 1; + Rdd5[32,16] = roundConvergent(rss5[32,16] + rtt5[32,16] + 1, 1:1) >> 1; + Rdd5[48,16] = roundConvergent(rss5[48,16] + rtt5[48,16] + 1, 1:1) >> 1; + build EndPacket; +} + +# (v2,13) vavgh -- "Rdd32 = vavgh ( Rss32 , Rtt32 ) :rnd" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 1 0 1 0 s s s s s P P + t t t t t 0 1 1 d d d d d + +:vavgh":rnd" Rdd5,rss5,rtt5 EndPacket is iclass=13 & op2127=0x1a & op13=0 & op0507=3 & rss5 & rtt5 & Rdd5 & $(END_PACKET) +{ + Rdd5[0,16] = (rss5[0,16] + rtt5[0,16] + 1) >> 1; + Rdd5[16,16] = (rss5[16,16] + rtt5[16,16] + 1) >> 1; + Rdd5[32,16] = (rss5[32,16] + rtt5[32,16] + 1) >> 1; + Rdd5[48,16] = (rss5[48,16] + rtt5[48,16] + 1) >> 1; + build EndPacket; +} + +# (v2,13) vavgub -- "Rdd32 = vavgub ( Rss32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 1 0 1 0 s s s s s P P + t t t t t 0 0 0 d d d d d + +:vavgub Rdd5,rss5,rtt5 EndPacket is iclass=13 & op2127=0x1a & op13=0 & op0507=0 & rss5 & rtt5 & Rdd5 & $(END_PACKET) +unimpl + +# (v2,13) vavgub -- "Rdd32 = vavgub ( Rss32 , Rtt32 ) :rnd" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 1 0 1 0 s s s s s P P + t t t t t 0 0 1 d d d d d + +:vavgub":rnd" Rdd5,rss5,rtt5 EndPacket is iclass=13 & op2127=0x1a & op13=0 & op0507=1 & rss5 & rtt5 & Rdd5 & $(END_PACKET) +unimpl + +# (v2,13) vavguh -- "Rdd32 = vavguh ( Rss32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 1 0 1 0 s s s s s P P + t t t t t 1 0 1 d d d d d + +:vavguh Rdd5,rss5,rtt5 EndPacket is iclass=13 & op2127=0x1a & op13=0 & op0507=5 & rss5 & rtt5 & Rdd5 & $(END_PACKET) +unimpl + +# (v2,13) vavguh -- "Rdd32 = vavguh ( Rss32 , Rtt32 ) :rnd" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 1 0 1 0 s s s s s P P + t t t t t 1 1 + d d d d d + +:vavguh":rnd" Rdd5,rss5,rtt5 EndPacket is iclass=13 & op2127=0x1a & op13=0 & op0507=6 & rss5 & rtt5 & Rdd5 & $(END_PACKET) +unimpl + +# (v2,13) vavguw -- "Rdd32 = vavguw ( Rss32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 1 0 1 1 s s s s s P P + t t t t t 0 1 1 d d d d d + +:vavguw Rdd5,rss5,rtt5 EndPacket is iclass=13 & op2127=0x1b & op13=0 & op0507=3 & rss5 & rtt5 & Rdd5 & $(END_PACKET) +unimpl + +# (v2,13) vavguw -- "Rdd32 = vavguw ( Rss32 , Rtt32 ) :rnd" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 1 0 1 1 s s s s s P P + t t t t t 1 0 0 d d d d d + +:vavguw":rnd" Rdd5,rss5,rtt5 EndPacket is iclass=13 & op2127=0x1b & op13=0 & op0507=4 & rss5 & rtt5 & Rdd5 & $(END_PACKET) +unimpl + +# (v2,13) vavgw -- "Rdd32 = vavgw ( Rss32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 1 0 1 1 s s s s s P P + t t t t t 0 0 0 d d d d d + +:vavgw Rdd5,rss5,rtt5 EndPacket is iclass=13 & op2127=0x1b & op13=0 & op0507=0 & rss5 & rtt5 & Rdd5 & $(END_PACKET) +unimpl + +# (v2,13) vavgw -- "Rdd32 = vavgw ( Rss32 , Rtt32 ) :crnd" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 1 0 1 1 s s s s s P P + t t t t t 0 1 0 d d d d d + +:vavgw":crnd" Rdd5,rss5,rtt5 EndPacket is iclass=13 & op2127=0x1b & op13=0 & op0507=2 & rss5 & rtt5 & Rdd5 & $(END_PACKET) +unimpl + +# (v2,13) vavgw -- "Rdd32 = vavgw ( Rss32 , Rtt32 ) :rnd" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 1 0 1 1 s s s s s P P + t t t t t 0 0 1 d d d d d + +:vavgw":rnd" Rdd5,rss5,rtt5 EndPacket is iclass=13 & op2127=0x1b & op13=0 & op0507=1 & rss5 & rtt5 & Rdd5 & $(END_PACKET) +unimpl + +# (v65,8) vclip -- "Rdd32 = vclip ( Rss32 , #u5 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 0 0 0 1 1 0 s s s s s P P 0 i i i i i 1 1 0 d d d d d + +define pcodeop vclip; + +:vclip Rdd5,rss5,Uimm8_0812 EndPacket is iclass=8 & op2127=0x46 & op13=0 & op0507=6 & rss5 & Uimm8_0812 & Rdd5 & $(END_PACKET) { + Rdd5 = vclip(rss5,Uimm8_0812); + build EndPacket; +} + +# (v4,13) vcmpb.eq -- "Pd4 = vcmpb.eq ( Rss32 , #u8 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 1 1 0 0 + 0 0 s s s s s P P + i i i i i i i i 0 0 + d d + +:vcmpb.eq Pd2,rss5,Uimm8_0512 EndPacket is iclass=13 & op2127=0x60 & op13=0 & op0204=0 & Uimm8_0512 & rss5 & Pd2 & $(END_PACKET) { + Pd2 = Pd2 & vcmpb.eq(rss5,Uimm8_0512); + build EndPacket; +} + +# (v2,13) vcmpb.eq -- "Pd4 = vcmpb.eq ( Rss32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 0 0 + + s s s s s P P 0 t t t t t 1 1 0 + + + d d + +:vcmpb.eq Pd2,rss5,rtt5 EndPacket is iclass=13 & op2127=0x10 & op13=0 & op0207=0x30 & rtt5 & rss5 & Pd2 & $(END_PACKET) { + Pd2 = Pd2 & vcmpb.eq(rss5,rtt5); + build EndPacket; +} + +# (v4,13) vcmpb.gt -- "Pd4 = vcmpb.gt ( Rss32 , #s8 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 1 1 0 0 + 0 1 s s s s s P P + i i i i i i i i 0 0 + d d + +define pcodeop vcmpb.gt; + +:vcmpb.gt Pd2,rss5,Simm8_0512 EndPacket is iclass=13 & op2127=0x61 & op13=0 & op0204=0 & Simm8_0512 & rss5 & Pd2 & $(END_PACKET) { + Pd2 = Pd2 & vcmpb.gt(rss5,Simm8_0512); + build EndPacket; +} + +# (v4,13) vcmpb.gt -- "Pd4 = vcmpb.gt ( Rss32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 0 0 + + s s s s s P P 1 t t t t t 0 1 0 + + + d d + +:vcmpb.gt Pd2,rss5,rtt5 EndPacket is iclass=13 & op2127=0x10 & op13=1 & op0207=0x10 & rtt5 & rss5 & Pd2 & $(END_PACKET) { + Pd2 = Pd2 & vcmpb.gt(rss5,rtt5); + build EndPacket; +} + +# (v4,13) vcmpb.gtu -- "Pd4 = vcmpb.gtu ( Rss32 , #u7 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 1 1 0 0 + 1 0 s s s s s P P + 0 i i i i i i i 0 0 + d d + +define pcodeop vcmpb.gtu; + +:vcmpb.gtu Pd2,rss5,Uimm8_0511 EndPacket is iclass=13 & op2127=0x62 & op1213=0 & op0204=0 & Uimm8_0511 & rss5 & Pd2 & $(END_PACKET) { + Pd2 = Pd2 & vcmpb.gtu(rss5,Uimm8_0511); + build EndPacket; +} + +# (v2,13) vcmpb.gtu -- "Pd4 = vcmpb.gtu ( Rss32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 0 0 + + s s s s s P P 0 t t t t t 1 1 1 + + + d d + +:vcmpb.gtu Pd2,rss5,rtt5 EndPacket is iclass=13 & op2127=0x10 & op13=0 & op0207=0x38 & rtt5 & rss5 & Pd2 & $(END_PACKET) { + Pd2 = Pd2 & vcmpb.gtu(rss5,rtt5); + build EndPacket; +} + +# (v4,13) vcmph.eq -- "Pd4 = vcmph.eq ( Rss32 , #s8 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 1 1 0 0 + 0 0 s s s s s P P - i i i i i i i i 0 1 + d d + +define pcodeop vcmph.eq; + +:vcmph.eq Pd2,rss5,Simm8_0512 EndPacket is iclass=13 & op2127=0x60 & op13=0 & op0204=2 & Simm8_0512 & rss5 & Pd2 & $(END_PACKET) { + Pd2 = Pd2 & vcmph.eq(rss5,Simm8_0512); + build EndPacket; +} + +# (v2,13) vcmph.eq -- "Pd4 = vcmph.eq ( Rss32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 0 0 + + s s s s s P P 0 t t t t t 0 1 1 + + + d d + +:vcmph.eq Pd2,rss5,rtt5 EndPacket is iclass=13 & op2127=0x10 & op13=0 & op0207=0x18 & rtt5 & rss5 & Pd2 & $(END_PACKET) { + Pd2 = Pd2 & vcmph.eq(rss5,rtt5); + build EndPacket; +} + +# (v4,13) vcmph.gt -- "Pd4 = vcmph.gt ( Rss32 , #s8 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 1 1 0 0 + 0 1 s s s s s P P + i i i i i i i i 0 1 + d d + +define pcodeop vcmph.gt; + +:vcmph.gt Pd2,rss5,Simm8_0512 EndPacket is iclass=13 & op2127=0x61 & op13=0 & op0204=2 & Simm8_0512 & rss5 & Pd2 & $(END_PACKET) { + Pd2 = Pd2 & vcmph.gt(rss5,Simm8_0512); + build EndPacket; +} + +# (v2,13) vcmph.gt -- "Pd4 = vcmph.gt ( Rss32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 0 0 + + s s s s s P P 0 t t t t t 1 0 0 + + + d d + +:vcmph.gt Pd2,rss5,rtt5 EndPacket is iclass=13 & op2127=0x10 & op13=0 & op0207=0x20 & rtt5 & rss5 & Pd2 & $(END_PACKET) { + Pd2 = Pd2 & vcmph.gt(rss5,rtt5); + build EndPacket; +} + +# (v4,13) vcmph.gtu -- "Pd4 = vcmph.gtu ( Rss32 , #u7 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 1 1 0 0 + 1 0 s s s s s P P + 0 i i i i i i i 0 1 + d d + +define pcodeop vcmph.gtu; + +:vcmph.gtu Pd2,rss5,Uimm8_0511 EndPacket is iclass=13 & op2127=0x62 & op1213=0 & op0204=2 & Uimm8_0511 & rss5 & Pd2 & $(END_PACKET) { + Pd2 = Pd2 & vcmph.gtu(rss5,Uimm8_0511); + build EndPacket; +} + +# (v2,13) vcmph.gtu -- "Pd4 = vcmph.gtu ( Rss32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 0 0 + + s s s s s P P 0 t t t t t 1 0 1 + + + d d + +:vcmph.gtu Pd2,rss5,rtt5 EndPacket is iclass=13 & op2127=0x10 & op13=0 & op0207=0x28 & rtt5 & rss5 & Pd2 & $(END_PACKET) { + Pd2 = Pd2 & vcmph.gtu(rss5,rtt5); + build EndPacket; +} + +# (v4,13) vcmpw.eq -- "Pd4 = vcmpw.eq ( Rss32 , #s8 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 1 1 0 0 + 0 0 s s s s s P P + i i i i i i i i 1 0 + d d + +define pcodeop vcmpw.eq; + +:vcmpw.eq Pd2,rss5,Simm8_0512 EndPacket is iclass=13 & op2127=0x60 & op13=0 & op0204=4 & Simm8_0512 & rss5 & Pd2 & $(END_PACKET) { + Pd2 = Pd2 & vcmpw.eq(rss5,Simm8_0512); + build EndPacket; +} + +# (v2,13) vcmpw.eq -- "Pd4 = vcmpw.eq ( Rss32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 0 0 + + s s s s s P P 0 t t t t t 0 0 0 + + + d d + +:vcmpw.eq Pd2,rss5,rtt5 EndPacket is iclass=13 & op2127=0x10 & op13=0 & op0207=0 & rtt5 & rss5 & Pd2 & $(END_PACKET) { + Pd2 = Pd2 & vcmpw.eq(rss5,rtt5); + build EndPacket; +} + +# (v4,13) vcmpw.gt -- "Pd4 = vcmpw.gt ( Rss32 , #s8 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 1 1 0 0 - 0 1 s s s s s P P + i i i i i i i i 1 0 + d d + +define pcodeop vcmpw.gt; + +:vcmpw.gt Pd2,rss5,Simm8_0512 EndPacket is iclass=13 & op2127=0x61 & op13=0 & op0204=4 & Simm8_0512 & rss5 & Pd2 & $(END_PACKET) { + Pd2 = Pd2 & vcmpw.gt(rss5,Simm8_0512); + build EndPacket; +} + +# (v2,13) vcmpw.gt -- "Pd4 = vcmpw.gt ( Rss32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 0 0 + + s s s s s P P 0 t t t t t 0 0 1 + + + d d + +:vcmpw.gt Pd2,rss5,rtt5 EndPacket is iclass=13 & op2127=0x10 & op13=0 & op0207=0x08 & rtt5 & rss5 & Pd2 & $(END_PACKET) { + Pd2 = Pd2 & vcmpw.gt(rss5,rtt5); + build EndPacket; +} + +# (v4,13) vcmpw.gtu -- "Pd4 = vcmpw.gtu ( Rss32 , #u7 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 1 1 0 0 + 1 0 s s s s s P P + 0 i i i i i i i 1 0 + d d + +define pcodeop vcmpw.gtu; + +:vcmpw.gtu Pd2,rss5,Uimm8_0511 EndPacket is iclass=13 & op2127=0x62 & op1213=0 & op0204=4 & Uimm8_0511 & rss5 & Pd2 & $(END_PACKET) { + Pd2 = Pd2 & vcmpw.gtu(rss5,Uimm8_0511); + build EndPacket; +} + +# (v2,13) vcmpw.gtu -- "Pd4 = vcmpw.gtu ( Rss32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 0 0 + + s s s s s P P 0 t t t t t 0 1 0 + + + d d + +:vcmpw.gtu Pd2,rss5,rtt5 EndPacket is iclass=13 & op2127=0x10 & op13=0 & op0207=0x10 & rtt5 & rss5 & Pd2 & $(END_PACKET) { + Pd2 = Pd2 & vcmpw.gtu(rss5,rtt5); + build EndPacket; +} + +# (v2,14) vcmpyi -- "Rdd32 = vcmpyi ( Rss32 , Rtt32 ) :<<1 :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 0 1 1 0 s s s s s P P + t t t t t 1 1 0 d d d d d + +:vcmpyi":<<1:sat" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x46 & op13=0 & op0507=6 & rtt5 & rss5 & Rdd5 & $(END_PACKET) +unimpl + +# (v2,14) vcmpyi -- "Rdd32 = vcmpyi ( Rss32 , Rtt32 ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 0 0 1 0 s s s s s P P + t t t t t 1 1 0 d d d d d + +:vcmpyi":sat" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x42 & op13=0 & op0507=6 & rtt5 & rss5 & Rdd5 & $(END_PACKET) +unimpl + +# (v2,14) vcmpyi -- "Rxx32 += vcmpyi ( Rss32 , Rtt32 ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 1 0 0 1 0 s s s s s P P + t t t t t 1 0 0 x x x x x + +:vcmpyi+=":sat" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x52 & op13=0 & op0507=4 & rtt5 & rss5 & Rdd5 & $(END_PACKET) +unimpl + +# (v2,14) vcmpyr -- "Rdd32 = vcmpyr ( Rss32 , Rtt32 ) :<<1 :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 0 1 0 1 s s s s s P P + t t t t t 1 1 0 d d d d d + +define pcodeop vcmpyrX2Sat; + +:vcmpyr":<<1:sat" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x45 & op13=0 & op0507=6 & rtt5 & rss5 & Rdd5 & $(END_PACKET) { + Rdd5 = vcmpyrX2Sat(rss5, rtt5); + build EndPacket; +} + +# (v2,14) vcmpyr -- "Rdd32 = vcmpyr ( Rss32 , Rtt32 ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 0 0 0 1 s s s s s P P + t t t t t 1 1 0 d d d d d + +define pcodeop vcmpyrSat; + +:vcmpyr":sat" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x41 & op13=0 & op0507=6 & rtt5 & rss5 & Rdd5 & $(END_PACKET) { + Rdd5 = vcmpyrSat(rss5, rtt5); + build EndPacket; +} + +# (v2,14) vcmpyr -- "Rxx32 += vcmpyr ( Rss32 , Rtt32 ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 1 0 0 0 1 s s s s s P P + t t t t t 1 0 0 x x x x x + +define pcodeop vcmpyrSatAdd; + +:vcmpyr+=":sat" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x51 & op13=0 & op0507=4 & rtt5 & rss5 & rdd5 & Rdd5 & $(END_PACKET) { + Rdd5 = vcmpyrSat(rss5, rtt5, rdd5); + build EndPacket; +} + +# (v4,12) vcnegh -- "Rdd32 = vcnegh ( Rss32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 0 1 1 1 1 + s s s s s P P + t t t t t 0 1 + d d d d d + +:vcnegh Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x1e & op13=0 & op0507=2 & rt5 & rss5 & Rdd5 & $(END_PACKET) +unimpl + +# (v2,8) vconj -- "Rdd32 = vconj ( Rss32 ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 0 0 0 1 0 + s s s s s P P + + + + + + 1 1 1 d d d d d + +define pcodeop vconjSat; + +:vconj":sat" Rdd5,rss5 EndPacket is iclass=8 & op2127=0x04 & op0513=0x07 & rss5 & Rdd5 & $(END_PACKET) +{ + Rdd5 = vconjSat(rss5); + build EndPacket; +} + +# (v2,12) vcrotate -- "Rdd32 = vcrotate ( Rss32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 0 1 1 1 1 + s s s s s P P + t t t t t 0 0 + d d d d d + +define pcodeop vcrotate; + +:vcrotate Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x1e & op13=0 & op0507=0 & rt5 & rss5 & Rdd5 & $(END_PACKET) +{ + Rdd5 = vcrotate(rss5, rt5); + build EndPacket; +} + +# (v2,14) vdmpy -- "Rd32 = vdmpy ( Rss32 , Rtt32 ) :<<1 :rnd :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 1 1 + + s s s s s P P + t t t t t + 0 0 d d d d d + +define pcodeop vdmpyX2RndSat; + +:vdmpy":<<1:rnd:sat" Rd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x4c & op13=0 & op0507=0 & rtt5 & rss5 & Rd5 & $(END_PACKET) { + Rd5 = vdmpyX2RndSat(rss5, rtt5); + build EndPacket; +} + +# (v2,14) vdmpy -- "Rd32 = vdmpy ( Rss32 , Rtt32 ) :rnd :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 1 0 + + s s s s s P P + t t t t t + 0 0 d d d d d + +define pcodeop vdmpyRndSat; + +:vdmpy":rnd:sat" Rd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x48 & op13=0 & op0507=0 & rtt5 & rss5 & Rd5 & $(END_PACKET) { + Rd5 = vdmpyRndSat(rss5, rtt5); + build EndPacket; +} + +# (v2,14) vdmpy -- "Rdd32 = vdmpy ( Rss32 , Rtt32 ) :<<1 :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 0 1 0 0 s s s s s P P + t t t t t 1 0 0 d d d d d + +define pcodeop vdmpyX2Sat; + +:vdmpy":<<1:sat" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x44 & op13=0 & op0507=4 & rtt5 & rss5 & Rdd5 & $(END_PACKET) { + Rdd5 = vdmpyX2Sat(rss5, rtt5); + build EndPacket; +} + +# (v2,14) vdmpy -- "Rdd32 = vdmpy ( Rss32 , Rtt32 ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 0 0 0 0 s s s s s P P + t t t t t 1 0 0 d d d d d + +define pcodeop vdmpySat; + +:vdmpy":sat" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x40 & op13=0 & op0507=4 & rtt5 & rss5 & Rdd5 & $(END_PACKET) { + Rdd5 = vdmpySat(rss5, rtt5); + build EndPacket; +} + +# (v2,14) vdmpy -- "Rxx32 += vdmpy ( Rss32 , Rtt32 ) :<<1 :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 1 0 1 0 0 s s s s s P P + t t t t t 1 0 0 x x x x x + +define pcodeop vdmpyX2SatAdd; + +:vdmpy+=":<<1:sat" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x54 & op13=0 & op0507=4 & rtt5 & rss5 & rdd5 & Rdd5 & $(END_PACKET) { + Rdd5 = vdmpyX2SatAdd(rss5, rtt5, rdd5); + build EndPacket; +} + +# (v2,14) vdmpy -- "Rxx32 += vdmpy ( Rss32 , Rtt32 ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 1 0 0 0 0 s s s s s P P + t t t t t 1 0 0 x x x x x + +define pcodeop vdmpySatAdd; + +:vdmpy+=":sat" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x50 & op13=0 & op0507=4 & rtt5 & rss5 & rdd5 & Rdd5 & $(END_PACKET) { + Rdd5 = vdmpySatAdd(rss5, rtt5, rdd5); + build EndPacket; +} + +# (v?,14) vdmpybsu -- "Rxx32 = vdmpybsu ( Rss32 , Rtt32 ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 0 1 0 1 s s s s s P P + t t t t t 0 0 1 x x x x x + +define pcodeop vdmpybsuSat; + +:vdmpybsu=":sat" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x45 & op13=0 & op0507=1 & rtt5 & rss5 & Rdd5 & $(END_PACKET) { + Rdd5 = vdmpybsuSat(rss5, rtt5); + build EndPacket; +} + +# (v?,14) vdmpybsu -- "Rxx32 += vdmpybsu ( Rss32 , Rtt32 ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 1 0 0 0 1 s s s s s P P + t t t t t 0 0 1 x x x x x + +define pcodeop vdmpybsuSatAdd; + +:vdmpybsu+=":sat" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x51 & op13=0 & op0507=1 & rtt5 & rss5 & rdd5 & Rdd5 & $(END_PACKET) { + Rdd5 = vdmpybsuSatAdd(rss5, rtt5, rdd5); + build EndPacket; +} + +# (v2,8) vitpack -- "Rd32 = vitpack ( Ps4 , Pt4 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 0 0 1 + 0 + + + + s s P P + + + + t t + + + d d d d d + +:vitpack Rd5,pu1617,pu0809 EndPacket is iclass=8 & op2127=0x48 & op1820=0 & op1013=0 & op0507=0 & pu1617 & pu0809 & Rd5 & $(END_PACKET) +{ + Rd5 = zext((pu1617 & 0x55) | (pu0809 & 0xaa)); + build EndPacket; +} + +# (v2,12) vlslh -- "Rdd32 = vlslh ( Rss32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 0 1 1 0 1 + s s s s s P P + t t t t t 1 1 + d d d d d + +define pcodeop vlslh; + +:vlslh Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x1a & op13=0 & op0507=6 & Rdd5 & rt5 & rss5 & $(END_PACKET) { + Rdd5 = vlslh(rss5, rt5); + build EndPacket; +} + +# (v2,12) vlslw -- "Rdd32 = vlslw ( Rss32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 0 1 1 0 0 + s s s s s P P + t t t t t 1 1 + d d d d d + +define pcodeop vlslw; + +:vlslw Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x18 & op13=0 & op0507=6 & Rdd5 & rt5 & rss5 & $(END_PACKET) { + Rdd5 = vlslw(rss5, rt5); + build EndPacket; +} + +# (v2,8) vlsrh -- "Rdd32 = vlsrh ( Rss32 , #u4 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 0 0 0 1 0 + s s s s s P P 0 0 i i i i 0 0 1 d d d d d + +define pcodeop vlsrh; + +:vlsrh Rdd5,rss5,Uimm8_0811 EndPacket is iclass=8 & op2127=0x04 & op1213=0 & op0507=1 & Rdd5 & Uimm8_0811 & rss5 & $(END_PACKET) { + Rdd5 = vlsrh(rss5, Uimm8_0811); + build EndPacket; +} + +# (v2,12) vlsrh -- "Rdd32 = vlsrh ( Rss32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 0 1 1 0 1 + s s s s s P P + t t t t t 0 1 + d d d d d + +:vlsrh Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x1a & op13=0 & op0507=2 & Rdd5 & rt5 & rss5 & $(END_PACKET) { + Rdd5 = vlsrh(rss5, rt5); + build EndPacket; +} + +# (v2,8) vlsrw -- "Rdd32 = vlsrw ( Rss32 , #u5 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 0 0 0 0 1 + s s s s s P P 0 i i i i i 0 0 1 d d d d d + +define pcodeop vlsrw; + +:vlsrw Rdd5,rss5,Uimm8_0812 EndPacket is iclass=8 & op2127=0x02 & op13=0 & op0507=1 & Rdd5 & Uimm8_0812 & rss5 & $(END_PACKET) { + Rdd5 = vlsrw(rss5, Uimm8_0812); + build EndPacket; +} + +# (v2,12) vlsrw -- "Rdd32 = vlsrw ( Rss32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 0 1 1 0 0 + s s s s s P P + t t t t t 0 1 + d d d d d + +:vlsrw Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x18 & op13=0 & op0507=2 & Rdd5 & rt5 & rss5 & $(END_PACKET) { + Rdd5 = vlsrw(rss5, rt5); + build EndPacket; +} + +# (v4,13) vmaxb -- "Rdd32 = vmaxb ( Rtt32 , Rss32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 1 1 1 0 s s s s s P P + t t t t t 1 1 0 d d d d d + +define pcodeop vmaxb; + +:vmaxb Rdd5,rss5,rtt5 EndPacket is iclass=13 & op2127=0x1e & op13=0 & op0507=6 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vmaxb(rss5, rtt5); + build EndPacket; +} + +# (v2,13) vmaxh -- "Rdd32 = vmaxh ( Rtt32 , Rss32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 1 1 1 0 s s s s s P P + t t t t t 0 0 1 d d d d d + +define pcodeop vmaxh; + +:vmaxh Rdd5,rss5,rtt5 EndPacket is iclass=13 & op2127=0x1e & op13=0 & op0507=1 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vmaxh(rss5, rtt5); + build EndPacket; +} + +# (v2,13) vmaxub -- "Rdd32 = vmaxub ( Rtt32 , Rss32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 1 1 1 0 s s s s s P P + t t t t t 0 0 0 d d d d d + +define pcodeop vmaxub; + +:vmaxub Rdd5,rss5,rtt5 EndPacket is iclass=13 & op2127=0x1e & op13=0 & op0507=0 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vmaxub(rss5, rtt5); + build EndPacket; +} + +# (v2,13) vmaxuh -- "Rdd32 = vmaxuh ( Rtt32 , Rss32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 1 1 1 0 s s s s s P P + t t t t t 0 1 0 d d d d d + +define pcodeop vmaxuh; + +:vmaxuh Rdd5,rss5,rtt5 EndPacket is iclass=13 & op2127=0x1e & op13=0 & op0507=2 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vmaxuh(rss5, rtt5); + build EndPacket; +} + +# (v2,13) vmaxuw -- "Rdd32 = vmaxuw ( Rtt32 , Rss32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 1 1 0 1 s s s s s P P + t t t t t 1 0 1 d d d d d + +define pcodeop vmaxuw; + +:vmaxuw Rdd5,rss5,rtt5 EndPacket is iclass=13 & op2127=0x1d & op13=0 & op0507=5 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vmaxuw(rss5, rtt5); + build EndPacket; +} + +# (v2,13) vmaxw -- "Rdd32 = vmaxw ( Rtt32 , Rss32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 1 1 1 0 s s s s s P P + t t t t t 0 1 1 d d d d d + +define pcodeop vmaxw; + +:vmaxw Rdd5,rss5,rtt5 EndPacket is iclass=13 & op2127=0x1e & op13=0 & op0507=3 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vmaxw(rss5, rtt5); + build EndPacket; +} + +# (v4,13) vminb -- "Rdd32 = vminb ( Rtt32 , Rss32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 1 1 1 0 s s s s s P P + t t t t t 1 1 1 d d d d d + +define pcodeop vminb; + +:vminb Rdd5,rss5,rtt5 EndPacket is iclass=13 & op2127=0x1e & op13=0 & op0507=7 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vminb(rss5, rtt5); + build EndPacket; +} + +# (v2,13) vminh -- "Rdd32 = vminh ( Rtt32 , Rss32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 1 1 0 1 s s s s s P P + t t t t t 0 0 1 d d d d d + +define pcodeop vminh; + +:vminh Rdd5,rss5,rtt5 EndPacket is iclass=13 & op2127=0x1d & op13=0 & op0507=1 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vminh(rss5, rtt5); + build EndPacket; +} + +# (v2,13) vminub -- "Rdd32 = vminub ( Rtt32 , Rss32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 1 1 0 1 s s s s s P P + t t t t t 0 0 0 d d d d d + +define pcodeop vminub; + +:vminub Rdd5,rss5,rtt5 EndPacket is iclass=13 & op2127=0x1d & op13=0 & op0507=0 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vminub(rss5, rtt5); + build EndPacket; +} + +# (v2,13) vminuh -- "Rdd32 = vminuh ( Rtt32 , Rss32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 1 1 0 1 s s s s s P P + t t t t t 0 1 0 d d d d d + +define pcodeop vminuh; + +:vminuh Rdd5,rss5,rtt5 EndPacket is iclass=13 & op2127=0x1d & op13=0 & op0507=2 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vminuh(rss5, rtt5); + build EndPacket; +} + +# (v2,13) vminuw -- "Rdd32 = vminuw ( Rtt32 , Rss32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 1 1 0 1 s s s s s P P + t t t t t 1 0 0 d d d d d + +define pcodeop vminuw; + +:vminuw Rdd5,rss5,rtt5 EndPacket is iclass=13 & op2127=0x1d & op13=0 & op0507=4 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vminuw(rss5, rtt5); + build EndPacket; +} + +# (v2,13) vminw -- "Rdd32 = vminw ( Rtt32 , Rss32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 1 1 0 1 s s s s s P P + t t t t t 0 1 1 d d d d d + +define pcodeop vminw; + +:vminw Rdd5,rss5,rtt5 EndPacket is iclass=13 & op2127=0x1d & op13=0 & op0507=3 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vminw(rss5, rtt5); + build EndPacket; +} + +# (v4,14) vmpybsu -- "Rdd32 = vmpybsu ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 0 1 0 1 0 s s s s s P P + t t t t t 0 0 1 d d d d d + +define pcodeop vmpybsu; + +:vmpybsu Rdd5,rs5,rt5 EndPacket is iclass=14 & op2127=0x2a & op13=0 & op0507=1 & Rdd5 & rt5 & rs5 & $(END_PACKET) { + Rdd5 = vmpybsu(rs5, rt5); + build EndPacket; +} + +# (v4,14) vmpybsu -- "Rxx32 += vmpybsu ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 1 1 1 1 0 s s s s s P P + t t t t t 0 0 1 x x x x x + +:vmpybsu+= Rdd5,rs5,rt5 EndPacket is iclass=14 & op2127=0x3e & op13=0 & op0507=1 & Rdd5 & rdd5 & rt5 & rs5 & $(END_PACKET) +unimpl + +# (v4,14) vmpybu -- "Rdd32 = vmpybu ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 0 1 1 0 0 s s s s s P P + t t t t t 0 0 1 d d d d d + +define pcodeop vmpybu; + +:vmpybu Rdd5,rs5,rt5 EndPacket is iclass=14 & op2127=0x2c & op13=0 & op0507=1 & Rdd5 & rt5 & rs5 & $(END_PACKET) { + Rdd5 = vmpybu(rs5, rt5); + build EndPacket; +} + +# (v4,14) vmpybu -- "Rxx32 += vmpybu ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 1 1 1 0 0 s s s s s P P + t t t t t 0 0 1 x x x x x + +:vmpybu+= Rdd5,rs5,rt5 EndPacket is iclass=14 & op2127=0x3c & op13=0 & op0507=1 & Rdd5 & rdd5 & rt5 & rs5 & $(END_PACKET) +unimpl + +# (v2,14) vmpyeh -- "Rdd32 = vmpyeh ( Rss32 , Rtt32 ) :<<1 :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 0 1 0 0 s s s s s P P + t t t t t 1 1 0 d d d d d + +define pcodeop vmpyehX2Sat; + +:vmpyeh":<<1:sat" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x44 & op13=0 & op0507=6 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vmpyehX2Sat(rss5, rtt5); + build EndPacket; +} + +# (v2,14) vmpyeh -- "Rdd32 = vmpyeh ( Rss32 , Rtt32 ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 0 0 0 0 s s s s s P P + t t t t t 1 1 0 d d d d d + +define pcodeop vmpyehSat; + +:vmpyeh":sat" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x40 & op13=0 & op0507=6 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vmpyehSat(rss5, rtt5); + build EndPacket; +} + +# (v2,14) vmpyeh -- "Rxx32 += vmpyeh ( Rss32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 1 0 0 0 1 s s s s s P P + t t t t t 0 1 0 x x x x x + +define pcodeop vmpyehAdd; + +:vmpyeh+= Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x51 & op13=0 & op0507=2 & Rdd5 & rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vmpyehAdd(rss5, rtt5, rdd5); + build EndPacket; +} + +# (v2,14) vmpyeh -- "Rxx32 += vmpyeh ( Rss32 , Rtt32 ) :<<1 :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 1 0 1 0 0 s s s s s P P + t t t t t 1 1 0 x x x x x + +define pcodeop vmpyehX2SatAdd; + +:vmpyeh+=":<<1:sat" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x54 & op13=0 & op0507=6 & Rdd5 & rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vmpyehX2SatAdd(rss5, rtt5, rdd5); + build EndPacket; +} + +# (v2,14) vmpyeh -- "Rxx32 += vmpyeh ( Rss32 , Rtt32 ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 1 0 0 0 0 s s s s s P P + t t t t t 1 1 0 x x x x x + +define pcodeop vmpyehSatAdd; + +:vmpyeh+=":sat" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x50 & op13=0 & op0507=6 & Rdd5 & rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vmpyehSatAdd(rss5, rtt5, rdd5); + build EndPacket; +} + +# (v2,14) vmpyh -- "Rd32 = vmpyh ( Rs32 , Rt32 ) :<<1 :rnd :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 0 1 1 0 1 s s s s s P P + t t t t t 1 1 1 d d d d d + +define pcodeop vmpyhX2RndSat; + +:vmpyh":<<1:rnd:sat" Rd5,rs5,rt5 EndPacket is iclass=14 & op2127=0x6d & op13=0 & op0507=7 & Rd5 & rt5 & rs5 & $(END_PACKET) { + Rd5 = vmpyhX2RndSat(rs5, rt5); + build EndPacket; +} + +# (v2,14) vmpyh -- "Rd32 = vmpyh ( Rs32 , Rt32 ) :rnd :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 0 1 0 0 1 s s s s s P P + t t t t t 1 1 1 d d d d d + +define pcodeop vmpyhRndSat; + +:vmpyh":rnd:sat" Rd5,rs5,rt5 EndPacket is iclass=14 & op2127=0x69 & op13=0 & op0507=7 & Rd5 & rt5 & rs5 & $(END_PACKET) { + Rd5 = vmpyhRndSat(rs5, rt5); + build EndPacket; +} + +# (v2,14) vmpyh -- "Rdd32 = vmpyh ( Rs32 , Rt32 ) :<<1 :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 0 1 1 0 0 s s s s s P P + t t t t t 1 0 1 d d d d d + +define pcodeop vmpyhX2Sat; + +:vmpyh":<<1:sat" Rdd5,rs5,rt5 EndPacket is iclass=14 & op2127=0x2c & op13=0 & op0507=5 & Rdd5 & rt5 & rs5 & $(END_PACKET) { + Rdd5 = vmpyhX2Sat(rs5, rt5); + build EndPacket; +} + +# (v2,14) vmpyh -- "Rdd32 = vmpyh ( Rs32 , Rt32 ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 0 1 0 0 0 s s s s s P P + t t t t t 1 0 1 d d d d d + +define pcodeop vmpyhSat; + +:vmpyh":sat" Rdd5,rs5,rt5 EndPacket is iclass=14 & op2127=0x28 & op13=0 & op0507=5 & Rdd5 & rt5 & rs5 & $(END_PACKET) { + Rdd5 = vmpyhSat(rs5, rt5); + build EndPacket; +} + +# (v2,14) vmpyh -- "Rxx32 += vmpyh ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 1 1 0 0 1 s s s s s P P + t t t t t 0 0 1 x x x x x + +define pcodeop vmpyhAdd; + +:vmpyh+= Rdd5,rs5,rt5 EndPacket is iclass=14 & op2127=0x39 & op13=0 & op0507=1 & Rdd5 & rdd5 & rt5 & rs5 & $(END_PACKET) { + Rdd5 = vmpyhAdd(rs5, rt5, rdd5); + build EndPacket; +} + +# (v2,14) vmpyh -- "Rxx32 += vmpyh ( Rs32 , Rt32 ) :<<1 :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 1 1 1 0 0 s s s s s P P + t t t t t 1 0 1 x x x x x + +define pcodeop vmpyhX2SatAdd; + +:vmpyh+=":<<1:sat" Rdd5,rs5,rt5 EndPacket is iclass=14 & op2127=0x3c & op13=0 & op0507=5 & Rdd5 & rdd5 & rt5 & rs5 & $(END_PACKET) { + Rdd5 = vmpyhX2SatAdd(rs5, rt5, rdd5); + build EndPacket; +} + +# (v2,14) vmpyh -- "Rxx32 += vmpyh ( Rs32 , Rt32 ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 1 1 0 0 0 s s s s s P P + t t t t t 1 0 1 x x x x x + +define pcodeop vmpyhSatAdd; + +:vmpyh+=":sat" Rdd5,rs5,rt5 EndPacket is iclass=14 & op2127=0x38 & op13=0 & op0507=5 & Rdd5 & rdd5 & rt5 & rs5 & $(END_PACKET) { + Rdd5 = vmpyhSatAdd(rs5, rt5, rdd5); + build EndPacket; +} + +# (v4,14) vmpyhsu -- "Rdd32 = vmpyhsu ( Rs32 , Rt32 ) :<<1 :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 0 1 1 0 0 s s s s s P P + t t t t t 1 1 1 d d d d d + +define pcodeop vmpyhsuX2Sat; + +:vmpyhsu":<<1:sat" Rdd5,rs5,rt5 EndPacket is iclass=14 & op2127=0x2c & op13=0 & op0507=7 & Rdd5 & rt5 & rs5 & $(END_PACKET) { + Rdd5 = vmpyhsuX2Sat(rs5, rt5); + build EndPacket; +} + +# (v4,14) vmpyhsu -- "Rdd32 = vmpyhsu ( Rs32 , Rt32 ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 0 1 0 0 0 s s s s s P P + t t t t t 1 1 1 d d d d d + +define pcodeop vmpyhsuSat; + +:vmpyhsu":sat" Rdd5,rs5,rt5 EndPacket is iclass=14 & op2127=0x28 & op13=0 & op0507=7 & Rdd5 & rt5 & rs5 & $(END_PACKET) { + Rdd5 = vmpyhsuSat(rs5, rt5); + build EndPacket; +} + +# (v4,14) vmpyhsu -- "Rxx32 += vmpyhsu ( Rs32 , Rt32 ) :<<1 :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 1 1 1 1 1 s s s s s P P + t t t t t 1 0 1 x x x x x + +define pcodeop vmpyhsuX2SatAdd; + +:vmpyhsu+=":<<1:sat" Rdd5,rs5,rt5 EndPacket is iclass=14 & op2127=0x3f & op13=0 & op0507=5 & Rdd5 & rdd5 & rt5 & rs5 & $(END_PACKET) { + Rdd5 = vmpyhsuX2SatAdd(rs5, rt5, rdd5); + build EndPacket; +} + +# (v4,14) vmpyhsu -- "Rxx32 += vmpyhsu ( Rs32 , Rt32 ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 1 1 0 1 1 s s s s s P P + t t t t t 1 0 1 x x x x x + +define pcodeop vmpyhsuSatAdd; + +:vmpyhsu+=":sat" Rdd5,rs5,rt5 EndPacket is iclass=14 & op2127=0x3b & op13=0 & op0507=5 & Rdd5 & rdd5 & rt5 & rs5 & $(END_PACKET) { + Rdd5 = vmpyhsuSatAdd(rs5, rt5, rdd5); + build EndPacket; +} + +# (v2,14) vmpyweh -- "Rdd32 = vmpyweh ( Rss32 , Rtt32 ) :<<1 :rnd :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 0 1 0 1 s s s s s P P + t t t t t 1 0 1 d d d d d + +define pcodeop vmpywehX2RndSat; + +:vmpyweh":<<1:rnd:sat" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x45 & op13=0 & op0507=5 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vmpywehX2RndSat(rss5, rtt5); + build EndPacket; +} + +# (v2,14) vmpyweh -- "Rdd32 = vmpyweh ( Rss32 , Rtt32 ) :<<1 :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 0 1 0 0 s s s s s P P + t t t t t 1 0 1 d d d d d + +define pcodeop vmpywehX2Sat; + +:vmpyweh":<<1:sat" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x44 & op13=0 & op0507=5 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vmpywehX2Sat(rss5, rtt5); + build EndPacket; +} + +# (v2,14) vmpyweh -- "Rdd32 = vmpyweh ( Rss32 , Rtt32 ) :rnd :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 0 0 0 1 s s s s s P P + t t t t t 1 0 1 d d d d d + +define pcodeop vmpywehRndSat; + +:vmpyweh":rnd:sat" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x41 & op13=0 & op0507=5 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vmpywehRndSat(rss5, rtt5); + build EndPacket; +} + +# (v2,14) vmpyweh -- "Rdd32 = vmpyweh ( Rss32 , Rtt32 ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 0 0 0 0 s s s s s P P + t t t t t 1 0 1 d d d d d + +define pcodeop vmpywehSat; + +:vmpyweh":sat" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x40 & op13=0 & op0507=5 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vmpywehSat(rss5, rtt5); + build EndPacket; +} + +# (v2,14) vmpyweh -- "Rxx32 += vmpyweh ( Rss32 , Rtt32 ) :<<1 :rnd :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 1 0 1 0 1 s s s s s P P + t t t t t 1 0 1 x x x x x + +define pcodeop vmpywehX2RndSatAdd; + +:vmpyweh+=":<<1:rnd:sat" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x55 & op13=0 & op0507=5 & Rdd5 & rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vmpywehX2RndSatAdd(rss5, rtt5, rdd5); + build EndPacket; +} + +# (v2,14) vmpyweh -- "Rxx32 += vmpyweh ( Rss32 , Rtt32 ) :<<1 :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 1 0 1 0 0 s s s s s P P + t t t t t 1 0 1 x x x x x + +define pcodeop vmpywehX2SatAdd; + +:vmpyweh+=":<<1:sat" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x54 & op13=0 & op0507=5 & Rdd5 & rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vmpywehX2SatAdd(rss5, rtt5, rdd5); + build EndPacket; +} + +# (v2,14) vmpyweh -- "Rxx32 += vmpyweh ( Rss32 , Rtt32 ) :rnd :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 1 0 0 0 1 s s s s s P P + t t t t t 1 0 1 x x x x x + +define pcodeop vmpywehRndSatAdd; + +:vmpyweh+=":rnd:sat" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x51 & op13=0 & op0507=5 & Rdd5 & rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vmpywehRndSatAdd(rss5, rtt5, rdd5); + build EndPacket; +} + +# (v2,14) vmpyweh -- "Rxx32 += vmpyweh ( Rss32 , Rtt32 ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 1 0 0 0 0 s s s s s P P + t t t t t 1 0 1 x x x x x + +define pcodeop vmpywehSatAdd; + +:vmpyweh+=":sat" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x50 & op13=0 & op0507=5 & Rdd5 & rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vmpywehSatAdd(rss5, rtt5, rdd5); + build EndPacket; +} + +# (v2,14) vmpyweuh -- "Rdd32 = vmpyweuh ( Rss32 , Rtt32 ) :<<1 :rnd :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 0 1 1 1 s s s s s P P + t t t t t 1 0 1 d d d d d + +define pcodeop vmpyweuhX2RndSat; + +:vmpyweuh":<<1:rnd:sat" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x47 & op13=0 & op0507=5 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vmpyweuhX2RndSat(rss5, rtt5); + build EndPacket; +} + +# (v2,14) vmpyweuh -- "Rdd32 = vmpyweuh ( Rss32 , Rtt32 ) :<<1 :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 0 1 1 0 s s s s s P P + t t t t t 1 0 1 d d d d d + +define pcodeop vmpyweuhX2Sat; + +:vmpyweuh":<<1:sat" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x46 & op13=0 & op0507=5 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vmpyweuhX2Sat(rss5, rtt5); + build EndPacket; +} + +# (v2,14) vmpyweuh -- "Rdd32 = vmpyweuh ( Rss32 , Rtt32 ) :rnd :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 0 0 1 1 s s s s s P P + t t t t t 1 0 1 d d d d d + +define pcodeop vmpyweuhRndSat; + +:vmpyweuh":rnd:sat" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x43 & op13=0 & op0507=5 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vmpyweuhRndSat(rss5, rtt5); + build EndPacket; +} + +# (v2,14) vmpyweuh -- "Rdd32 = vmpyweuh ( Rss32 , Rtt32 ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 0 0 1 0 s s s s s P P + t t t t t 1 0 1 d d d d d + +define pcodeop vmpyweuhSat; + +:vmpyweuh":sat" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x42 & op13=0 & op0507=5 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vmpyweuhSat(rss5, rtt5); + build EndPacket; +} + +# (v2,14) vmpyweuh -- "Rxx32 += vmpyweuh ( Rss32 , Rtt32 ) :<<1 :rnd :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 1 0 1 1 1 s s s s s P P + t t t t t 1 0 1 x x x x x + +define pcodeop vmpyweuhX2RndSatAdd; + +:vmpyweuh+=":<<1:rnd:sat" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x57 & op13=0 & op0507=5 & Rdd5 & rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vmpyweuhX2RndSatAdd(rss5, rtt5, rdd5); + build EndPacket; +} + +# (v2,14) vmpyweuh -- "Rxx32 += vmpyweuh ( Rss32 , Rtt32 ) :<<1 :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 1 0 1 1 0 s s s s s P P + t t t t t 1 0 1 x x x x x + +define pcodeop vmpyweuhX2SatAdd; + +:vmpyweuh+=":<<1:sat" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x56 & op13=0 & op0507=5 & Rdd5 & rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vmpyweuhX2SatAdd(rss5, rtt5, rdd5); + build EndPacket; +} + +# (v2,14) vmpyweuh -- "Rxx32 += vmpyweuh ( Rss32 , Rtt32 ) :rnd :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 1 0 0 1 1 s s s s s P P + t t t t t 1 0 1 x x x x x + +define pcodeop vmpyweuhRndSatAdd; + +:vmpyweuh+=":rnd:sat" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x53 & op13=0 & op0507=5 & Rdd5 & rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vmpyweuhRndSatAdd(rss5, rtt5, rdd5); + build EndPacket; +} + +# (v2,14) vmpyweuh -- "Rxx32 += vmpyweuh ( Rss32 , Rtt32 ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 1 0 0 1 0 s s s s s P P + t t t t t 1 0 1 x x x x x + +define pcodeop vmpyweuhSatAdd; + +:vmpyweuh+=":sat" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x52 & op13=0 & op0507=5 & Rdd5 & rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vmpyweuhSatAdd(rss5, rtt5, rdd5); + build EndPacket; +} + +# (v2,14) vmpywoh -- "Rdd32 = vmpywoh ( Rss32 , Rtt32 ) :<<1 :rnd :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 0 1 0 1 s s s s s P P + t t t t t 1 1 1 d d d d d + +define pcodeop vmpywohX2RndSat; + +:vmpywoh":<<1:rnd:sat" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x45 & op13=0 & op0507=7 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vmpywohX2RndSat(rss5, rtt5); + build EndPacket; +} + +# (v2,14) vmpywoh -- "Rdd32 = vmpywoh ( Rss32 , Rtt32 ) :<<1 :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 0 1 0 0 s s s s s P P + t t t t t 1 1 1 d d d d d + +define pcodeop vmpywohX2Sat; + +:vmpywoh":<<1:sat" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x44 & op13=0 & op0507=7 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vmpywohX2Sat(rss5, rtt5); + build EndPacket; +} + +# (v2,14) vmpywoh -- "Rdd32 = vmpywoh ( Rss32 , Rtt32 ) :rnd :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 0 0 0 1 s s s s s P P + t t t t t 1 1 1 d d d d d + +define pcodeop vmpywohRndSat; + +:vmpywoh":rnd:sat" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x41 & op13=0 & op0507=7 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vmpywohRndSat(rss5, rtt5); + build EndPacket; +} + +# (v2,14) vmpywoh -- "Rdd32 = vmpywoh ( Rss32 , Rtt32 ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 0 0 0 0 s s s s s P P + t t t t t 1 1 1 d d d d d + +define pcodeop vmpywohSat; + +:vmpywoh":sat" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x40 & op13=0 & op0507=7 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vmpywohSat(rss5, rtt5); + build EndPacket; +} + +# (v2,14) vmpywoh -- "Rxx32 += vmpywoh ( Rss32 , Rtt32 ) :<<1 :rnd :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 1 0 1 0 1 s s s s s P P + t t t t t 1 1 1 x x x x x + +define pcodeop vmpywohX2RndSatAdd; + +:vmpywoh+=":<<1:rnd:sat" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x55 & op13=0 & op0507=7 & Rdd5 & rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vmpywohX2RndSatAdd(rss5, rtt5, rdd5); + build EndPacket; +} + +# (v2,14) vmpywoh -- "Rxx32 += vmpywoh ( Rss32 , Rtt32 ) :<<1 :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 1 0 1 0 0 s s s s s P P + t t t t t 1 1 1 x x x x x + +define pcodeop vmpywohX2SatAdd; + +:vmpywoh+=":<<1:sat" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x54 & op13=0 & op0507=7 & Rdd5 & rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vmpywohX2SatAdd(rss5, rtt5, rdd5); + build EndPacket; +} + +# (v2,14) vmpywoh -- "Rxx32 += vmpywoh ( Rss32 , Rtt32 ) :rnd :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 1 0 0 0 1 s s s s s P P + t t t t t 1 1 1 x x x x x + +define pcodeop vmpywohRndSatAdd; + +:vmpywoh+=":rnd:sat" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x51 & op13=0 & op0507=7 & Rdd5 & rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vmpywohRndSatAdd(rss5, rtt5, rdd5); + build EndPacket; +} + +# (v2,14) vmpywoh -- "Rxx32 += vmpywoh ( Rss32 , Rtt32 ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 1 0 0 0 0 s s s s s P P + t t t t t 1 1 1 x x x x x + +define pcodeop vmpywohSatAdd; + +:vmpywoh+=":sat" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x50 & op13=0 & op0507=7 & Rdd5 & rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vmpywohSatAdd(rss5, rtt5, rdd5); + build EndPacket; +} + +# (v2,14) vmpywouh -- "Rdd32 = vmpywouh ( Rss32 , Rtt32 ) :<<1 :rnd :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 0 1 1 1 s s s s s P P + t t t t t 1 1 1 d d d d d + +:vmpywouh":<<1:rnd:sat" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x47 & op13=0 & op0507=7 & Rdd5 & rtt5 & rss5 & $(END_PACKET) +unimpl + +# (v2,14) vmpywouh -- "Rdd32 = vmpywouh ( Rss32 , Rtt32 ) :<<1 :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 0 1 1 0 s s s s s P P + t t t t t 1 1 1 d d d d d + +:vmpywouh":<<1:sat" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x46 & op13=0 & op0507=7 & Rdd5 & rtt5 & rss5 & $(END_PACKET) +unimpl + +# (v2,14) vmpywouh -- "Rdd32 = vmpywouh ( Rss32 , Rtt32 ) :rnd :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 0 0 1 1 s s s s s P P + t t t t t 1 1 1 d d d d d + +:vmpywouh":rnd:sat" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x43 & op13=0 & op0507=7 & Rdd5 & rtt5 & rss5 & $(END_PACKET) +unimpl + +# (v2,14) vmpywouh -- "Rdd32 = vmpywouh ( Rss32 , Rtt32 ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 0 0 1 0 s s s s s P P + t t t t t 1 1 1 d d d d d + +:vmpywouh":sat" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x42 & op13=0 & op0507=7 & Rdd5 & rtt5 & rss5 & $(END_PACKET) +unimpl + +# (v2,14) vmpywouh -- "Rxx32 += vmpywouh ( Rss32 , Rtt32 ) :<<1 :rnd :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 1 0 1 1 1 s s s s s P P + t t t t t 1 1 1 x x x x x + +:vmpywouh+=":<<1:rnd:sat" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x57 & op13=0 & op0507=7 & Rdd5 & rtt5 & rss5 & $(END_PACKET) +unimpl + +# (v2,14) vmpywouh -- "Rxx32 += vmpywouh ( Rss32 , Rtt32 ) :<<1 :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 1 0 1 1 0 s s s s s P P + t t t t t 1 1 1 x x x x x + +:vmpywouh+=":<<1:sat" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x56 & op13=0 & op0507=7 & Rdd5 & rtt5 & rss5 & $(END_PACKET) +unimpl + +# (v2,14) vmpywouh -- "Rxx32 += vmpywouh ( Rss32 , Rtt32 ) :rnd :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 1 0 0 1 1 s s s s s P P - t t t t t 1 1 1 x x x x x + +:vmpywouh+=":rnd:sat" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x53 & op13=0 & op0507=7 & Rdd5 & rtt5 & rss5 & $(END_PACKET) +unimpl + +# (v2,14) vmpywouh -- "Rxx32 += vmpywouh ( Rss32 , Rtt32 ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 1 0 0 1 0 s s s s s P P + t t t t t 1 1 1 x x x x x + +:vmpywouh+=":sat" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x52 & op13=0 & op0507=7 & Rdd5 & rtt5 & rss5 & $(END_PACKET) +unimpl + +# (v2,13) vmux -- "Rdd32 = vmux ( Pu4 , Rss32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 0 1 + + + s s s s s P P + t t t t t + u u d d d d d + +define pcodeop vmux; + +:vmux Rdd5,pu0506,rss5,rtt5 EndPacket is iclass=13 & op2127=0x08 & op13=0 & op7=0 & Rdd5 & rss5 & rtt5 & pu0506 & $(END_PACKET) { + Rdd5 = vmux(pu0506,rss5,rtt5); + build EndPacket; +} + +# (v2,15) vnavgh -- "Rd32 = vnavgh ( Rt32 , Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 1 0 1 1 1 + 1 1 s s s s s P P + t t t t t + + + d d d d d + +:vnavgh Rd5,rt5,rs5 EndPacket is iclass=15 & op2127=0x3b & op13=0 & op0507=0 & Rd5 & rt5 & rs5 & $(END_PACKET) +{ + Rd5[0,16] = (rt5[0,16] - rs5[0,16]) >> 1; + Rd5[16,16] = (rt5[16,16] - rs5[16,16]) >> 1; + build EndPacket; +} + +# (v2,13) vnavgh -- "Rdd32 = vnavgh ( Rtt32 , Rss32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 1 1 0 0 s s s s s P P + t t t t t 0 0 0 d d d d d + +:vnavgh Rdd5,rtt5,rss5 EndPacket is iclass=13 & op2127=0x1c & op13=0 & op0507=0 & Rdd5 & rtt5 & rss5 & $(END_PACKET) +{ + Rdd5[0,16] = (rtt5[0,16] - rss5[0,16]) >> 1; + Rdd5[16,16] = (rtt5[16,16] - rss5[16,16]) >> 1; + Rdd5[32,16] = (rtt5[32,16] - rss5[32,16]) >> 1; + Rdd5[48,16] = (rtt5[48,16] - rss5[48,16]) >> 1; + build EndPacket; +} + +# (v2,13) vnavgh -- "Rdd32 = vnavgh ( Rtt32 , Rss32 ) :crnd :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 1 1 0 0 s s s s s P P + t t t t t 0 1 0 d d d d d + +define pcodeop vnavghCrndSat; + +:vnavgh":crnd:sat" Rdd5,rtt5,rss5 EndPacket is iclass=13 & op2127=0x1c & op13=0 & op0507=2 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vnavghCrndSat(rtt5, rss5); + build EndPacket; +} + +# (v2,13) vnavgh -- "Rdd32 = vnavgh ( Rtt32 , Rss32 ) :rnd :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 1 1 0 0 s s s s s P P + t t t t t 0 0 1 d d d d d + +define pcodeop vnavghRndSat; + +:vnavgh":rnd:sat" Rdd5,rtt5,rss5 EndPacket is iclass=13 & op2127=0x1c & op13=0 & op0507=1 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vnavghRndSat(rtt5, rss5); + build EndPacket; +} + +# (v2,13) vnavgw -- "Rdd32 = vnavgw ( Rtt32 , Rss32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 1 1 0 0 s s s s s P P + t t t t t 0 1 1 d d d d d + +:vnavgw Rdd5,rtt5,rss5 EndPacket is iclass=13 & op2127=0x1c & op13=0 & op0507=3 & Rdd5 & rtt5 & rss5 & $(END_PACKET) +{ + Rdd5[0,32] = (rtt5[0,32] - rss5[0,32]) >> 1; + Rdd5[32,32] = (rtt5[32,32] - rss5[32,32]) >> 1; + build EndPacket; +} + +# (v2,13) vnavgw -- "Rdd32 = vnavgw ( Rtt32 , Rss32 ) :crnd :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 1 1 0 0 s s s s s P P + t t t t t 1 1 + d d d d d + +define pcodeop vnavgwCrndSat; + +:vnavgw":crnd:sat" Rdd5,rtt5,rss5 EndPacket is iclass=13 & op2127=0x1c & op13=0 & op0507=6 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vnavgwCrndSat(rtt5, rss5); + build EndPacket; +} + +# (v2,13) vnavgw -- "Rdd32 = vnavgw ( Rtt32 , Rss32 ) :rnd :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 1 1 0 0 s s s s s P P + t t t t t 1 0 + d d d d d + +define pcodeop vnavgwRndSat; + +:vnavgw":rnd:sat" Rdd5,rtt5,rss5 EndPacket is iclass=13 & op2127=0x1c & op13=0 & op0507=4 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vnavgwRndSat(rtt5, rss5); + build EndPacket; +} + +# (v4,14) vpmpyh -- "Rdd32 = vpmpyh ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 0 1 1 1 0 s s s s s P P + t t t t t 1 1 1 d d d d d + +:vpmpyh Rdd5,rs5,rt5 EndPacket is iclass=14 & op2127=0x2e & op13=0 & op0507=7 & Rdd5 & rt5 & rs5 & $(END_PACKET) +unimpl + +# (v4,14) vpmpyh -- "Rxx32 ^= vpmpyh ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 1 1 1 1 0 1 s s s s s P P + t t t t t 1 1 1 x x x x x + +:vpmpyh"^=" Rdd5,rs5,rt5 EndPacket is iclass=14 & op2127=0x3d & op13=0 & op0507=7 & Rdd5 & rt5 & rs5 & $(END_PACKET) +unimpl + +# (v4,14) vraddh -- "Rd32 = vraddh ( Rss32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 1 0 + 1 s s s s s P P + t t t t t 1 1 1 d d d d d + +:vraddh Rd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x49 & op13=0 & op0507=7 & Rd5 & rtt5 & rss5 & $(END_PACKET) { + tmp:4 = sext(rss5[0,16]); + tmp = tmp + sext(rss5[16,16]); + tmp = tmp + sext(rss5[32,16]); + tmp = tmp + sext(rss5[48,16]); + tmp = tmp + sext(rtt5[0,16]); + tmp = tmp + sext(rtt5[16,16]); + tmp = tmp + sext(rtt5[32,16]); + tmp = tmp + sext(rtt5[48,16]); + Rd5 = tmp; + build EndPacket; +} + +# (v2,14) vraddub -- "Rdd32 = vraddub ( Rss32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 0 0 1 0 s s s s s P P + t t t t t 0 0 1 d d d d d + +:vraddub Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x42 & op13=0 & op0507=1 & Rdd5 & rtt5 & rss5 & $(END_PACKET) +unimpl + +# (v2,14) vraddub -- "Rxx32 += vraddub ( Rss32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 1 0 0 1 0 s s s s s P P + t t t t t 0 0 1 x x x x x + +:vraddub+= Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x52 & op13=0 & op0507=1 & Rdd5 & rtt5 & rss5 & $(END_PACKET) +unimpl + +# (v4,14) vradduh -- "Rd32 = vradduh ( Rss32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 1 0 + + s s s s s P P + t t t t t + 0 1 d d d d d + +:vradduh Rd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x48 & op13=0 & op0507=1 & Rd5 & rtt5 & rss5 & $(END_PACKET) +unimpl + +# (v2,14) vrcmpyi -- "Rdd32 = vrcmpyi ( Rss32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 0 0 0 0 s s s s s P P + t t t t t 0 0 0 d d d d d + +define pcodeop vrcmpyi; + +:vrcmpyi Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x40 & op13=0 & op0507=0 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vrcmpyi(rss5, rtt5); + build EndPacket; +} + +# (v2,14) vrcmpyi -- "Rdd32 = vrcmpyi ( Rss32 , Rtt32 * )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 0 0 1 0 s s s s s P P + t t t t t 0 0 0 d d d d d + +:vrcmpyi Rdd5,rss5,Rtt5Conjugate EndPacket is iclass=14 & op2127=0x42 & op13=0 & op0507=0 & Rdd5 & Rtt5Conjugate & rss5 & $(END_PACKET) { + Rdd5 = vrcmpyi(rss5, Rtt5Conjugate); + build EndPacket; +} + +# (v2,14) vrcmpyi -- "Rxx32 += vrcmpyi ( Rss32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 1 0 0 0 0 s s s s s P P + t t t t t 0 0 0 x x x x x + +define pcodeop vrcmpyiAdd; + +:vrcmpyi+= Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x50 & op13=0 & op0507=0 & Rdd5 & rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vrcmpyiAdd(rss5, rtt5, rdd5); + build EndPacket; +} + +# (v2,14) vrcmpyi -- "Rxx32 += vrcmpyi ( Rss32 , Rtt32 * )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 1 0 0 1 0 s s s s s P P + t t t t t 0 0 0 x x x x x + +:vrcmpyi+= Rdd5,rss5,Rtt5Conjugate EndPacket is iclass=14 & op2127=0x52 & op13=0 & op0507=0 & rdd5 & Rdd5 & Rtt5Conjugate & rss5 & $(END_PACKET) { + Rdd5 = vrcmpyiAdd(rss5, Rtt5Conjugate, rdd5); + build EndPacket; +} + +# (v2,14) vrcmpyr -- "Rdd32 = vrcmpyr ( Rss32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 0 0 0 0 s s s s s P P + t t t t t 0 0 1 d d d d d + +define pcodeop vrcmpyr; + +:vrcmpyr Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x40 & op13=0 & op0507=1 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vrcmpyr(rss5, rtt5); + build EndPacket; +} + +# (v2,14) vrcmpyr -- "Rdd32 = vrcmpyr ( Rss32 , Rtt32 * )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 0 0 1 1 s s s s s P P + t t t t t 0 0 1 d d d d d + +:vrcmpyr Rdd5,rss5,Rtt5Conjugate EndPacket is iclass=14 & op2127=0x43 & op13=0 & op0507=1 & Rdd5 & Rtt5Conjugate & rss5 & $(END_PACKET) { + Rdd5 = vrcmpyr(rss5, Rtt5Conjugate); + build EndPacket; +} + +# (v2,14) vrcmpyr -- "Rxx32 += vrcmpyr ( Rss32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 1 0 0 0 0 s s s s s P P + t t t t t 0 0 1 x x x x x + +define pcodeop vrcmpyrAdd; + +:vrcmpyr+= Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x50 & op13=0 & op0507=1 & rdd5 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vrcmpyrAdd(rss5, rtt5, rdd5); + build EndPacket; +} + +# (v2,14) vrcmpyr -- "Rxx32 += vrcmpyr ( Rss32 , Rtt32 * )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 1 0 0 1 1 s s s s s P P + t t t t t 0 0 1 x x x x x + +:vrcmpyr+= Rdd5,rss5,Rtt5Conjugate EndPacket is iclass=14 & op2127=0x53 & op13=0 & op0507=1 & rdd5 & Rdd5 & Rtt5Conjugate & rss5 & $(END_PACKET) { + Rdd5 = vrcmpyrAdd(rss5, Rtt5Conjugate, rdd5); + build EndPacket; +} + +# (v4,14) vrcmpys -- "Rd32 = vrcmpys ( Rss32 , Rtt32 ) :<<1 :rnd :sat :raw :hi" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 1 1 + 1 s s s s s P P + t t t t t 1 1 0 d d d d d + +:vrcmpys":<<1:rnd:sat:raw:hi" Rd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x4d & op13=0 & op0507=6 & Rd5 & rtt5 & rss5 & $(END_PACKET) +unimpl + +# (v4,14) vrcmpys -- "Rd32 = vrcmpys ( Rss32 , Rtt32 ) :<<1 :rnd :sat :raw :lo" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 1 1 + 1 s s s s s P P + t t t t t 1 1 1 d d d d d + +:vrcmpys":<<1:rnd:sat:raw:lo" Rd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x4d & op13=0 & op0507=7 & Rd5 & rtt5 & rss5 & $(END_PACKET) +unimpl + +# (v4,14) vrcmpys -- "Rdd32 = vrcmpys ( Rss32 , Rtt32 ) :<<1 :sat :raw :hi" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 0 1 0 1 s s s s s P P + t t t t t 1 0 0 d d d d d + +:vrcmpys":<<1:sat:raw:hi" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x45 & op13=0 & op0507=4 & Rdd5 & rtt5 & rss5 & $(END_PACKET) +unimpl + +# (v4,14) vrcmpys -- "Rdd32 = vrcmpys ( Rss32 , Rtt32 ) :<<1 :sat :raw :lo" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 0 1 1 1 s s s s s P P + t t t t t 1 0 0 d d d d d + +:vrcmpys":<<1:sat:raw:lo" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x47 & op13=0 & op0507=4 & Rdd5 & rtt5 & rss5 & $(END_PACKET) +unimpl + +# (v4,14) vrcmpys -- "Rxx32 += vrcmpys ( Rss32 , Rtt32 ) :<<1 :sat :raw :hi" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 1 0 1 0 1 s s s s s P P + t t t t t 1 0 0 x x x x x + +:vrcmpys+=":<<1:sat:raw:hi" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x55 & op13=0 & op0507=4 & Rdd5 & rtt5 & rss5 & $(END_PACKET) +unimpl + +# (v4,14) vrcmpys -- "Rxx32 += vrcmpys ( Rss32 , Rtt32 ) :<<1 :sat :raw :lo" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 1 0 1 1 1 s s s s s P P + t t t t t 1 0 0 x x x x x + +:vrcmpys+=":<<1:sat:raw:lo" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x57 & op13=0 & op0507=4 & Rdd5 & rtt5 & rss5 & $(END_PACKET) +unimpl + +# (v4,12) vrcnegh -- "Rxx32 += vrcnegh ( Rss32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 1 0 1 1 0 0 1 s s s s s P P 1 t t t t t 1 1 1 x x x x x + +:vrcnegh+= Rdd5,rss5,rt5 EndPacket is iclass=12 & op2127=0x59 & op13=1 & op0507=7 & Rdd5 & rt5 & rss5 & $(END_PACKET) +unimpl + +# (v4,12) vrcrotate -- "Rdd32 = vrcrotate ( Rss32 , Rt32 , #u2 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 0 1 1 1 1 + s s s s s P P i t t t t t 1 1 i d d d d d + +:vrcrotate Rdd5,rss5,rt5,Uimm2_13_05 EndPacket is iclass=12 & op2127=0x1e & op0607=3 & Uimm2_13_05 & Rdd5 & rt5 & rss5 & $(END_PACKET) +unimpl + +# (v4,12) vrcrotate -- "Rxx32 += vrcrotate ( Rss32 , Rt32 , #u2 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 1 0 1 1 1 0 1 s s s s s P P i t t t t t + + i x x x x x + +:vrcrotate+= Rdd5,rss5,rt5,Uimm2_13_05 EndPacket is iclass=12 & op2127=0x5d & op0607=0 & Uimm2_13_05 & Rdd5 & rt5 & rss5 & $(END_PACKET) +unimpl + +# (v4,12) vrmaxh -- "Rxx32 = vrmaxh ( Rss32 , Ru32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 1 0 1 1 0 0 1 s s s s s P P 0 x x x x x 0 0 1 u u u u u + +:vrmaxh Rdd0812,rss5,ru5 EndPacket is iclass=12 & op2127=0x59 & op13=0 & op0507=1 & Rdd0812 & ru5 & rss5 & $(END_PACKET) +unimpl + +# (v4,12) vrmaxuh -- "Rxx32 = vrmaxuh ( Rss32 , Ru32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 1 0 1 1 0 0 1 s s s s s P P 1 x x x x x 0 0 1 u u u u u + +:vrmaxuh Rdd0812,rss5,ru5 EndPacket is iclass=12 & op2127=0x59 & op13=1 & op0507=1 & Rdd0812 & ru5 & rss5 & $(END_PACKET) +unimpl + +# (v4,12) vrmaxuw -- "Rxx32 = vrmaxuw ( Rss32 , Ru32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 1 0 1 1 0 0 1 s s s s s P P 1 x x x x x 0 1 0 u u u u u + +:vrmaxuw Rdd0812,rss5,ru5 EndPacket is iclass=12 & op2127=0x59 & op13=1 & op0507=2 & Rdd0812 & ru5 & rss5 & $(END_PACKET) +unimpl + +# (v4,12) vrmaxw -- "Rxx32 = vrmaxw ( Rss32 , Ru32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 1 0 1 1 0 0 1 s s s s s P P 0 x x x x x 0 1 0 u u u u u + +:vrmaxw Rdd0812,rss5,ru5 EndPacket is iclass=12 & op2127=0x59 & op13=0 & op0507=2 & Rdd0812 & ru5 & rss5 & $(END_PACKET) +unimpl + +# (v4,12) vrminh -- "Rxx32 = vrminh ( Rss32 , Ru32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 1 0 1 1 0 0 1 s s s s s P P 0 x x x x x 1 0 1 u u u u u + +:vrminh Rdd0812,rss5,ru5 EndPacket is iclass=12 & op2127=0x59 & op13=0 & op0507=5 & Rdd0812 & ru5 & rss5 & $(END_PACKET) +unimpl + +# (v4,12) vrminuh -- "Rxx32 = vrminuh ( Rss32 , Ru32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 1 0 1 1 0 0 1 s s s s s P P 1 x x x x x 1 0 1 u u u u u + +:vrminuh Rdd0812,rss5,ru5 EndPacket is iclass=12 & op2127=0x59 & op13=1 & op0507=5 & Rdd0812 & ru5 & rss5 & $(END_PACKET) +unimpl + +# (v4,12) vrminuw -- "Rxx32 = vrminuw ( Rss32 , Ru32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 1 0 1 1 0 0 1 s s s s s P P 1 x x x x x 1 1 0 u u u u u + +:vrminuw Rdd0812,rss5,ru5 EndPacket is iclass=12 & op2127=0x59 & op13=1 & op0507=6 & Rdd0812 & ru5 & rss5 & $(END_PACKET) +unimpl + +# (v4,12) vrminw -- "Rxx32 = vrminw ( Rss32 , Ru32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 1 0 1 1 0 0 1 s s s s s P P 0 x x x x x 1 1 0 u u u u u + +:vrminw Rdd0812,rss5,ru5 EndPacket is iclass=12 & op2127=0x59 & op13=0 & op0507=6 & Rdd0812 & ru5 & rss5 & $(END_PACKET) +unimpl + +# (v4,14) vrmpybsu -- "Rdd32 = vrmpybsu ( Rss32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 0 1 1 0 s s s s s P P + t t t t t 0 0 1 d d d d d + +:vrmpybsu Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x46 & op13=0 & op0507=1 & Rdd5 & rtt5 & rss5 & $(END_PACKET) +unimpl + +# (v4,14) vrmpybsu -- "Rxx32 += vrmpybsu ( Rss32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 1 0 1 1 0 s s s s s P P + t t t t t 0 0 1 x x x x x + +:vrmpybsu+= Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x56 & op13=0 & op0507=1 & Rdd5 & rtt5 & rss5 & $(END_PACKET) +unimpl + +# (v4,14) vrmpybu -- "Rdd32 = vrmpybu ( Rss32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 0 1 0 0 s s s s s P P + t t t t t 0 0 1 d d d d d + +:vrmpybu Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x44 & op13=0 & op0507=1 & Rdd5 & rtt5 & rss5 & $(END_PACKET) +unimpl + +# (v4,14) vrmpybu -- "Rxx32 += vrmpybu ( Rss32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 1 0 1 0 0 s s s s s P P + t t t t t 0 0 1 x x x x x + +:vrmpybu+= Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x54 & op13=0 & op0507=1 & Rdd5 & rtt5 & rss5 & $(END_PACKET) +unimpl + +# (v2,14) vrmpyh -- "Rdd32 = vrmpyh ( Rss32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 0 0 0 0 s s s s s P P + t t t t t 0 1 0 d d d d d + +define pcodeop vrmpyh; + +:vrmpyh Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x40 & op13=0 & op0507=2 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vrmpyh(rss5, rtt5); + build EndPacket; +} + +# (v2,14) vrmpyh -- "Rxx32 += vrmpyh ( Rss32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 1 0 0 0 0 s s s s s P P + t t t t t 0 1 0 x x x x x + +define pcodeop vrmpyhAdd; + +:vrmpyh+= Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x50 & op13=0 & op0507=2 & rdd5 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vrmpyhAdd(rss5, rtt5, rdd5); + build EndPacket; +} + +# (v4,14) vrmpyweh -- "Rdd32 = vrmpyweh ( Rss32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 0 0 1 0 s s s s s P P + t t t t t 1 0 0 d d d d d + +:vrmpyweh Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x42 & op13=0 & op0507=4 & Rdd5 & rtt5 & rss5 & $(END_PACKET) +unimpl + +# (v4,14) vrmpyweh -- "Rdd32 = vrmpyweh ( Rss32 , Rtt32 ) :<<1" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 0 1 1 0 s s s s s P P + t t t t t 1 0 0 d d d d d + +:vrmpyweh":<<1" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x46 & op13=0 & op0507=4 & Rdd5 & rtt5 & rss5 & $(END_PACKET) +unimpl + +# (v4,14) vrmpyweh -- "Rxx32 += vrmpyweh ( Rss32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 1 0 0 0 1 s s s s s P P + t t t t t 1 1 0 x x x x x + +:vrmpyweh+= Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x51 & op13=0 & op0507=6 & Rdd5 & rtt5 & rss5 & $(END_PACKET) +unimpl + +# (v4,14) vrmpyweh -- "Rxx32 += vrmpyweh ( Rss32 , Rtt32 ) :<<1" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 1 0 1 0 1 s s s s s P P + t t t t t 1 1 0 x x x x x + +:vrmpyweh+=":<<1" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x55 & op13=0 & op0507=6 & Rdd5 & rtt5 & rss5 & $(END_PACKET) +unimpl + +# (v4,14) vrmpywoh -- "Rdd32 = vrmpywoh ( Rss32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 0 0 0 1 s s s s s P P + t t t t t 0 1 0 d d d d d + +:vrmpywoh Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x41 & op13=0 & op0507=2 & Rdd5 & rtt5 & rss5 & $(END_PACKET) +unimpl + +# (v4,14) vrmpywoh -- "Rdd32 = vrmpywoh ( Rss32 , Rtt32 ) :<<1" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 0 1 0 1 s s s s s P P + t t t t t 0 1 0 d d d d d + +:vrmpywoh":<<1" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x45 & op13=0 & op0507=2 & Rdd5 & rtt5 & rss5 & $(END_PACKET) +unimpl + +# (v4,14) vrmpywoh -- "Rxx32 += vrmpywoh ( Rss32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 1 0 0 1 1 s s s s s P P + t t t t t 1 1 0 x x x x x + +:vrmpywoh+= Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x53 & op13=0 & op0507=6 & Rdd5 & rtt5 & rss5 & $(END_PACKET) +unimpl + +# (v4,14) vrmpywoh -- "Rxx32 += vrmpywoh ( Rss32 , Rtt32 ) :<<1" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 1 0 1 1 1 s s s s s P P + t t t t t 1 1 0 x x x x x + +:vrmpywoh+=":<<1" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x57 & op13=0 & op0507=6 & Rdd5 & rtt5 & rss5 & $(END_PACKET) +unimpl + +# (v2,8) vrndwh -- "Rd32 = vrndwh ( Rss32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 0 0 0 1 0 0 s s s s s P P + + + + + + 1 0 + d d d d d + +define pcodeop vrndwh; + +:vrndwh Rd5,rss5 EndPacket is iclass=8 & op2127=0x44 & op0513=0x04 & Rd5 & rss5 & $(END_PACKET) { + Rd5 = vrndwh(rss5); + build EndPacket; +} + +# (v2,8) vrndwh -- "Rd32 = vrndwh ( Rss32 ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 0 0 0 1 0 0 s s s s s P P + + + + + + 1 1 + d d d d d + +define pcodeop vrndwhSat; + +:vrndwh":sat" Rd5,rss5 EndPacket is iclass=8 & op2127=0x44 & op0513=0x06 & Rd5 & rss5 & $(END_PACKET) { + Rd5 = vrndwhSat(rss5); + build EndPacket; +} + +# (v2,14) vrsadub -- "Rdd32 = vrsadub ( Rss32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 0 0 1 0 s s s s s P P + t t t t t 0 1 0 d d d d d + +:vrsadub Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x42 & op13=0 & op0507=2 & Rdd5 & rtt5 & rss5 & $(END_PACKET) +unimpl + +# (v2,14) vrsadub -- "Rxx32 += vrsadub ( Rss32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 1 0 0 1 0 s s s s s P P + t t t t t 0 1 0 x x x x x + +:vrsadub+= Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x52 & op13=0 & op0507=2 & Rdd5 & rtt5 & rss5 & $(END_PACKET) +unimpl + +# (v2,8) vsathb -- "Rd32 = vsathb ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 1 0 0 1 0 + s s s s s P P + + + + + + 0 0 + d d d d d + +define pcodeop vsathb; + +:vsathb Rd5,rs5 EndPacket is iclass=8 & op2127=0x64 & op0513=0 & Rd5 & rs5 & $(END_PACKET) { + Rd5 = vsathb(rs5); + build EndPacket; +} + +# (v2,8) vsathb -- "Rd32 = vsathb ( Rss32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 0 0 0 0 0 0 s s s s s P P + + + + + + 1 1 + d d d d d + + +:vsathb Rd5,rss5 EndPacket is iclass=8 & op2127=0x40 & op0513=0x06 & Rd5 & rss5 & $(END_PACKET) { + Rd5 = vsathb(rss5); + build EndPacket; +} + +# (v2,8) vsathb -- "Rdd32 = vsathb ( Rss32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 0 0 0 0 0 + s s s s s P P + + + + + + 1 1 1 d d d d d + +:vsathb Rdd5,rss5 EndPacket is iclass=8 & op2127=0x00 & op0513=0x07 & Rdd5 & rss5 & $(END_PACKET) { + Rdd5 = vsathb(rss5); + build EndPacket; +} + +# (v2,8) vsathub -- "Rd32 = vsathub ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 1 0 0 1 0 + s s s s s P P + + + + + + 0 1 + d d d d d + +:vsathub Rd5,rs5 EndPacket is iclass=8 & op2127=0x64 & op0513=0x02 & Rd5 & rs5 & $(END_PACKET) +unimpl + +# (v2,8) vsathub -- "Rd32 = vsathub ( Rss32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 0 0 0 0 0 0 s s s s s P P + + + + + + 0 0 + d d d d d + +:vsathub Rd5,rss5 EndPacket is iclass=8 & op2127=0x40 & op0513=0 & Rd5 & rss5 & $(END_PACKET) +unimpl + +# (v2,8) vsathub -- "Rdd32 = vsathub ( Rss32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 0 0 0 0 0 + s s s s s P P + + + + + + 1 0 0 d d d d d + +:vsathub Rdd5,rss5 EndPacket is iclass=8 & op2127=0x00 & op0513=0x04 & Rdd5 & rss5 & $(END_PACKET) +unimpl + +# (v2,8) vsatwh -- "Rd32 = vsatwh ( Rss32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 0 0 0 0 0 0 s s s s s P P + + + + + + 0 1 + d d d d d + +define pcodeop vsatwh; + +:vsatwh Rd5,rss5 EndPacket is iclass=8 & op2127=0x40 & op0513=0x02 & Rd5 & rss5 & $(END_PACKET) { + Rd5 = vsatwh(rss5); + build EndPacket; +} + +# (v2,8) vsatwh -- "Rdd32 = vsatwh ( Rss32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 0 0 0 0 0 + s s s s s P P + + + + + + 1 1 0 d d d d d + +:vsatwh Rdd5,rss5 EndPacket is iclass=8 & op2127=0x00 & op0513=0x06 & Rdd5 & rss5 & $(END_PACKET) { + Rdd5 = vsatwh(rss5); + build EndPacket; +} + +# (v2,8) vsatwuh -- "Rd32 = vsatwuh ( Rss32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 0 0 0 0 0 0 s s s s s P P + + + + + + 1 0 + d d d d d + +define pcodeop vsatwuh; + +:vsatwuh Rd5,rss5 EndPacket is iclass=8 & op2127=0x40 & op0513=0x04 & Rd5 & rss5 & $(END_PACKET) { + Rd5 = vsatwuh(rss5); + build EndPacket; +} + +# (v2,8) vsatwuh -- "Rdd32 = vsatwuh ( Rss32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 0 0 0 0 0 + s s s s s P P + + + + + + 1 0 1 d d d d d + +:vsatwuh Rdd5,rss5 EndPacket is iclass=8 & op2127=0x00 & op0513=0x05 & Rdd5 & rss5 & $(END_PACKET) { + Rdd5 = vsatwuh(rss5); + build EndPacket; +} + +# (v2,8) vsplatb -- "Rd32 = vsplatb ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 1 0 0 0 1 0 s s s s s P P + + + + + + 1 1 1 d d d d d + +define pcodeop vsplatb; + +:vsplatb Rd5,rs5 EndPacket is iclass=8 & op2127=0x62 & op0813=0 & op0507=7 & Rd5 & rs5 & $(END_PACKET) { + Rd5 = vsplatb(rs5); + build EndPacket; +} + +# (?,8) vsplatb -- "Rdd32 = vsplatb ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 1 0 0 0 1 + s s s s s P P + + + + + + 1 0 + d d d d d + +:vsplatb Rdd5,rs5 EndPacket is iclass=8 & op2127=0x22 & op0813=0 & op0507=4 & Rdd5 & rs5 & $(END_PACKET) { + Rdd5 = vsplatb(rs5); + build EndPacket; +} + +# (v2,8) vsplath -- "Rdd32 = vsplath ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 1 0 0 0 1 + s s s s s P P + + + + + + 0 1 + d d d d d + +define pcodeop vsplath; + +:vsplath Rdd5,rs5 EndPacket is iclass=8 & op2127=0x22 & op0813=0 & op0507=2 & Rdd5 & rs5 & $(END_PACKET) { + Rdd5 = vsplath(rs5); + build EndPacket; +} + +# (v2,12) vspliceb -- "Rdd32 = vspliceb ( Rss32 , Rtt32 , #u3 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 0 0 0 1 + + s s s s s P P + t t t t t i i i d d d d d + +:vspliceb Rdd5,rss5,rtt5,Uimm3_0507 EndPacket is iclass=12 & op2127=0x04 & op13=0 & Uimm3_0507 & Rdd5 & rss5 & rtt5 & $(END_PACKET) { + cnt:1 = 8 * Uimm3_0507; + mask:8 = -1 >> (64 - cnt); + Rdd5 = (rtt5 << cnt) | (mask & rss5); + build EndPacket; +} + +# (v2,12) vspliceb -- "Rdd32 = vspliceb ( Rss32 , Rtt32 , Pu4 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 0 1 0 1 0 + s s s s s P P + t t t t t + u u d d d d d + +:vspliceb Rdd5,rss5,rtt5,pu0506 EndPacket is iclass=12 & op2127=0x14 & op13=0 & op7=0 & pu0506 & Rdd5 & rss5 & rtt5 & $(END_PACKET) { + cnt:1 = 8 * (pu0506 & 0x7); + mask:8 = -1 >> (64 - cnt); + Rdd5 = (rtt5 << cnt) | (mask & rss5); + build EndPacket; +} + +# (v2,15) vsubh -- "Rd32 = vsubh ( Rt32 , Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 1 0 1 1 0 1 0 0 s s s s s P P + t t t t t + + + d d d d d + +:vsubh Rd5,rt5,rs5 EndPacket is iclass=15 & op2127=0x34 & op13=0 & op0507=0 & Rd5 & rt5 & rs5 & $(END_PACKET) { + Rd5[0,16] = rt5[0,16] - rs5[0,16]; + Rd5[16,16] = rt5[16,16] - rs5[16,16]; + build EndPacket; +} + +# (v2,15) vsubh -- "Rd32 = vsubh ( Rt32 , Rs32 ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 1 0 1 1 0 1 0 1 s s s s s P P + t t t t t + + + d d d d d + +:vsubh":sat" Rd5,rt5,rs5 EndPacket is iclass=15 & op2127=0x35 & op13=0 & op0507=0 & Rd5 & rt5 & rs5 & $(END_PACKET) { + h:2 = 0; + subSat16(h, rt5[0,16], rs5[0,16]); + Rd5[0,16] = h; + subSat16(h, rt5[16,16], rs5[16,16]); + Rd5[16,16] = h; + build EndPacket; +} + +# (v2,13) vsubh -- "Rdd32 = vsubh ( Rtt32 , Rss32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 1 0 0 1 s s s s s P P + t t t t t 0 1 0 d d d d d + +:vsubh Rdd5,rtt5,rss5 EndPacket is iclass=13 & op2127=0x19 & op13=0 & op0507=2 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5[0,16] = rtt5[0,16] - rss5[0,16]; + Rdd5[16,16] = rtt5[16,16] - rss5[16,16]; + Rdd5[32,16] = rtt5[32,16] - rss5[32,16]; + Rdd5[48,16] = rtt5[48,16] - rss5[48,16]; + build EndPacket; +} + +# (v2,13) vsubh -- "Rdd32 = vsubh ( Rtt32 , Rss32 ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 1 0 0 1 s s s s s P P + t t t t t 0 1 1 d d d d d + +:vsubh":sat" Rdd5,rtt5,rss5 EndPacket is iclass=13 & op2127=0x19 & op13=0 & op0507=3 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { + h:2 = 0; + subSat16(h, rtt5[0,16], rss5[0,16]); + Rdd5[0,16] = h; + subSat16(h, rtt5[16,16], rss5[16,16]); + Rdd5[16,16] = h; + subSat16(h, rtt5[32,16], rss5[32,16]); + Rdd5[32,16] = h; + subSat16(h, rtt5[48,16], rss5[48,16]); + Rdd5[48,16] = h; + build EndPacket; +} + +# (v2,13) vsubub -- "Rdd32 = vsubub ( Rtt32 , Rss32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 1 0 0 1 s s s s s P P + t t t t t 0 0 0 d d d d d + +define pcodeop vsubub; + +:vsubub Rdd5,rtt5,rss5 EndPacket is iclass=13 & op2127=0x19 & op13=0 & op0507=0 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vsubub(rtt5,rss5); + build EndPacket; +} + +# (v2,13) vsubub -- "Rdd32 = vsubub ( Rtt32 , Rss32 ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 1 0 0 1 s s s s s P P + t t t t t 0 0 1 d d d d d + +define pcodeop vsububSat; + +:vsubub":sat" Rdd5,rtt5,rss5 EndPacket is iclass=13 & op2127=0x19 & op13=0 & op0507=1 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5 = vsububSat(rtt5,rss5); + build EndPacket; +} + +# (v2,15) vsubuh -- "Rd32 = vsubuh ( Rt32 , Rs32 ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 1 0 1 1 0 1 1 1 s s s s s P P + t t t t t + + + d d d d d + +:vsubuh":sat" Rd5,rt5,rs5 EndPacket is iclass=15 & op2127=0x37 & op13=0 & op0507=0 & Rd5 & rt5 & rs5 & $(END_PACKET) { + h:2 = 0; + subuSat16(h, rt5[0,16], rs5[0,16]); + Rd5[0,16] = h; + subuSat16(h, rt5[16,16], rs5[16,16]); + Rd5[16,16] = h; + build EndPacket; +} + +# (v2,13) vsubuh -- "Rdd32 = vsubuh ( Rtt32 , Rss32 ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 1 0 0 1 s s s s s P P + t t t t t 1 0 0 d d d d d + +:vsubuh":sat" Rdd5,rtt5,rss5 EndPacket is iclass=13 & op2127=0x19 & op13=0 & op0507=4 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { + h:2 = 0; + subuSat16(h, rtt5[0,16], rss5[0,16]); + Rdd5[0,16] = h; + subuSat16(h, rtt5[16,16], rss5[16,16]); + Rdd5[16,16] = h; + subuSat16(h, rtt5[32,16], rss5[32,16]); + Rdd5[32,16] = h; + subuSat16(h, rtt5[48,16], rss5[48,16]); + Rdd5[48,16] = h; + build EndPacket; +} + +# (v2,13) vsubw -- "Rdd32 = vsubw ( Rtt32 , Rss32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 1 0 0 1 s s s s s P P + t t t t t 1 0 1 d d d d d + +:vsubw Rdd5,rtt5,rss5 EndPacket is iclass=13 & op2127=0x19 & op13=0 & op0507=5 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { + Rdd5[0,32] = rtt5[0,32] - rss5[0,32]; + Rdd5[32,32] = rtt5[32,32] - rss5[32,32]; + build EndPacket; +} + +# (v2,13) vsubw -- "Rdd32 = vsubw ( Rtt32 , Rss32 ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 1 0 0 1 s s s s s P P + t t t t t 1 1 0 d d d d d + +:vsubw":sat" Rdd5,rtt5,rss5 EndPacket is iclass=13 & op2127=0x19 & op13=0 & op0507=6 & Rdd5 & rtt5 & rss5 & $(END_PACKET) { + w:4 = 0; + subSat32(w, rtt5[0,32], rss5[0,32]); + Rdd5[0,32] = w; + subSat32(w, rtt5[32,32], rss5[32,32]); + Rdd5[32,32] = w; + build EndPacket; +} + +# (v2,8) vsxtbh -- "Rdd32 = vsxtbh ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 1 0 0 0 0 + s s s s s P P + + + + + + 0 0 + d d d d d + +define pcodeop vsxtbh; + +:vsxtbh Rdd5,rs5 EndPacket is iclass=8 & op2127=0x20 & op0513=0 & Rdd5 & rs5 & $(END_PACKET) { + Rdd5 = vsxtbh(rs5); + build EndPacket; +} + +# (v2,8) vsxthw -- "Rdd32 = vsxthw ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 1 0 0 0 0 + s s s s s P P + + + + + + 1 0 + d d d d d + +:vsxthw Rdd5,rs5 EndPacket is iclass=8 & op2127=0x20 & op0513=0x04 & Rdd5 & rs5 & $(END_PACKET) { + Rdd5[0,32] = sext(rs5[0,16]); + Rdd5[32,32] = sext(rs5[16,16]); + build EndPacket; +} + +# (v2,8) vtrunehb -- "Rd32 = vtrunehb ( Rss32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 0 0 0 1 0 0 s s s s s P P + + + + + + 0 1 + d d d d d + +define pcodeop vtrunehb; + +:vtrunehb Rd5,rss5 EndPacket is iclass=8 & op2127=0x44 & op0513=0x02 & Rd5 & rss5 & $(END_PACKET) { + Rd5 = vtrunehb(rss5); + build EndPacket; +} + +# (v2,12) vtrunewh -- "Rdd32 = vtrunewh ( Rss32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 0 0 1 1 0 + s s s s s P P + t t t t t 0 1 + d d d d d + +:vtrunewh Rdd5,rss5,rtt5 EndPacket is iclass=12 & op2127=0x0c & op13=0 & op0507=2 & Rdd5 & rss5 & rtt5 & $(END_PACKET) { + Rdd5[0,16] = rtt5[0,16]; + Rdd5[16,16] = rtt5[32,16]; + Rdd5[32,16] = rss5[0,16]; + Rdd5[48,16] = rss5[32,16]; + build EndPacket; +} + +# (v2,8) vtrunohb -- "Rd32 = vtrunohb ( Rss32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 0 0 0 1 0 0 s s s s s P P + + + + + + 0 0 + d d d d d + +define pcodeop vtrunohb; + +:vtrunohb Rd5,rss5 EndPacket is iclass=8 & op2127=0x44 & op0513=0 & Rd5 & rss5 & $(END_PACKET) { + Rd5 = vtrunohb(rss5); + build EndPacket; +} + +# (v2,12) vtrunowh -- "Rdd32 = vtrunowh ( Rss32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 0 0 1 1 0 + s s s s s P P + t t t t t 1 0 + d d d d d + +:vtrunowh Rdd5,rss5,rtt5 EndPacket is iclass=12 & op2127=0x0c & op13=0 & op0507=4 & Rdd5 & rss5 & rtt5 & $(END_PACKET) { + Rdd5[0,16] = rtt5[16,16]; + Rdd5[16,16] = rtt5[48,16]; + Rdd5[32,16] = rss5[16,16]; + Rdd5[48,16] = rss5[48,16]; + build EndPacket; +} + +# (v4,12) vxaddsubh -- "Rdd32 = vxaddsubh ( Rss32 , Rtt32 ) :rnd :>>1 :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 0 0 1 1 1 + s s s s s P P + t t t t t 0 0 + d d d d d + +define pcodeop vxaddsubhRndX2Sat; + +:vxaddsubh":rnd:>>1:sat" Rdd5,rss5,rtt5 EndPacket is iclass=12 & op2127=0x0e & op13=0 & op0507=0 & Rdd5 & rss5 & rtt5 & $(END_PACKET) { + Rdd5 = vxaddsubhRndX2Sat(rtt5,rss5); + build EndPacket; +} + +# (v4,12) vxaddsubh -- "Rdd32 = vxaddsubh ( Rss32 , Rtt32 ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 0 0 1 0 1 + s s s s s P P + t t t t t 1 0 + d d d d d + +define pcodeop vxaddsubhSat; + +:vxaddsubh":sat" Rdd5,rss5,rtt5 EndPacket is iclass=12 & op2127=0x0a & op13=0 & op0507=4 & Rdd5 & rss5 & rtt5 & $(END_PACKET) { + Rdd5 = vxaddsubhSat(rtt5,rss5); + build EndPacket; +} + +# (v4,12) vxaddsubw -- "Rdd32 = vxaddsubw ( Rss32 , Rtt32 ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 0 0 1 0 1 + s s s s s P P + t t t t t 0 0 + d d d d d + +define pcodeop vxaddsubwSat; + +:vxaddsubw":sat" Rdd5,rss5,rtt5 EndPacket is iclass=12 & op2127=0x0a & op13=0 & op0507=0 & Rdd5 & rss5 & rtt5 & $(END_PACKET) { + Rdd5 = vxaddsubwSat(rtt5,rss5); + build EndPacket; +} + +# (v4,12) vxsubaddh -- "Rdd32 = vxsubaddh ( Rss32 , Rtt32 ) :rnd :>>1 :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 0 0 1 1 1 + s s s s s P P + t t t t t 0 1 + d d d d d + +define pcodeop vxsubaddhRndX2Sat; + +:vxsubaddh":rnd:>>1:sat" Rdd5,rss5,rtt5 EndPacket is iclass=12 & op2127=0x0e & op13=0 & op0507=2 & Rdd5 & rss5 & rtt5 & $(END_PACKET) { + Rdd5 = vxsubaddhRndX2Sat(rtt5,rss5); + build EndPacket; +} + +# (v4,12) vxsubaddh -- "Rdd32 = vxsubaddh ( Rss32 , Rtt32 ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 0 0 1 0 1 + s s s s s P P + t t t t t 1 1 + d d d d d + +define pcodeop vxsubaddhSat; + +:vxsubaddh":sat" Rdd5,rss5,rtt5 EndPacket is iclass=12 & op2127=0x0a & op13=0 & op0507=6 & Rdd5 & rss5 & rtt5 & $(END_PACKET) { + Rdd5 = vxsubaddhSat(rtt5,rss5); + build EndPacket; +} + +# (v4,12) vxsubaddw -- "Rdd32 = vxsubaddw ( Rss32 , Rtt32 ) :sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 0 0 1 0 1 + s s s s s P P + t t t t t 0 1 + d d d d d + +define pcodeop vxsubaddwSat; + +:vxsubaddw":sat" Rdd5,rss5,rtt5 EndPacket is iclass=12 & op2127=0x0a & op13=0 & op0507=2 & Rdd5 & rss5 & rtt5 & $(END_PACKET) { + Rdd5 = vxsubaddwSat(rtt5,rss5); + build EndPacket; +} + +# (v2,8) vzxtbh -- "Rdd32 = vzxtbh ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 1 0 0 0 0 + s s s s s P P + + + + + + 0 1 + d d d d d + +define pcodeop vzxtbh; + +:vzxtbh Rdd5,rs5 EndPacket is iclass=8 & op2127=0x20 & op0513=0x02 & Rdd5 & rs5 & $(END_PACKET) { + Rdd5 = vzxtbh(rs5); + build EndPacket; +} + +# (v2,8) vzxthw -- "Rdd32 = vzxthw ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 1 0 0 0 0 + s s s s s P P + + + + + + 1 1 + d d d d d + +:vzxthw Rdd5,rs5 EndPacket is iclass=8 & op2127=0x20 & op0513=0x06 & Rdd5 & rs5 & $(END_PACKET) { + Rdd5[0,32] = zext(rs5[0,16]); + Rdd5[32,32] = zext(rs5[16,16]); + build EndPacket; +} + +# (v2,6) wait -- "wait ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 0 1 0 0 0 1 0 s s s s s P P - - - - - - 0 0 0 - - - - - + +define pcodeop wait; + +:wait rs5 EndPacket is iclass=6 & op2127=0x22 & op0507=0 & rs5 & $(END_PACKET) { + wait(rs5); + build EndPacket; +} + +# (v2,6) xor -- "Pd4 = xor ( Ps4 , Pt4 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 0 1 0 1 1 0 1 0 0 - - s s P P 0 - - - t t - - - - - - d d + +:xor Pd2,pu1617,pu0809 EndPacket is iclass=6 & op2127=0x5a & op1820=0 & op1013=0 & op0207=0 & pu0809 & pu1617 & Pd2 & $(END_PACKET) { + Pd2 = Pd2 & (pu1617 ^ pu0809); + build EndPacket; +} + +# (v2,15) xor -- "Rd32 = xor ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 1 0 0 0 1 0 1 1 s s s s s P P - t t t t t - - - d d d d d + +:xor Rd5,rs5,rt5 EndPacket is iclass=15 & op2127=0x0b & Rd5 & rs5 & rt5 & $(END_PACKET) { + Rd5 = rs5 ^ rt5; + build EndPacket; +} + +# (v2,13) xor -- "Rdd32 = xor ( Rss32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 1 1 1 1 s s s s s P P - t t t t t 1 0 0 d d d d d + +:xor Rdd5,rss5,rtt5 EndPacket is iclass=13 & op2127=0x1f & op0507=4 & Rdd5 & rss5 & rtt5 & $(END_PACKET) { + Rdd5 = rss5 ^ rtt5; + build EndPacket; +} + +# (v4,14) xor -- "Rx32 &= xor ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 1 0 1 0 s s s s s P P + t t t t t + 1 0 x x x x x + +:xor&= Rd5,rs5,rt5 EndPacket is iclass=0xe & op2127=0x7a & op13=0 & op0507=2 & rs5 & rt5 & rd5 & Rd5 & $(END_PACKET) +{ + Rd5 = rd5 & (rs5 ^ rt5); + build EndPacket; +} + +# (v2,14) xor -- "Rx32 ^= xor ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 1 1 0 0 s s s s s P P + t t t t t + 1 1 x x x x x + +:xor"^=" Rd5,rs5,rt5 EndPacket is iclass=0xe & op2127=0x7c & op13=0 & op0507=3 & rs5 & rt5 & rd5 & Rd5 & $(END_PACKET) +{ + Rd5 = rd5 ^ (rs5 ^ rt5); + build EndPacket; +} + +# (v4,14) xor -- "Rx32 |= xor ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 1 1 1 0 s s s s s P P + t t t t t + 0 1 x x x x x + +:xor|= Rd5,rs5,rt5 EndPacket is iclass=0xe & op2127=0x7e & op13=0 & op0507=1 & rs5 & rt5 & rd5 & Rd5 & $(END_PACKET) +{ + Rd5 = rd5 | (rs5 ^ rt5); + build EndPacket; +} + +# (v4,12) xor -- "Rxx32 ^= xor ( Rss32 , Rtt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 1 0 1 0 1 + + s s s s s P P + t t t t t + + + x x x x x + +:xor"^=" Rdd5,rss5,rtt5 EndPacket is iclass=0xc & op2127=0x54 & op13=0 & op0507=0 & rss5 & rtt5 & rdd5 & Rdd5 & $(END_PACKET) +{ + Rdd5 = rdd5 ^ (rss5 ^ rtt5); + build EndPacket; +} + +# (v2,15) xor -- "if ( Pu4 ) Rd32 = xor ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 1 1 0 0 1 + 1 1 s s s s s P P 0 t t t t t 0 u u d d d d d +# +# (v2,15) xor -- "if ( ! Pu4 ) Rd32 = xor ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 1 1 0 0 1 + 1 1 s s s s s P P 0 t t t t t 1 u u d d d d d +# +# (v2,15) xor -- "if ( Pu4 .new ) Rd32 = xor ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 1 1 0 0 1 + 1 1 s s s s s P P 1 t t t t t 0 u u d d d d d +# +# (v2,15) xor -- "if ( ! Pu4 .new ) Rd32 = xor ( Rs32 , Rt32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 1 1 0 0 1 + 1 1 s s s s s P P 1 t t t t t 1 u u d d d d d + +:xor^PuCond0506_N13_S07 rd5,rs5,rt5 EndPacket is iclass=15 & op2327=0x12 & op22=1 & op21=1 & PuCond0506_N13_S07 & rs5 & rt5 & rd5 & rd5_ & SetNRegRd5 & $(END_PACKET) { + build PuCond0506_N13_S07; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + rd5_ = rs5 ^ rt5; + + <> + if (ConditionReg == 0) goto ; + rd5 = rd5_; + +} + +# (v4,7) zxtb -- "if ( Pu4 ) Rd32 = zxtb ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 1 0 0 0 0 1 0 0 s s s s s P P 1 + 0 0 u u + + + d d d d d +# +# (v4,7) zxtb -- "if ( ! Pu4 ) Rd32 = zxtb ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 1 0 0 0 0 1 0 0 s s s s s P P 1 + 1 0 u u + + + d d d d d +# +# (v4,7) zxtb -- "if ( Pu4 .new ) Rd32 = zxtb ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 1 0 0 0 0 1 0 0 s s s s s P P 1 + 0 1 u u + + + d d d d d +# +# (v4,7) zxtb -- "if ( ! Pu4 .new ) Rd32 = zxtb ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 1 0 0 0 0 1 0 0 s s s s s P P 1 + 1 1 u u + + + d d d d d + +:zxtb^PuCond0809_N10_S11 rd5,rs5 EndPacket is iclass=7 & op2127=0x04 & op1213=2 & op0507=0 & rs5 & rd5 & rd5_ & SetNRegRd5 & PuCond0809_N10_S11 & $(END_PACKET) +{ + build PuCond0809_N10_S11; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + rd5_ = zext(rs5:1); + + <> + if (ConditionReg == 0) goto ; + rd5 = rd5_; + +} + +# (v2,7) zxth -- "Rd32 = zxth ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 1 0 0 0 0 1 1 0 s s s s s P P 0 + + + + + + + + d d d d d + +:zxth Rd5,rs5 EndPacket is iclass=7 & op2127=0x06 & op0513=0 & rs5 & Rd5 & $(END_PACKET) +{ + Rd5 = zext(rs5:2); + build EndPacket; +} + +# (v4,7) zxth -- "if ( Pu4 ) Rd32 = zxth ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 1 0 0 0 0 1 1 0 s s s s s P P 1 + 0 0 u u + + + d d d d d +# +# (v4,7) zxth -- "if ( ! Pu4 ) Rd32 = zxth ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 1 0 0 0 0 1 1 0 s s s s s P P 1 + 1 0 u u + + + d d d d d +# +# (v4,7) zxth -- "if ( Pu4 .new ) Rd32 = zxth ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 1 0 0 0 0 1 1 0 s s s s s P P 1 + 0 1 u u + + + d d d d d +# +# (v4,7) zxth -- "if ( ! Pu4 .new ) Rd32 = zxth ( Rs32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 1 0 0 0 0 1 1 0 s s s s s P P 1 + 1 1 u u + + + d d d d d + +:zxth^PuCond0809_N10_S11 rd5,rs5 EndPacket is iclass=7 & op2127=0x06 & op1213=2 & op0507=0 & rs5 & rd5 & rd5_ & SetNRegRd5 & PuCond0809_N10_S11 & $(END_PACKET) +{ + build PuCond0809_N10_S11; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + rd5_ = zext(rs5:2); + + <> + if (ConditionReg == 0) goto ; + rd5 = rd5_; + +} + +# +# Dual-Instructions with PP bits +# + +JmpRel9: "; jump" RelDest9x is RelDest9x { + <> + goto RelDest9x; +} + +# (v4,1) jump -- "Rd16 = #U6 ; jump #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 - 1 1 0 - - i i d d d d P P I I I I I I i i i i i i i - + +:assign Rd1619,Uimm8_0813 JmpRel9 EndPacket is iclass=1 & op2426=6 & Uimm8_0813 & Rd1619 & JmpRel9 & $(END_PACKET) { + Rd1619 = zext(Uimm8_0813); + build EndPacket; +} + +# (v4,1) jump -- "Rd16 = Rs16 ; jump #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 - 1 1 1 - - i i s s s s P P - - d d d d i i i i i i i - + +:assign Rd0811,rs4p JmpRel9 EndPacket is iclass=1 & op2426=7 & rs4p & Rd0811 & JmpRel9 & $(END_PACKET) { + Rd0811 = rs4p; + build JmpRel9; + build EndPacket; +} + +# (v4,1) jump:nt -- "Pu1 = cmp.eq ( Rs16 , #-1 ) ; if ( Pu1 .new ) jump:nt #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 + 0 u 1 1 0 i i s s s s P P 0 - - - 0 0 i i i i i i i - +# +# (v4,1) jump:nt -- "Pu1 = cmp.eq ( Rs16 , #-1 ) ; if ( ! Pu1 .new ) jump:nt #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 + 0 u 1 1 1 i i s s s s P P 0 - - - 0 0 i i i i i i i - +# +# (v4,1) jump:t -- "Pu1 = cmp.eq ( Rs16 , #-1 ) ; if ( Pu1 .new ) jump:t #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 + 0 u 1 1 0 i i s s s s P P 1 - - - 0 0 i i i i i i i - +# +# (v4,1) jump:t -- "Pu1 = cmp.eq ( Rs16 , #-1 ) ; if ( ! Pu1 .new ) jump:t #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 + 0 u 1 1 1 i i s s s s P P 1 - - - 0 0 i i i i i i i - +# + +FlowCond_Pu25_S22: ".if("pu25name".new)" is op22=0 & pu25name & pu25_ { tmp:1 = pu25_ & 1; export tmp; } +FlowCond_Pu25_S22: ".if(!"pu25name".new)" is op22=1 & pu25name & pu25_ { tmp:1 = !(pu25_ & 1); export tmp; } + +IfJmpRel9_Pu25_T13_S22: "; jump"^FlowCond_Pu25_S22^Taken13 RelDest9x is FlowCond_Pu25_S22 & Taken13 & RelDest9x { + <> + if (FlowCond_Pu25_S22 == 0) goto ; + goto RelDest9x; + +} + +:cmp.eq Pd25,rs4p,MinusOne IfJmpRel9_Pu25_T13_S22 EndPacket is iclass=1 & op2627=0 & op2324=3 & op0809=0 & Pd25 & rs4p & MinusOne & IfJmpRel9_Pu25_T13_S22 & $(END_PACKET) { + bool:1 = (rs4p == -1); + Pd25 = Pd25 & (bool * 0xff); + build IfJmpRel9_Pu25_T13_S22; + build EndPacket; +} + +# (v4,1) jump:nt -- "Pu1 = cmp.eq ( Rs16 , #U5 ) ; if ( Pu1 .new ) jump:nt #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 + 0 u 0 0 0 i i s s s s P P 0 I I I I I i i i i i i i - +# +# (v4,1) jump:nt -- "Pu1 = cmp.eq ( Rs16 , #U5 ) ; if ( ! Pu1 .new ) jump:nt #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 + 0 u 0 0 1 i i s s s s P P 0 I I I I I i i i i i i i - +# +# (v4,1) jump:t -- "Pu1 = cmp.eq ( Rs16 , #U5 ) ; if ( Pu1 .new ) jump:t #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 + 0 u 0 0 0 i i s s s s P P 1 I I I I I i i i i i i i - +# +# (v4,1) jump:t -- "Pu1 = cmp.eq ( Rs16 , #U5 ) ; if ( ! Pu1 .new ) jump:t #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 + 0 u 0 0 1 i i s s s s P P 1 I I I I I i i i i i i i - + +:cmp.eq Pd25,rs4p,Uimm8_0812 IfJmpRel9_Pu25_T13_S22 EndPacket is iclass=1 & op2627=0 & op2324=0 & Pd25 & rs4p & Uimm8_0812 & IfJmpRel9_Pu25_T13_S22 & $(END_PACKET) { + bool:1 = (rs4p == zext(Uimm8_0812)); + Pd25 = Pd25 & (bool * 0xff); + build IfJmpRel9_Pu25_T13_S22; + build EndPacket; +} + +# (v4,1) jump:nt -- "Pu1 = cmp.eq ( Rs16 , Rt16 ) ; if ( Pu1 .new ) jump:nt #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 + 1 0 0 0 0 i i s s s s P P 0 u t t t t i i i i i i i - +# +# (v4,1) jump:nt -- "Pu1 = cmp.eq ( Rs16 , Rt16 ) ; if ( ! Pu1 .new ) jump:nt #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 + 1 0 0 0 1 i i s s s s P P 0 u t t t t i i i i i i i - +# +# (v4,1) jump:t -- "Pu1 = cmp.eq ( Rs16 , Rt16 ) ; if ( Pu1 .new ) jump:t #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 + 1 0 0 0 0 i i s s s s P P 1 u t t t t i i i i i i i - +# +# (v4,1) jump:t -- "Pu1 = cmp.eq ( Rs16 , Rt16 ) ; if ( ! Pu1 .new ) jump:t #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 + 1 0 0 0 1 i i s s s s P P 1 u t t t t i i i i i i i - + +FlowCond_Pu12_S22: ".if("pu12name".new)" is op22=0 & pu12name & pu12_ { tmp:1 = pu12_ & 1; export tmp; } +FlowCond_Pu12_S22: ".if(!"pu12name".new)" is op22=1 & pu12name & pu12_ { tmp:1 = !(pu12_ & 1); export tmp; } + +IfJmpRel9_Pu12_T13_S22: "; jump"^FlowCond_Pu12_S22^Taken13 RelDest9x is FlowCond_Pu12_S22 & Taken13 & RelDest9x { + <> + if (FlowCond_Pu12_S22 == 0) goto ; + goto RelDest9x; + +} + +:cmp.eq Pd12,rs4p,rt4p IfJmpRel9_Pu12_T13_S22 EndPacket is iclass=1 & op2327=8 & Pd12 & rs4p & rt4p & IfJmpRel9_Pu12_T13_S22 & $(END_PACKET) { + bool:1 = (rs4p == rt4p); + Pd12 = Pd12 & (bool * 0xff); + build IfJmpRel9_Pu12_T13_S22; + build EndPacket; +} + +# (v4,1) jump:nt -- "Pu1 = cmp.gt ( Rs16 , #-1 ) ; if ( Pu1 .new ) jump:nt #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 + 0 u 1 1 0 i i s s s s P P 0 - - - 0 1 i i i i i i i - +# +# (v4,1) jump:nt -- "Pu1 = cmp.gt ( Rs16 , #-1 ) ; if ( ! Pu1 .new ) jump:nt #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 + 0 u 1 1 1 i i s s s s P P 0 - - - 0 1 i i i i i i i - +# +# (v4,1) jump:t -- "Pu1 = cmp.gt ( Rs16 , #-1 ) ; if ( Pu1 .new ) jump:t #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 + 0 u 1 1 0 i i s s s s P P 1 - - - 0 1 i i i i i i i - +# +# (v4,1) jump:t -- "Pu1 = cmp.gt ( Rs16 , #-1 ) ; if ( ! Pu1 .new ) jump:t #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 + 0 u 1 1 1 i i s s s s P P 1 - - - 0 1 i i i i i i i - + +:cmp.gt Pd25,rs4p,MinusOne IfJmpRel9_Pu25_T13_S22 EndPacket is iclass=1 & op2627=0 & op2324=3 & op0809=1 & Pd25 & rs4p & MinusOne & IfJmpRel9_Pu25_T13_S22 & $(END_PACKET) { + bool:1 = (rs4p s> -1); + Pd25 = Pd25 & (bool * 0xff); + build IfJmpRel9_Pu25_T13_S22; + build EndPacket; +} + +# (v4,1) jump:nt -- "Pu1 = cmp.gt ( Rs16 , #U5 ) ; if ( Pu1 .new ) jump:nt #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 + 0 u 0 1 0 i i s s s s P P 0 I I I I I i i i i i i i - +# +# (v4,1) jump:nt -- "Pu1 = cmp.gt ( Rs16 , #U5 ) ; if ( ! Pu1 .new ) jump:nt #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 + 0 u 0 1 1 i i s s s s P P 0 I I I I I i i i i i i i - +# +# (v4,1) jump:t -- "Pu1 = cmp.gt ( Rs16 , #U5 ) ; if ( Pu1 .new ) jump:t #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 + 0 u 0 1 0 i i s s s s P P 1 I I I I I i i i i i i i - +# +# (v4,1) jump:t -- "Pu1 = cmp.gt ( Rs16 , #U5 ) ; if ( ! Pu1 .new ) jump:t #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 + 0 u 0 1 1 i i s s s s P P 1 I I I I I i i i i i i i - + +:cmp.gt Pd25,rs4p,Uimm8_0812 IfJmpRel9_Pu25_T13_S22 EndPacket is iclass=1 & op2627=0 & op2324=1 & Pd25 & rs4p & Uimm8_0812 & IfJmpRel9_Pu25_T13_S22 & $(END_PACKET) { + bool:1 = (rs4p s> zext(Uimm8_0812)); + Pd25 = Pd25 & (bool * 0xff); + build IfJmpRel9_Pu25_T13_S22; + build EndPacket; +} + +# (v4,1) jump:nt -- "Pu1 = cmp.gt ( Rs16 , Rt16 ) ; if ( Pu1 .new ) jump:nt #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 + 1 0 0 1 0 i i s s s s P P 0 u t t t t i i i i i i i - +# +# (v4,1) jump:nt -- "Pu1 = cmp.gt ( Rs16 , Rt16 ) ; if ( ! Pu1 .new ) jump:nt #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 + 1 0 0 1 1 i i s s s s P P 0 u t t t t i i i i i i i - +# +# (v4,1) jump:t -- "Pu1 = cmp.gt ( Rs16 , Rt16 ) ; if ( Pu1 .new ) jump:t #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 + 1 0 0 1 0 i i s s s s P P 1 u t t t t i i i i i i i - +# +# (v4,1) jump:t -- "Pu1 = cmp.gt ( Rs16 , Rt16 ) ; if ( ! Pu1 .new ) jump:t #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 + 1 0 0 1 1 i i s s s s P P 1 u t t t t i i i i i i i - + +:cmp.gt Pd12,rs4p,rt4p IfJmpRel9_Pu12_T13_S22 EndPacket is iclass=1 & op2327=9 & Pd12 & rs4p & rt4p & IfJmpRel9_Pu12_T13_S22 & $(END_PACKET) { + bool:1 = (rs4p s> rt4p); + Pd12 = Pd12 & (bool * 0xff); + build IfJmpRel9_Pu12_T13_S22; + build EndPacket; +} + +# (v4,1) jump:nt -- "Pu1 = cmp.gtu ( Rs16 , #U5 ) ; if ( Pu1 .new ) jump:nt #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 + 0 u 1 0 0 i i s s s s P P 0 I I I I I i i i i i i i - +# +# (v4,1) jump:nt -- "Pu1 = cmp.gtu ( Rs16 , #U5 ) ; if ( ! Pu1 .new ) jump:nt #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 + 0 u 1 0 1 i i s s s s P P 0 I I I I I i i i i i i i - +# +# (v4,1) jump:t -- "Pu1 = cmp.gtu ( Rs16 , #U5 ) ; if ( Pu1 .new ) jump:t #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 + 0 u 1 0 0 i i s s s s P P 1 I I I I I i i i i i i i - +# +# (v4,1) jump:t -- "Pu1 = cmp.gtu ( Rs16 , #U5 ) ; if ( ! Pu1 .new ) jump:t #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 + 0 u 1 0 1 i i s s s s P P 1 I I I I I i i i i i i i - + +:cmp.gtu Pd25,rs4p,Uimm8_0812 IfJmpRel9_Pu25_T13_S22 EndPacket is iclass=1 & op2627=0 & op2324=2 & Pd25 & rs4p & Uimm8_0812 & IfJmpRel9_Pu25_T13_S22 & $(END_PACKET) { + bool:1 = (rs4p > zext(Uimm8_0812)); + Pd25 = Pd25 & (bool * 0xff); + build IfJmpRel9_Pu25_T13_S22; + build EndPacket; +} + +# (v4,1) jump:nt -- "Pu1 = cmp.gtu ( Rs16 , Rt16 ) ; if ( Pu1 .new ) jump:nt #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 + 1 0 1 0 0 i i s s s s P P 0 u t t t t i i i i i i i - +# +# (v4,1) jump:nt -- "Pu1 = cmp.gtu ( Rs16 , Rt16 ) ; if ( ! Pu1 .new ) jump:nt #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 + 1 0 1 0 1 i i s s s s P P 0 u t t t t i i i i i i i - +# +# (v4,1) jump:t -- "Pu1 = cmp.gtu ( Rs16 , Rt16 ) ; if ( Pu1 .new ) jump:t #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 + 1 0 1 0 0 i i s s s s P P 1 u t t t t i i i i i i i - +# +# (v4,1) jump:t -- "Pu1 = cmp.gtu ( Rs16 , Rt16 ) ; if ( ! Pu1 .new ) jump:t #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 + 1 0 1 0 1 i i s s s s P P 1 u t t t t i i i i i i i - + +:cmp.gtu Pd12,rs4p,rt4p IfJmpRel9_Pu12_T13_S22 EndPacket is iclass=1 & op2327=0xa & Pd12 & rs4p & rt4p & IfJmpRel9_Pu12_T13_S22 & $(END_PACKET) { + bool:1 = (rs4p > rt4p); + Pd12 = Pd12 & (bool * 0xff); + build IfJmpRel9_Pu12_T13_S22; + build EndPacket; +} + +# (v4,1) jump:nt -- "Pu1 = tstbit ( Rs16 , #0 ) ; if ( Pu1 .new ) jump:nt #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 + 0 u 1 1 0 i i s s s s P P 0 - - - 1 1 i i i i i i i - +# +# (v4,1) jump:nt -- "Pu1 = tstbit ( Rs16 , #0 ) ; if ( ! Pu1 .new ) jump:nt #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 + 0 u 1 1 1 i i s s s s P P 0 - - - 1 1 i i i i i i i - +# +# (v4,1) jump:t -- "Pu1 = tstbit ( Rs16 , #0 ) ; if ( Pu1 .new ) jump:t #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 + 0 u 1 1 0 i i s s s s P P 1 - - - 1 1 i i i i i i i - +# +# (v4,1) jump:t -- "Pu1 = tstbit ( Rs16 , #0 ) ; if ( ! Pu1 .new ) jump:t #r9:2x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 + 0 u 1 1 1 i i s s s s P P 1 - - - 1 1 i i i i i i i - + +:tstbit Pd25,rs4p,Zero IfJmpRel9_Pu25_T13_S22 EndPacket is iclass=1 & op2627=0 & op2324=3 & op0809=3 & Pd25 & rs4p & Zero & IfJmpRel9_Pu25_T13_S22 & $(END_PACKET) { + bool:1 = (rs4p & 1) != 0; + Pd25 = Pd25 & (bool * 0xff); + build IfJmpRel9_Pu25_T13_S22; + build EndPacket; +} diff --git a/Ghidra/Processors/Hexagon/data/languages/hexagon.slaspec b/Ghidra/Processors/Hexagon/data/languages/hexagon.slaspec new file mode 100755 index 0000000000..778d7a7887 --- /dev/null +++ b/Ghidra/Processors/Hexagon/data/languages/hexagon.slaspec @@ -0,0 +1,888 @@ +# Qualcomm Hexagon (V73) and HVX (V69) + +## KNOWN ISSUES +# 1. Shift amounts may be positive or negative, however in some cases no special handling +# is provided for negative shift amounts. +# 2. There are many complex instructions with unimplemented pcode or simple custom pcodeops +# +## NOTES +# 1. Implementation includes V73 system registers, instruction set may be incomplete +# 2. HVX vector register size is 128-bytes (see defines below), paired size is 256-bytes +# +## VERSIONS +# 1.x - preliminary versions (pre-release) +# 2.0 - initial release +# 2.1 - added support for conditional commit of modifying operands, e.g. (r0++#4) (r0=#4) +# 2.2 - TBD (research change history) +# 2.3 - Added missing instructions and corrected invalid DF instructions. The disabled +# ADD_DP_OPS property has been used to contain these although they may be removed +# in the future. +# 2.4 - Added EXEC_COND crossbuild (12.0.1) and added HVX support (12.0.2) +# + +@define HVX_VECTOR_SIZE "128" +@define HVX_VECTOR_PAIR_SIZE "256" +@define HVX_VECTOR_BASE "0x2000" +@define HVX_VECTOR_TMP_BASE "0x3000" + +@define HVX_PREDICATE_SIZE "16" + +define endian=little; +define alignment=4; + +define space ram type=ram_space size=4 default; +define space register type=register_space size=4; + +# General purpose registers +# Register aliases have been used for R29(SP), R30(FP) and R31(LR) + +define register offset=0 size=8 [ R1R0 R3R2 R5R4 R7R6 R9R8 R11R10 R13R12 R15R14 + R17R16 R19R18 R21R20 R23R22 R25R24 R27R26 R29R28 R31R30 ]; + +define register offset=0 size=4 [ R0 R1 R2 R3 R4 R5 R6 R7 + R8 R9 R10 R11 R12 R13 R14 R15 + R16 R17 R18 R19 R20 R21 R22 R23 + R24 R25 R26 R27 R28 SP FP LR ]; + +define register offset=0 size=2 [ R0.L R0.H R1.L R1.H R2.L R2.H R3.L R3.H + R4.L R4.H R5.L R5.H R6.L R6.H R7.L R7.H + R8.L R8.H R9.L R9.H R10.L R10.H R11.L R11.H + R12.L R12.H R13.L R13.H R14.L R14.H R15.L R15.H + R16.L R16.H R17.L R17.H R18.L R18.H R19.L R19.H + R20.L R20.H R21.L R21.H R22.L R22.H R23.L R23.H + R24.L R24.H R25.L R25.H R26.L R26.H R27.L R27.H + R28.L R28.H R29.L R29.H R30.L R30.H R31.L R31.H ]; + +# General purpose shadow registers (used to delay register writes until end of instruction packet) + +define register offset=0x100 size=8 [ R1R0_ R3R2_ R5R4_ R7R6_ R9R8_ R11R10_ R13R12_ R15R14_ + R17R16_ R19R18_ R21R20_ R23R22_ R25R24_ R27R26_ R29R28_ R31R30_ ]; + +define register offset=0x100 size=4 [ R0.new R1.new R2.new R3.new R4.new R5.new R6.new R7.new + R8.new R9.new R10.new R11.new R12.new R13.new R14.new R15.new + R16.new R17.new R18.new R19.new R20.new R21.new R22.new R23.new + R24.new R25.new R26.new R27.new R28.new SP.new FP.new LR.new ]; + +define register offset=0x100 size=2 [ R0.L_ R0.H_ R1.L_ R1.H_ R2.L_ R2.H_ R3.L_ R3.H_ + R4.L_ R4.H_ R5.L_ R5.H_ R6.L_ R6.H_ R7.L_ R7.H_ + R8.L_ R8.H_ R9.L_ R9.H_ R10.L_ R10.H_ R11.L_ R11.H_ + R12.L_ R12.H_ R13.L_ R13.H_ R14.L_ R14.H_ R15.L_ R15.H_ + R16.L_ R16.H_ R17.L_ R17.H_ R18.L_ R18.H_ R19.L_ R19.H_ + R20.L_ R20.H_ R21.L_ R21.H_ R22.L_ R22.H_ R23.L_ R23.H_ + R24.L_ R24.H_ R25.L_ R25.H_ R26.L_ R26.H_ R27.L_ R27.H_ + R28.L_ R28.H_ R29.L_ R29.H_ R30.L_ R30.H_ R31.L_ R31.H_ ]; + +# Control registers (range C16-C31 not defined by V5/V55) +# TODO: Check Control register naming across versions - with only one variant not sure how we handle this +define register offset=0x200 size=8 [ C1C0 C3C2 C5C4 C7C6 C9C8 C11C10 C13C12 UPCYCLE + C17C16 PKTCOUNT C21C20 C23C22 C25C24 C27C26 C29C28 UTIMER ]; + +define register offset=0x200 size=4 [ SA0 LC0 SA1 LC1 P3P0 C5 M0 M1 + USR PC UGP GP CS0 CS1 UPCYCLELO UPCYCLEHI + FRAMELIMIT FRAMEKEY PKTCOUNTLO PKTCOUNTHI C20 C21 C22 C23 + C24 C25 C26 C27 C28 C29 UTIMERLO UTIMERHI ]; + +define register offset=0x210 size=1 [ P3 P2 P1 P0 ]; # corresponds to P3P0 + +# TODO: Do ALL of the control registers need shadows for writing/flushing ?? +define register offset=0x300 size=8 [ C1C0_ C3C2_ C5C4_ C7C6_ C9C8_ C11C10_ C13C12_ UPCYCLE_ + C17C16_ PKTCOUNT_ C21C20_ C23C22_ C25C24_ C27C26_ C29C28_ UTIMER_ ]; + +define register offset=0x300 size=4 [ SA0_ LC0_ SA1_ LC1_ P3P0_ C5_ M0_ M1_ + USR_ PC_ UGP_ GP_ CS0_ CS1_ UPCYCLELO_ UPCYCLEHI_ + FRAMELIMIT_ FRAMEKEY_ PKTCOUNTLO_ PKTCOUNTHI_ C20_ C21_ C22_ C23_ + C24_ C25_ C26_ C27_ C28_ C29_ UTIMERLO_ UTIMERHI_ ]; # shadow versions + +define register offset=0x310 size=1 [ P3.new P2.new P1.new P0.new ]; # new/shadow versions, corresponds to P3P0_ + +# Guest Registers (see pspec for renaming) +# TODO: Do all guest registers need shadows for writing/flushing ?? +define register offset=0x400 size=8 [ G1G0 G3G2 G5G4 G7G6 G9G8 G11G10 G13G12 G15G14 + G17G16 G19G18 G21G20 G23G22 G25G24 G27G26 G29G28 G31G30 ]; + +define register offset=0x400 size=4 [ G0 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 + G16 G17 G18 G19 G20 G21 G22 G23 G24 G25 G26 G27 G28 G29 G30 G31 ]; + +# System Registers (see pspec for renaming) +# TODO: Do all system registers need shadows for writing/flushing ?? +define register offset=0x800 size=8 [ S1S0 S3S2 S5S4 S7S6 S9S8 S11S10 S13S12 S15S14 + S17S16 S19S18 S21S20 S23S22 S25S24 S27S26 S29S28 S31S30 + S33S32 S35S34 S37S36 S39S38 S41S40 S43S42 S45S44 S47S46 + S49S48 S51S50 S53S52 S55S54 S57S56 S59S58 S61S60 S63S62 ]; + +define register offset=0x800 size=4 [ S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 + S16 S17 S18 S19 S20 S21 S22 S23 S24 S25 S26 S27 S28 S29 S30 S31 + S32 S33 S34 S35 S36 S37 S38 S39 S40 S41 S42 S43 S44 S45 S46 S47 + S48 S49 S50 S51 S52 S53 S54 S55 S56 S57 S58 S59 S60 S61 S62 S63 ]; + +# System register mappings (may differ with version) +@define ELR "S3" +@define SSR "S6" +@define CAUSE "S6[0,8]" # SSR bits 0..7, Exception/Trap Cause + +# Hidden language registers + +# ConditionReg: The condition register set by various +# conditional subconstructors which should be built within the +# appropriate <> or <> pcode section for an instruction +# immediately before using the ConditionReg value. +# +# WARNING! This may present a limitation if multiple condition/predicate +# registers are utilized within a single execute packet. +# +# <> +# build PuCondXYZ; +# if (ConditionReg == 0) goto ; +# rd5 = rd5_; +# + +define register offset=0x1000 size=1 [ ConditionReg ]; + +# ReturnAddr: This register is updated with inst_next for use within the <> section +# to facilitate LR assignment prior to a CALL flow. + +define register offset=0x1004 size=4 [ ReturnAddr ]; + +define register offset=$(HVX_VECTOR_BASE) size=$(HVX_VECTOR_PAIR_SIZE) + [ V1V0 V3V2 V5V4 V7V6 V9V8 V11V10 V13V12 V15V14 + V17V16 V19V18 V21V20 V23V22 V25V24 V27V26 V29V28 V31V30 ]; + +define register offset=$(HVX_VECTOR_BASE) size=$(HVX_VECTOR_SIZE) + [ V0 V1 V2 V3 V4 V5 V6 V7 + V8 V9 V10 V11 V12 V13 V14 V15 + V16 V17 V18 V19 V20 V21 V22 V23 + V24 V25 V26 V27 V28 V29 V30 V31 ]; + +# +# HVX vector temporary / shadow registers +# + +define register offset=$(HVX_VECTOR_TMP_BASE) size=$(HVX_VECTOR_PAIR_SIZE) + [ V1V0_ V3V2_ V5V4_ V7V6_ V9V8_ V11V10_ V13V12_ V15V14_ + V17V16_ V19V18_ V21V20_ V23V22_ V25V24_ V27V26_ V29V28_ V31V30_ ]; + + +define register offset=$(HVX_VECTOR_TMP_BASE) size=$(HVX_VECTOR_SIZE) + [ V0.new V1.new V2.new V3.new V4.new V5.new V6.new V7.new + V8.new V9.new V10.new V11.new V12.new V13.new V14.new V15.new + V16.new V17.new V18.new V19.new V20.new V21.new V22.new V23.new + V24.new V25.new V26.new V27.new V28.new V29.new V30.new V31.new ]; + +# +# HVX Predicate Registers (four predicate registers, each having 1-bit per byte of a vector register) +# +define register offset=0x4000 size=$(HVX_PREDICATE_SIZE) [ Q0 Q1 Q2 Q3 ]; + +# +# Define context bits +# + +define register offset=0x5000 size=12 contextreg; + +define context contextreg + + # Stored context bits + immext = (0,25) noflow # unshifted extended immediate value (26-bits << 6) + simmext = (0,25) signed noflow # unshifted extended immediate value (26-bits << 6) + immexted = (26,26) noflow # flag indicating previous instr was immext + + packetOffset = (27,28) noflow # instruction number within packet (distance from start of packet) + # The packetOffset is set prior to the actual instruction decode phase + packetOffset0 = (28,28) noflow # packetOffset bit-0 (lsb) + packetOffset1 = (27,27) noflow # packetOffset bit-1 (msb) + + useLoopCfg = (29,29) noflow # indicates body of h/w loop where LPCFG!=0 + + unused1 = (30,31) # Required to prevent field split across 32-bit integer boundary + + # NOTE: bulk packetBits used to simplify context propogation + packetBits = (32,63) noflow # allows bulk propagation (part 1 of 2) + + #--- start of auto-propogated packetBits (all sub-fields must be noflow) --- + + parse1 = (32,33) noflow #(keep) parse value for first instruction in packet (used for end of loop detection) + parse2 = (34,35) noflow #(keep) parse value for second instruction in packet (used for end of loop detection) + + # Ns8 / Os8 new register operand tracking + nreg0 = (36,40) noflow #(keep) slot-0 assigned reg (raw reg-number) + nreg1 = (41,45) noflow #(keep) slot-1 assigned reg (raw reg-number) + nreg2 = (46,50) noflow #(keep) slot-2 assigned reg (raw reg-number) + + removed1 = (51,55) noflow # no longer used - available for reuse + + # xreg - tracks immext use required for Ns8 and Os8 new register tracking + xreg = (56,60) noflow #(keep) slot reduction count when identifying nreg assignment slot + + unused2 = (61,63) noflow # Required to prevent field split across 32-bit integer boundary + + #--- end of auto-propogated packetBits --- + + # Transient context bits + phase = (64,66) #(keep) 3-bit instruction parse phase (used by :^instruction) + + # (keep) Localized transient context bits which may utilize overlapping regions in some controlled cases + tmpCtx3 = (67,69) # Temporary 3-bit context storage + tmpCtx2 = (67,68) # Temporary 2-bit context storage + nregSlot = (67,68) # computed nreg/vnreg slot derived from upper 2-bits of 3-bit Ns8 or Os8 encoding + shift = (67,68) # memory address shift factor (0-3) + + # Ns8 and Os8 .new register decode assist + nregr = (69,73) # computed new register 5-bit index (raw reg-number) + nreg = (69,73) # computed new scalar register (attached) - R0..R31 + nreg_ = (69,73) # computed new scalar shadow register (attached) - R0_..R31_ + vnreg = (69,73) # computed new vector register (attached) - V0..V31 + vnreg_ = (69,73) # computed new vector shadow register (attached) - V0_..V31_ + + cond = (74,74) # set if instruction is conditional with complex operand and ConditionReg will be set + # (not used by packed instructions) + + unused3 = (75,95) +; + +# USR Register Fields +@define LPCFG "USR[8,2]" +@define LPCFG_ "USR_[8,2]" +@define OVF "USR[0,1]" +@define OVF_ "USR_[0,1]" + +# Tokens + +define token instr (32) + iclass = (28,31) # instruction class (see page 118) + iclass3031 = (30,31) + iclass2931 = (29,31) + iclass2829 = (28,29) + iclass31 = (31,31) + iclass30 = (30,30) + iclass29 = (29,29) + iclass28 = (28,28) + + parse = (14,15) # packet/loop bits (01/10-not end of packet, 11-end of packet, 00-EE instruction) + parse_0 = (14,14) + parse_1 = (15,15) + + op2627 = (26,27) + op2527 = (25,27) + op2427 = (24,27) + op2426 = (24,26) + op2327 = (23,27) + op2326 = (23,26) + op2324 = (23,24) + op2227 = (22,27) + op2224 = (22,24) + op2223 = (22,23) + op2127 = (21,27) + op2125 = (21,25) + op2124 = (21,24) + op2123 = (21,23) + op2122 = (21,22) + op1920 = (19,20) + op1820 = (18,20) + op1827 = (18,27) + op1720 = (17,20) + op1620 = (16,20) + op1617 = (16,17) + op1213 = (12,13) + op1113 = (11,13) + op1112 = (11,12) + op1013 = (10,13) + op1012 = (10,12) + op1011 = (10,11) + op0913 = (9,13) + op0912 = (9,12) + op0911 = (9,11) + op0910 = (9,10) + op0813 = (8,13) + op0812 = (8,12) + op0810 = (8,10) + op0809 = (8,9) + op0613 = (6,13) + op0612 = (6,12) + op0607 = (6,7) + op0513 = (5,13) + op0512 = (5,12) + op0508 = (5,8) + op0507 = (5,7) + op0506 = (5,6) + op0412 = (4,12) + op0306 = (3,6) + op0304 = (3,4) + op0213 = (2,13) + op0207 = (2,7) + op0205 = (2,5) + op0204 = (2,4) + op0013 = (0,13) + op0007 = (0,7) + op0004 = (0,4) + op0002 = (0,2) + op0001 = (0,1) + + op27 = (27,27) + op26 = (26,26) + op25 = (25,25) + op24 = (24,24) + op23 = (23,23) + op22 = (22,22) + op21 = (21,21) + op20 = (20,20) + op19 = (19,19) + op18 = (18,18) + op16 = (16,16) + op13 = (13,13) + op12 = (12,12) + op11 = (11,11) + op10 = (10,10) + op8 = (8,8) + op7 = (7,7) + op6 = (6,6) + op5 = (5,5) + op4 = (4,4) + op3 = (3,3) + op2 = (2,2) + op1 = (1,1) + op0 = (0,0) + + s2526 = (25,26) signed + s2223 = (22,23) signed + s22 = (22,22) signed + s2127 = (21,27) signed + s2122 = (21,22) signed + s21 = (21,21) signed + s2026 = (20,26) signed + s2021 = (20,21) signed + s1924 = (19,24) signed + s1624 = (16,24) signed + s1622 = (16,22) signed + s1620 = (16,20) signed + s1619 = (16,19) signed + s13 = (13,13) signed + s0813 = (8,13) signed + s0812 = (8,12) signed + s0810 = (8,10) signed + s0712 = (7,12) signed + s0513 = (5,13) signed + s0512 = (5,12) signed + s0508 = (5,8) signed + s0410 = (4,10) signed + s0308 = (3,8) signed + s0306 = (3,6) signed + + i2526 = (25,26) + i2427 = (24,27) + i2426 = (24,26) + i24 = (24,24) + i2223 = (22,23) + i2127 = (21,27) + i2123 = (21,23) + i2122 = (21,22) + i2025 = (20,25) + i2024 = (20,24) + i1923 = (19,23) + i1627 = (16,27) + i1620 = (16,20) + i1619 = (16,19) + i1617 = (16,17) + i13 = (13,13) + i1213 = (12,13) + i9 = (9,9) + i0813 = (8,13) + i0812 = (8,12) + i0811 = (8,11) + i0810 = (8,10) + i8 = (8,8) + i0712 = (7,12) + i0513 = (5,13) + i0512 = (5,12) + i0511 = (5,11) + i0510 = (5,10) + i0509 = (5,9) + i0507 = (5,7) + i0506 = (5,6) + i5 = (5,5) + i0409 = (4,9) + i0408 = (4,8) + i0307 = (3,7) + i0306 = (3,6) + i0304 = (3,4) + i3 = (3,3) + i0204 = (2,4) + i0113 = (1,13) + i0111 = (1,11) + i0107 = (1,7) + i1 = (1,1) + i0013 = (0,13) + i0010 = (0,10) + i0007 = (0,7) + i0006 = (0,6) + i0005 = (0,5) + i0004 = (0,4) + i0003 = (0,3) + i0001 = (0,1) + + pu2324 = (23,24) # 8-bit predicate reg + pu2122 = (21,22) # 8-bit predicate reg + pu2122_ = (21,22) # 8-bit predicate reg (shadow) + pu2122name = (21,22) # 8-bit predicate reg (name) + pu1617 = (16,17) # 8-bit predicate reg + pu1112 = (11,12) # 8-bit predicate reg + pu1112_ = (11,12) # 8-bit predicate reg (shadow) + pu1112name = (11,12) # 8-bit predicate reg (name) + pu0910 = (9,10) # 8-bit predicate reg + pu0910_ = (9,10) # 8-bit predicate reg (shadow) + pu0910name = (9,10) # 8-bit predicate reg (name) + pu0809 = (8,9) # 8-bit predicate reg + pu0809_ = (8,9) # 8-bit predicate reg (shadow) + pu0809name = (8,9) # 8-bit predicate reg (name) + pu0607 = (6,7) # 8-bit predicate reg + pu0506 = (5,6) # 8-bit predicate reg + pu0506_ = (5,6) # 8-bit predicate reg (shadow) + pu0506name = (5,6) # 8-bit predicate reg (name) + pu0001 = (0,1) # 8-bit predicate reg + pu0001_ = (0,1) # 8-bit predicate reg (shadow) + pu0001name = (0,1) # 8-bit predicate reg (name) + + pu25 = (25,25) # P0/P1 + pu25_ = (25,25) # P0.new/P1.new + pu25name = (25,25) # P0/P1 (name) + pu12 = (12,12) # P0/P1 + pu12_ = (12,12) # P0.new/P1.new + pu12name = (12,12) # P0/P1 (name) + + qv0001 = (0,1) # HVX Vector predicate reg (Q0..Q3) + qv0506 = (5,6) # HVX Vector predicate reg (Q0..Q3) + qv0809 = (8,9) # HVX Vector predicate reg (Q0..Q3) + qv1112 = (11,12) # HVX Vector predicate reg (Q0..Q3) + qv2223 = (22,23) # HVX Vector predicate reg (Q0..Q3) + + mu = (13,13) # M0/M1 reg + + cs5 = (16,20) # 32-bit control reg + css5 = (16,20) # dual 32-bit control reg + + gs5 = (16,20) # 32-bit guest reg + gss5 = (16,20) # dual 32-bit guest reg + + rs5 = (16,20) # 32-bit general reg + rs5H = (16,20) # 16-bit general reg (high halfword) + rs5L = (16,20) # 16-bit general reg (low halfword) + rss5 = (16,20) # 64-bit general reg + rss5h = (16,20) # 32-bit high reg for rss5 + + rxx5 = (16,20) # 64-bit general reg + rxx5_ = (16,20) # 64-bit general reg (shadow) + rx5 = (16,20) # 32-bit general reg + rx5_ = (16,20) # 32-bit general reg (shadow) + rf5 = (16,20) # 32-bit general reg + rf5_ = (16,20) # 32-bit general reg (shadow) + rx5H = (16,20) # 16-bit general reg (high halfword) + rx5H_ = (16,20) # 16-bit general reg (high halfword, shadow) + rx5L = (16,20) # 16-bit general reg (low halfword) + rx5L_ = (16,20) # 16-bit general reg (low halfword, shadow) + + + rtt5 = (8,12) # 64-bit general reg + rtt5h = (8,12) # 32-bit high reg for rtt5 + rt5 = (8,12) # 32-bit general reg + rt5H = (8,12) # 16-bit general reg (high halfword) + rt5L = (8,12) # 16-bit general reg (low halfword) + + rd0812 = (8,12) # 32-bit general reg + rd0812_ = (8,12) # 32-bit general reg (shadow) + rdd0812 = (8,12) # 64-bit general reg + rdd0812_ = (8,12) # 64-bit general reg (shadow) + + rd5 = (0,4) # 32-bit general reg + rd5_ = (0,4) # 32-bit general reg (shadow) + rdd5 = (0,4) # 64-bit general reg + rdd5_ = (0,4) # 64-bit general reg (shadow) + rdd5h = (0,4) # hi (odd) 32-bit reg of a 64-bit general reg (use rd5 for lo/even) + rdd5h_ = (0,4) # hi (odd) 32-bit reg of a 64-bit general reg (use rd5 for lo/even) (shadow) + + rt1618 = (16,18) # 32-bit general reg (r0..r7) + + cd5 = (0,4) # 32-bit control reg + cd5_ = (0,4) # 32-bit control reg (shadow) + cdd5 = (0,4) # dual 32-bit control reg + cdd5_ = (0,4) # dual 32-bit control reg (shadow) + + gd5 = (0,4) # 32-bit guest reg + gdd5 = (0,4) # dual 32-bit guest regs + + ru5 = (0,4) # 32-bit control reg + ruu5 = (0,4) # 64-bit general reg + ru5H = (0,4) # 16-bit general reg (high halfword) + ru5L = (0,4) # 16-bit general reg (low halfword) + + vdd5 = (0,4) # HVX vector register pair + vdd5_ = (0,4) # HVX vector register pair (shadow) + + vss5 = (0,4) # HVX vector register pair + + vuu5 = (8,12) # HVX vector register pair +# vuu5_ = (8,12) # HVX vector register pair (shadow) + + vvv5 = (16,20) # HVX vector register pair +# vvv5_ = (16,20) # HVX vector register pair (shadow) + + vd5 = (0,4) # HVX vector register + vd5_ = (0,4) # HVX vector register (shadow) + + vs5 = (0,4) # HVX vector register +# vs5_ = (0,4) # HVX vector register (shadow) + + vu5 = (8,12) # HVX vector register +# vu5_ = (8,12) # HVX vector register (shadow) + + vv5 = (16,20) # HVX vector register +# vv5_ = (16,20) # HVX vector register (shadow) + + vz5 = (19,23) # HVX vector register +# vz5_ = (19,23) # HVX vector register (shadow) + + nreg_1618 = (16,18) # Ns8 32-bit general register .new (3-bit encoded) + nreg_0810 = (8,10) # Ns8 32-bit general register .new (3-bit encoded) + nreg_0002 = (0,2) # Ns8 32-bit general register or Os8 vector .new (3-bit encoded) + nreg_0002lsb = (0,0) # lsb of 3-bit encoding for alternate .new register use + + sd6 = (0,5) # supervisory register (assumed to be 32-bits each) + sdd6 = (0,5) # supervisory register (assumed to be 64-bits each) + ss6 = (16,21) # supervisory register (assumed to be 32-bits each) + sss6 = (16,21) # supervisory register (assumed to be 64-bits each) + + # duplex/packed fields - PP mode + + rs4p = (16,19) # 16-bit general reg + rt4p = (8,11) # 16-bit general reg + rd0811 = (8,11) # 16-bit general reg + rd0811_ = (8,11) # 16-bit general reg (shadow) + rd1619 = (16,19) # 16-bit general reg + rd1619_ = (16,19) # 16-bit general reg (shadow) + + # duplex/packed fields - left side (register attachments are somewhat assumed) + + rdd3l = (16,18) # 64-bit general reg + rdd3l_ = (16,18) # 64-bit general reg (shadow) + rtt3l = (16,18) # 64-bit general reg + rd4l = (16,19) # 32-bit general reg + rd4l_ = (16,19) # 32-bit general reg (shadow) + rt4l = (16,19) # 32-bit general reg + rs4l = (20,23) # 32-bit general reg + + # duplex/packed fields - right side (register attachments are somewhat assumed) + + rdd3r = (0,2) # 64-bit general reg + rdd3r_ = (0,2) # 64-bit general reg + rtt3r = (0,2) # 64-bit general reg + rd4r = (0,3) # 32-bit general reg + rd4r_ = (0,3) # 32-bit general reg (shadow) + rs4r = (4,7) # 32-bit general reg + rt4r = (0,3) # 32-bit general reg +; + +# +# Attach statements +# + +# 64-bit reg selector is 5-bits - the LS bit must always be 0 (even reg) + +attach variables [ rdd5 rxx5 rss5 rtt5 ruu5 rdd0812 ] + [ R1R0 _ R3R2 _ R5R4 _ R7R6 _ R9R8 _ R11R10 _ R13R12 _ R15R14 _ + R17R16 _ R19R18 _ R21R20 _ R23R22 _ R25R24 _ R27R26 _ R29R28 _ R31R30 _ ]; + +attach variables [ rdd5_ rxx5_ rdd0812_ ] + [ R1R0_ _ R3R2_ _ R5R4_ _ R7R6_ _ R9R8_ _ R11R10_ _ R13R12_ _ R15R14_ _ + R17R16_ _ R19R18_ _ R21R20_ _ R23R22_ _ R25R24_ _ R27R26_ _ R29R28_ _ R31R30_ _]; + +# Access to high word reg of specified long word rtt5, rt5 can be used for low word reg +attach variables [ rtt5h rss5h ] + [ R1 _ R3 _ R5 _ R7 _ R9 _ R11 _ R13 _ R15 _ R17 _ R19 _ R21 _ R23 _ R25 _ R27 _ SP _ LR _ ]; + +# Access to high word reg of specified long word rdd5, rd5 can be used for low word reg +attach variables [ rdd5h ] + [ R1 _ R3 _ R5 _ R7 _ + R9 _ R11 _ R13 _ R15 _ + R17 _ R19 _ R21 _ R23 _ + R25 _ R27 _ SP _ LR _ ]; +attach variables [ rdd5h_ ] + [ R1.new _ R3.new _ R5.new _ R7.new _ + R9.new _ R11.new _ R13.new _ R15.new _ + R17.new _ R19.new _ R21.new _ R23.new _ + R25.new _ R27.new _ SP.new _ LR.new _ ]; + +attach variables [ rdd3l rtt3l rdd3r rtt3r ] + [ R1R0 R3R2 R5R4 R7R6 R17R16 R19R18 R21R20 R23R22 ]; +attach variables [ rdd3l_ rdd3r_ ] + [ R1R0_ R3R2_ R5R4_ R7R6_ R17R16_ R19R18_ R21R20_ R23R22_ ]; + +attach variables [ rd5 rd0812 rs5 rt5 ru5 rx5 rf5 nreg ] + [ R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 + R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 SP FP LR ]; + +attach variables [ rt1618 ] + [ R0 R1 R2 R3 R4 R5 R6 R7 ]; + +attach variables [ rd5_ rd0812_ rx5_ rf5_ nreg_ ] + [ R0.new R1.new R2.new R3.new R4.new R5.new R6.new R7.new + R8.new R9.new R10.new R11.new R12.new R13.new R14.new R15.new + R16.new R17.new R18.new R19.new R20.new R21.new R22.new R23.new + R24.new R25.new R26.new R27.new R28.new SP.new FP.new LR.new ]; + +attach variables [ rx5H rs5H rt5H ru5H ] + [ R0.H R1.H R2.H R3.H R4.H R5.H R6.H R7.H + R8.H R9.H R10.H R11.H R12.H R13.H R14.H R15.H + R16.H R17.H R18.H R19.H R20.H R21.H R22.H R23.H + R24.H R25.H R26.H R27.H R28.H R29.H R30.H R31.H ]; + +attach variables [ rx5H_ ] + [ R0.H_ R1.H_ R2.H_ R3.H_ R4.H_ R5.H_ R6.H_ R7.H_ + R8.H_ R9.H_ R10.H_ R11.H_ R12.H_ R13.H_ R14.H_ R15.H_ + R16.H_ R17.H_ R18.H_ R19.H_ R20.H_ R21.H_ R22.H_ R23.H_ + R24.H_ R25.H_ R26.H_ R27.H_ R28.H_ R29.H_ R30.H_ R31.H_ ]; + +attach variables [ rx5L rs5L rt5L ru5L ] + [ R0.L R1.L R2.L R3.L R4.L R5.L R6.L R7.L + R8.L R9.L R10.L R11.L R12.L R13.L R14.L R15.L + R16.L R17.L R18.L R19.L R20.L R21.L R22.L R23.L + R24.L R25.L R26.L R27.L R28.L R29.L R30.L R31.L ]; + +attach variables [ rx5L_ ] + [ R0.L_ R1.L_ R2.L_ R3.L_ R4.L_ R5.L_ R6.L_ R7.L_ + R8.L_ R9.L_ R10.L_ R11.L_ R12.L_ R13.L_ R14.L_ R15.L_ + R16.L_ R17.L_ R18.L_ R19.L_ R20.L_ R21.L_ R22.L_ R23.L_ + R24.L_ R25.L_ R26.L_ R27.L_ R28.L_ R29.L_ R30.L_ R31.L_ ]; + +attach variables [ rs4p rt4p rs4l rt4l rs4r rd4l rd4r rt4r rd0811 rd1619 ] + [ R0 R1 R2 R3 R4 R5 R6 R7 R16 R17 R18 R19 R20 R21 R22 R23]; +attach variables [ rd4l_ rd4r_ rd0811_ rd1619_ ] + [ R0.new R1.new R2.new R3.new R4.new R5.new R6.new R7.new + R16.new R17.new R18.new R19.new R20.new R21.new R22.new R23.new]; + +attach variables [ cd5 cs5 ] + [ SA0 LC0 SA1 LC1 P3P0 C5 M0 M1 + USR PC UGP GP CS0 CS1 UPCYCLELO UPCYCLEHI + FRAMELIMIT FRAMEKEY PKTCOUNTLO PKTCOUNTHI C20 C21 C22 C23 + C24 C25 C26 C27 C28 C29 UTIMERLO UTIMERHI ]; + +attach variables [ cd5_ ] + [ SA0_ LC0_ SA1_ LC1_ P3P0_ C5_ M0_ M1_ + USR_ PC UGP_ GP_ CS0_ CS1_ UPCYCLELO_ UPCYCLEHI_ + FRAMELIMIT_ FRAMEKEY_ PKTCOUNTLO_ PKTCOUNTHI_ C20_ C21_ C22_ C23_ + C24_ C25_ C26_ C27_ C28_ C29_ UTIMERLO_ UTIMERHI_ ]; + +attach variables [ css5 cdd5 ] + [ C1C0 _ C3C2 _ C5C4 _ C7C6 _ + C9C8 _ C11C10 _ C13C12 _ UPCYCLE _ + C17C16 _ PKTCOUNT _ C21C20 _ C23C22 _ + C25C24 _ C27C26 _ C29C28 _ UTIMER _ ]; + +attach variables [ cdd5_ ] + [ C1C0_ _ C3C2_ _ C5C4_ _ C7C6_ _ + C9C8_ _ C11C10_ _ C13C12_ _ UPCYCLE_ _ + C17C16_ _ PKTCOUNT_ _ C21C20_ _ C23C22_ _ + C25C24_ _ C27C26_ _ C29C28_ _ UTIMER_ _ ]; + +attach variables [ mu ] [ M0 M1 ]; + +attach variables [ pu12 pu25 ] [ P0 P1 ]; +attach variables [ pu12_ pu25_ ] [ P0.new P1.new ]; +attach names [ pu12name pu25name ] [ "P0" "P1" ]; + +attach variables [ pu0001 pu0506 pu0607 pu0809 pu1112 pu0910 pu1617 pu2122 pu2324 ] [ P0 P1 P2 P3 ]; +attach variables [ pu0001_ pu0506_ pu0809_ pu0910_ pu1112_ pu2122_ ] [ P0.new P1.new P2.new P3.new ]; +attach names [ pu0001name pu0506name pu0809name pu1112name pu0910name pu2122name ] [ "P0" "P1" "P2" "P3" ]; + +attach variables [ qv0001 qv0506 qv0809 qv1112 qv2223 ] [ Q0 Q1 Q2 Q3 ]; + +attach variables [ ss6 sd6 ] # TODO: Shadow reg's not implemented for system regs + [ S0 S1 S2 S3 S4 S5 S6 S7 + S8 S9 S10 S11 S12 S13 S14 S15 + S16 S17 S18 S19 S20 S21 S22 S23 + S24 S25 S26 S27 S28 S29 S30 S31 + S32 S33 S34 S35 S36 S37 S38 S39 + S40 S41 S42 S43 S44 S45 S46 S47 + S48 S49 S50 S51 S52 S53 S54 S55 + S56 S57 S58 S59 S60 S61 S62 S63 ]; + +attach variables [ sss6 sdd6 ] # TODO: Shadow reg's not implemented for system regs + [ S1S0 _ S3S2 _ S5S4 _ S7S6 _ + S9S8 _ S11S10 _ S13S12 _ S15S14 _ + S17S16 _ S19S18 _ S21S20 _ S23S22 _ + S25S24 _ S27S26 _ S29S28 _ S31S30 _ + S33S32 _ S35S34 _ S37S36 _ S39S38 _ + S41S40 _ S43S42 _ S45S44 _ S47S46 _ + S49S48 _ S51S50 _ S53S52 _ S55S54 _ + S57S56 _ S59S58 _ S61S60 _ S63S62 _ ]; + +attach variables [ gss5 gdd5 ] [ # TODO: Shadow reg's not implemented for guest regs + G1G0 _ G3G2 _ G5G4 _ G7G6 _ + G9G8 _ G11G10 _ G13G12 _ G15G14 _ + G17G16 _ G19G18 _ G21G20 _ G23G22 _ + G25G24 _ G27G26 _ G29G28 _ G31G30 _ ]; + +attach variables [ gs5 gd5 ] [ # TODO: Shadow reg's not implemented for guest regs + G0 G1 G2 G3 G4 G5 G6 G7 + G8 G9 G10 G11 G12 G13 G14 G15 + G16 G17 G18 G19 G20 G21 G22 G23 + G24 G25 G26 G27 G28 G29 G30 G31 ]; + +# +# HVX vector registers +# + +# NOTE: HVX Vector register access size and signedness are generally indicated by a +# suffix in assembly source, e.g., .b .ub .h .uh .w.uw +# We currently do not name lane-access registers and rely on lane access sizes as +# defined by the pspec. + +# double-vector reg selector is 5-bits - the LS bit must always be 0 (even reg) + +attach variables [ vdd5 vss5 vuu5 vvv5 ] + [ V1V0 _ V3V2 _ V5V4 _ V7V6 _ V9V8 _ V11V10 _ V13V12 _ V15V14 _ + V17V16 _ V19V18 _ V21V20 _ V23V22 _ V25V24 _ V27V26 _ V29V28 _ V31V30 _ ]; + +attach variables [ vd5 vs5 vu5 vv5 vz5 vnreg ] + [ V0 V1 V2 V3 V4 V5 V6 V7 + V8 V9 V10 V11 V12 V13 V14 V15 + V16 V17 V18 V19 V20 V21 V22 V23 + V24 V25 V26 V27 V28 V29 V30 V31 ]; + +attach variables [ vdd5_ ] # TODO: Removed vuu5_ vvv5_ + [ V1V0_ _ V3V2_ _ V5V4_ _ V7V6_ _ V9V8_ _ V11V10_ _ V13V12_ _ V15V14_ _ + V17V16_ _ V19V18_ _ V21V20_ _ V23V22_ _ V25V24_ _ V27V26_ _ V29V28_ _ V31V30_ _ ]; + +attach variables [ vd5_ vnreg_ ] # TODO: Removed vs5_ vu5_ vv5_ vz5_ + [ V0.new V1.new V2.new V3.new V4.new V5.new V6.new V7.new + V8.new V9.new V10.new V11.new V12.new V13.new V14.new V15.new + V16.new V17.new V18.new V19.new V20.new V21.new V22.new V23.new + V24.new V25.new V26.new V27.new V28.new V29.new V30.new V31.new ]; + +# +# Ns8 .new scalar register support +# + +# The assigned register must be written to the nreg slot which corresponds to +# the packet slot minus the xreg value. The xreg value is incremented +# anytime an immext instruction is encountered within the packet. +# Assumptions: +# 1. Packet contains 4 instruction slots +# 2. Use of Rx.new will always be the last instruction within a packet +# 3. At most 2 immext instructions may exist in packet +# 4. Two adjacent immext instructions not allowed +# 5. left/right EE instructions are of no concern (they are always last in packet) +# 6. 64-bit scalar register destination is not allowed but we do not prevent it +# 7. New value store context may be shared for scalar and vector register use since +# only one or the other will be forwarded by any one instruction. + +# Set appropriate nreg based upon packetOffset less number of preceeding immext ops +# Cases have been optimized based upon valid placement of immext within packet + +# Set appropriate new value store index 'nreg#' using default destination register field rd5_ +# This new value store subconstructor can be shared with vd5_ and vdd5_, which all use the +# same token bit range (00,04). +SetNRegRd5: is packetOffset=0 & rd5_ [ nreg0=rd5_; ] { } +SetNRegRd5: is packetOffset=1 & rd5_ [ nreg1=rd5_; ] { } +SetNRegRd5: is packetOffset=1 & xreg=1 & rd5_ [ nreg0=rd5_; ] { } +SetNRegRd5: is packetOffset=2 & rd5_ [ nreg2=rd5_; ] { } +SetNRegRd5: is packetOffset=2 & xreg=1 & rd5_ [ nreg1=rd5_; ] { } +SetNRegRd5: is packetOffset=3 { } # no need to retain new value register for last instruction + +# Set appropriate nreg using rx5_ +SetNRegRx5: is packetOffset=0 & rx5_ [ nreg0=rx5_; ] { } +SetNRegRx5: is packetOffset=1 & rx5_ [ nreg1=rx5_; ] { } +SetNRegRx5: is packetOffset=1 & xreg=1 & rx5_ [ nreg0=rx5_; ] { } +SetNRegRx5: is packetOffset=2 & rx5_ [ nreg2=rx5_; ] { } +SetNRegRx5: is packetOffset=2 & xreg=1 & rx5_ [ nreg1=rx5_; ] { } +SetNRegRx5: is packetOffset=3 { } # no need to retain new value register for last instruction + +# Set appropriate nreg using rd0812_ +SetNRegRd0812: is packetOffset=0 & rd0812_ [ nreg0=rd0812_; ] { } +SetNRegRd0812: is packetOffset=1 & rd0812_ [ nreg1=rd0812_; ] { } +SetNRegRd0812: is packetOffset=1 & xreg=1 & rd0812_ [ nreg0=rd0812_; ] { } +SetNRegRd0812: is packetOffset=2 & rd0812_ [ nreg2=rd0812_; ] { } +SetNRegRd0812: is packetOffset=2 & xreg=1 & rd0812_ [ nreg1=rd0812_; ] { } +SetNRegRd0812: is packetOffset=3 { } # no need to retain new value register for last instruction + +# TODO: If needed, add SetNReg for: Re32 Rx32 Rd16 Re16 Rx16 Ry16 Rd8 + +# Compute new value store index context 'nregr' based upon 'nregSlot' and appropriate 'nreg#' context. +# This subcontructor may be shared by both Ns8 (new scalar reg) and Os8 (new vector reg) decode since +# they share the underlying new value index 'nreg#' context storage. +# NOTE: The nregSlot must preceed the current packetOffset +GetNReg: is nregSlot=0 & (packetOffset0=1 | packetOffset1=1) & nreg0 [ nregr = nreg0; ] { } +GetNReg: is nregSlot=1 & packetOffset1=1 & nreg1 [ nregr = nreg1; ] { } +GetNReg: is nregSlot=2 & packetOffset=3 & nreg2 [ nregr = nreg2; ] { } + +# Decode 3-bit encoded Ns8 .new register, setting nregSlot (lsb of 3-bit nreg field ignored) +# and return appropriate nreg (R0.new - R31.new). The nregSlot must refer to a previous +# instruction slot within the same execute packet. +# +# NOTE: Since the non-shadow register location is returned (while .new is displayed) is is assumed +# that the location will not be read until the <> phase or later + +Nreg1618: nreg_ is GetNReg & nreg_ & nreg & nreg_1618 [ nregSlot = packetOffset - xreg - (nreg_1618 >> 1); ] { export nreg; } +Nreg0810: nreg_ is GetNReg & nreg_ & nreg & nreg_0810 [ nregSlot = packetOffset - xreg - (nreg_0810 >> 1); ] { export nreg; } +Nreg0002: nreg_ is GetNReg & nreg_ & nreg & nreg_0002 [ nregSlot = packetOffset - xreg - (nreg_0002 >> 1); ] { export nreg; } + +# +# HVX Os8 .new vector register support +# Employs the same strategy as the Ns8 above with some context fields sharing use for both Os8 and Ns8 +# + +# NOTE: More investigation is needed for the correct 3-bit Os8 encoding. Some information suggests +# that bits identify the specific pipeline which produced the vector result and is not based on +# packetOffset as originally believed. + +# Set appropriate new value index 'nregr' using vd5_ or vdd5_ (same as rd5_ field) +SetVNRegVd5: is SetNRegRd5 { } + +# Compute Os8 new value store index 'nregr' based upon 'nregSlot' when Os8 lsb is '0'. +# NOTE: We can share GetNReg use with Ns8 decode for this case. +GetVNReg: is GetNReg { } + +# Compute alternate Os8 new value store index 'nregr' based upon 'nregSlot' when Os8 lsb is '1'. +# This will produce a new value store index that corresponds to the other vector register within +# the same pair (e.g., if vnreg# indicates V0 index, V1 index will be use by inverting lsb for 'nregr') +# NOTE: The nregSlot must preceed the current packetOffset +GetVNAltReg: is nregSlot=0 & (packetOffset0=1 | packetOffset1=1) & nreg0 [ nregr = nreg0 ^ 1; ] { } +GetVNAltReg: is nregSlot=1 & packetOffset1=1 & nreg1 [ nregr = nreg1 ^ 1; ] { } +GetVNAltReg: is nregSlot=2 & packetOffset=3 & nreg2 [ nregr = nreg2 ^ 1; ] { } + +# Decode 3-bit encoded Os8 .new vector register, setting nregSlot (lsb of 3-bit nreg field ignored) +# and return appropriate vnreg (V0.new - V31.new). The nregSlot must refer to a previous +# instruction slot within the same execute packet. +# +# NOTE: Since the non-shadow register location is returned (while .new is displayed) is is assumed +# that the location will not be read until the <> phase or later + +# The lsb of 3-bit Os8 field indicates an alternate register. It appears to have two cases: +# 1) register pair: if '1' .new corresponds to the other register in the aligned pair (GetVNAltReg) +# 2) dual independent registers: Vx(0), Vy(1) use case (not yet supported) + +VNreg0002: vnreg_ is GetVNReg & vnreg_ & vnreg & nreg_0002lsb=0 & nreg_0002 [ nregSlot = packetOffset - xreg - (nreg_0002 >> 1); ] { export vnreg; } +VNreg0002: vnreg_ is GetVNAltReg & vnreg_ & vnreg & nreg_0002lsb=1 & nreg_0002 [ nregSlot = packetOffset - xreg - (nreg_0002 >> 1); ] { export vnreg; } + +# +# General Instruction Set parse and execute packet and crossbuild constructors +# +@include "hexagon.sinc" + +# +# Packed/Duplex 'EE' Instruction Set +# 29..31 Instruction Class +# 14..15 PP parse bits +# 00..12 Right sub-instruction (Slot-0) +# 16..28 Left sub-instruction (Slot-1) +# +@include "hexagon_left.sinc" +@include "hexagon_right.sinc" + +# +# Floating Point Instruction Set +# +@include "hexagon_float.sinc" + +# +# Vector Instruction Set (HVX extension) +# +@include "hexagon_hvx.sinc" + diff --git a/Ghidra/Processors/Hexagon/data/languages/hexagon_float.sinc b/Ghidra/Processors/Hexagon/data/languages/hexagon_float.sinc new file mode 100644 index 0000000000..de104c131d --- /dev/null +++ b/Ghidra/Processors/Hexagon/data/languages/hexagon_float.sinc @@ -0,0 +1,872 @@ +# +# Floating Point Instructions +# Added with V5x: +# convert_sf2d, convert_sf2df, convert_sf2ud, convert_sf2uw, convert_sf2w +# convert_d2sf, convert_ud2sf, convert_uw2sf, convert_w2sf +# convert_df2d, convert_df2sf, convert_df2ud, convert_df2uw, convert_df2w +# convert_d2df, convert_ud2df, convert_uw2df, convert_w2df +# sfadd, sfclass, sfcmp.*, sffixupd, sffixupn, sffixupr, sfmake, sfmax, sfmin, sfmpy, sfsub +# dfclass, dfcmp.*, dfmake +# Added with V65: +# sfinvsqrta, sfrecipa +# Added with V66: +# dfadd, dfsub +# Added with V67: +# dfmax, dfmin, dfmpyfix, dfmpyhh, dfmpylh, dfmpyll +# +# See bottom of this file for additional instruction patterns found within QEMU source code. +# Use of the undocumented double-precission floating instructions are disabled by default +# due to conflicts with V6 instructions. The option ADD_DP_OPS must be defined to +# to enable the use of these undocumented instructions which will disable the use of +# corresponding V6 instructions which conflict. +# + +define pcodeop convertFloat2UInt; +define pcodeop chopFloat2UInt; + +# +# V5x Floating Point Instructions +# + +# (v5,8) convert_sf2d -- "Rdd = convert_sf2d ( Rs )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 1 0 0 1 + + s s s s s P P + + + + + + 1 0 0 d d d d d + +:convert_sf2d Rdd5,rs5 EndPacket is iclass=8 & op2127=0x24 & op0813=0 & op0507=4 & rs5 & Rdd5 & $(END_PACKET) { + # TODO: Rounding mode and other exceptional conditions are not implemented + Rdd5 = trunc(rs5); + build EndPacket; +} + +# (v5,8) convert_sf2d -- "Rdd = convert_sf2d ( Rs ) :chop" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 1 0 0 1 + + s s s s s P P + + + + + + 1 1 0 d d d d d + +:convert_sf2d^":chop" Rdd5,rs5 EndPacket is iclass=8 & op2127=0x24 & op0813=0 & op0507=6 & rs5 & Rdd5 & $(END_PACKET) { + # TODO: Exceptional conditions are not implemented + Rdd5 = trunc(rs5); + build EndPacket; +} + +# (v5,8) convert_sf2df -- "Rdd = convert_sf2df ( Rs )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 1 0 0 1 + + s s s s s P P + + + + + + 0 0 0 d d d d d + +:convert_sf2df Rdd5,rs5 EndPacket is iclass=8 & op2127=0x24 & op0813=0 & op0507=0 & rs5 & Rdd5 & $(END_PACKET) { + Rdd5 = float2float(rs5); + build EndPacket; +} + +# (v5,8) convert_sf2ud -- "Rdd = convert_sf2ud ( Rs )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 1 0 0 1 + + s s s s s P P + + + + + + 0 1 1 d d d d d + +:convert_sf2ud Rdd5,rs5 EndPacket is iclass=8 & op2127=0x24 & op0813=0 & op0507=3 & rs5 & Rdd5 & $(END_PACKET) { + # TODO: Exceptional conditions are not implemented + float:4 = float2float(rs5); + Rdd5 = convertFloat2UInt(float); + build EndPacket; +} + +# (v5,8) convert_sf2ud -- "Rdd = convert_sf2ud ( Rs ) :chop" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 1 0 0 1 + + s s s s s P P + + + + + + 1 0 1 d d d d d + +:convert_sf2ud^":chop" Rdd5,rs5 EndPacket is iclass=8 & op2127=0x24 & op0813=0 & op0507=5 & rs5 & Rdd5 & $(END_PACKET) { + # TODO: Exceptional conditions are not implemented + float:4 = float2float(rs5); + Rdd5 = chopFloat2UInt(float); + build EndPacket; +} + +# (v5,8) convert_sf2uw -- "Rd = convert_sf2uw ( Rs )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 0 1 1 0 1 1 s s s s s P P + + + + + + 0 0 0 d d d d d + +:convert_sf2uw Rd5,rs5 EndPacket is iclass=8 & op2127=0x5b & op0813=0 & op0507=0 & rs5 & Rd5 & $(END_PACKET) { + # TODO: Rounding mode and other exceptional conditions are not implemented + float:4 = float2float(rs5); + Rd5 = convertFloat2UInt(float); + build EndPacket; +} + +# (v5,8) convert_sf2uw -- "Rd = convert_sf2uw ( Rs ) :chop" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 0 1 1 0 1 1 s s s s s P P + + + + + + 0 0 1 d d d d d + +:convert_sf2uw^":chop" Rd5,rs5 EndPacket is iclass=8 & op2127=0x5b & op0813=0 & op0507=1 & rs5 & Rd5 & $(END_PACKET) { + # TODO: Exceptional conditions are not implemented + float:4 = float2float(rs5); + Rd5 = chopFloat2UInt(float); + build EndPacket; +} + +# (v5,8) convert_sf2w -- "Rd = convert_sf2w ( Rs )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 0 1 1 1 0 0 s s s s s P P + + + + + + 0 0 0 d d d d d + +:convert_sf2w Rd5,rs5 EndPacket is iclass=8 & op2127=0x5c & op0813=0 & op0507=0 & rs5 & Rd5 & $(END_PACKET) { + # TODO: Rounding mode and other exceptional conditions are not implemented + Rd5 = trunc(rs5); + build EndPacket; +} + +# (v5,8) convert_sf2w -- "Rd = convert_sf2w ( Rs ) :chop" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 0 1 1 1 0 0 s s s s s P P + + + + + + 0 0 1 d d d d d + +:convert_sf2w^":chop" Rd5,rs5 EndPacket is iclass=8 & op2127=0x5c & op0813=0 & op0507=1 & rs5 & Rd5 & $(END_PACKET) { + # TODO: Exceptional conditions are not implemented + Rd5 = trunc(rs5); + build EndPacket; +} + +# (v5,8) convert_d2sf -- "Rd = convert_d2sf ( Rss )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 0 0 0 0 1 0 s s s s s P P + + + + + + 0 0 1 d d d d d + +:convert_d2sf Rd5,rss5 EndPacket is iclass=8 & op2127=0x42 & op0813=0 & op0507=1 & rss5 & Rd5 & $(END_PACKET) { + Rd5 = int2float(rss5); + build EndPacket; +} + +# (v5,8) convert_ud2sf -- "Rd = convert_ud2sf ( Rss )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 0 0 0 0 0 1 s s s s s P P + + + + + + 0 0 1 d d d d d + +# TODO: we do not have an unsigned int2float - could zext but not with 8-byte reg if we want to emulate +define pcodeop convertUInt2float; + +:convert_ud2sf Rd5,rss5 EndPacket is iclass=8 & op2127=0x41 & op0813=0 & op0507=1 & rss5 & Rd5 & $(END_PACKET) { + tmp:9 = zext(rss5); + Rd5 = int2float(tmp); + build EndPacket; +} + +# (v5,8) convert_uw2sf -- "Rd = convert_uw2sf ( Rs )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 0 1 1 0 0 1 s s s s s P P + + + + + + 0 0 0 d d d d d + +:convert_uw2sf Rd5,rs5 EndPacket is iclass=8 & op2127=0x59 & op0813=0 & op0507=0 & rs5 & Rd5 & $(END_PACKET) { + tmp:8 = zext(rs5); + Rd5 = int2float(tmp); + build EndPacket; +} + +# (v5,8) convert_w2sf -- "Rd = convert_w2sf ( Rs )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 0 1 1 0 1 0 s s s s s P P + + + + + + 0 0 0 d d d d d + +:convert_w2sf Rd5,rs5 EndPacket is iclass=8 & op2127=0x5a & op0813=0 & op0507=0 & rs5 & Rd5 & $(END_PACKET) { + Rd5 = int2float(rs5); + build EndPacket; +} + +# (v5,8) convert_df2d -- "Rdd = convert_df2d ( Rss )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 0 0 0 1 1 1 s s s s s P P 0 + + + + + 0 0 0 d d d d d + +:convert_df2d Rdd5,rss5 EndPacket is iclass=8 & op2127=0x07 & op0813=0 & op0507=0 & rss5 & Rdd5 & $(END_PACKET) { + # TODO: Rounding mode and other exceptional conditions are not implemented + Rdd5 = trunc(rss5); + build EndPacket; +} + +# (v5,8) convert_df2d -- "Rdd = convert_df2d ( Rss ) :chop" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 0 0 0 1 1 1 s s s s s P P 0 + + + + + 1 1 0 d d d d d + +:convert_df2d^":chop" Rdd5,rss5 EndPacket is iclass=8 & op2127=0x07 & op0813=0 & op0507=6 & rss5 & Rdd5 & $(END_PACKET) { + # TODO: Exceptional conditions are not implemented + Rdd5 = trunc(rss5); + build EndPacket; +} + +# (v5,8) convert_df2sf -- "Rd = convert_df2sf ( Rss )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 0 0 0 0 0 0 s s s s s P P + + + + + + 0 0 1 d d d d d + +:convert_df2sf Rd5,rss5 EndPacket is iclass=8 & op2127=0x40 & op0813=0 & op0507=1 & rss5 & Rd5 & $(END_PACKET) { + Rd5 = float2float(rss5); + build EndPacket; +} + +# (v5,8) convert_df2ud -- "Rdd = convert_df2ud ( Rss )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 0 0 0 1 1 1 s s s s s P P 0 + + + + + 0 0 1 d d d d d + +:convert_df2ud Rdd5,rss5 EndPacket is iclass=8 & op2127=0x07 & op0813=0 & op0507=1 & rss5 & Rdd5 & $(END_PACKET) { + # TODO: Exceptional conditions are not implemented + float:8 = float2float(rss5); + Rdd5 = convertFloat2UInt(float); + build EndPacket; +} + +# (v5,8) convert_df2ud -- "Rdd = convert_df2ud ( Rss ) :chop" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 0 0 0 1 1 1 s s s s s P P 0 + + + + + 1 1 1 d d d d d + +:convert_df2ud^":chop" Rdd5,rss5 EndPacket is iclass=8 & op2127=0x07 & op0813=0 & op0507=7 & rss5 & Rdd5 & $(END_PACKET) { + # TODO: Exceptional conditions are not implemented + float:8 = float2float(rss5); + Rdd5 = chopFloat2UInt(float); + build EndPacket; +} + +# (v5,8) convert_df2uw -- "Rd = convert_df2uw ( Rss )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 0 0 0 0 1 1 s s s s s P P + + + + + + 0 0 1 d d d d d + +:convert_df2uw Rd5,rss5 EndPacket is iclass=8 & op2127=0x43 & op0813=0 & op0507=1 & rss5 & Rd5 & $(END_PACKET) { + # TODO: Rounding mode and other exceptional conditions are not implemented + float:8 = float2float(rss5); + Rd5 = convertFloat2UInt(float); + build EndPacket; +} + +# (v5,8) convert_df2uw -- "Rd = convert_df2uw ( Rss ) :chop" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 0 0 0 1 0 1 s s s s s P P + + + + + + 0 0 1 d d d d d + +:convert_df2uw^":chop" Rd5,rss5 EndPacket is iclass=8 & op2127=0x45 & op0813=0 & op0507=1 & rss5 & Rd5 & $(END_PACKET) { + # TODO: Exceptional conditions are not implemented + float:8 = float2float(rss5); + Rd5 = chopFloat2UInt(float); + build EndPacket; +} + +# (v5,8) convert_df2w -- "Rd = convert_df2w ( Rss )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 0 0 0 1 0 0 s s s s s P P + + + + + + 0 0 1 d d d d d + +:convert_df2w Rd5,rss5 EndPacket is iclass=8 & op2127=0x44 & op0813=0 & op0507=1 & rss5 & Rd5 & $(END_PACKET) { + # TODO: Rounding mode and other exceptional conditions are not implemented + Rd5 = trunc(rss5); + build EndPacket; +} + +# (v5,8) convert_df2w -- "Rd = convert_df2w ( Rss ) :chop" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 0 0 0 1 1 1 s s s s s P P + + + + + + 0 0 1 d d d d d + +:convert_df2w^":chop" Rd5,rss5 EndPacket is iclass=8 & op2127=0x47 & op0813=0 & op0507=1 & rss5 & Rd5 & $(END_PACKET) { + # TODO: Exceptional conditions are not implemented + Rd5 = trunc(rss5); + build EndPacket; +} + +# (v5,8) convert_d2df -- "Rdd = convert_d2df ( Rss )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 0 0 0 1 1 1 s s s s s P P 0 + + + + + 0 1 1 d d d d d + +:convert_d2df Rdd5,rss5 EndPacket is iclass=8 & op2127=0x07 & op0813=0 & op0507=3 & rss5 & Rdd5 & $(END_PACKET) { + Rdd5 = int2float(rss5); + build EndPacket; +} + +# (v5,8) convert_ud2df -- "Rdd = convert_ud2df ( Rss )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 0 0 0 1 1 1 s s s s s P P 0 + + + + + 0 1 0 d d d d d + +:convert_ud2df Rdd5,rss5 EndPacket is iclass=8 & op2127=0x07 & op0813=0 & op0507=2 & rss5 & Rdd5 & $(END_PACKET) { + tmp:9 = zext(rss5); + Rdd5 = int2float(tmp); + build EndPacket; +} + +# (v5,8) convert_uw2df -- "Rdd = convert_uw2df ( Rs )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 1 0 0 1 + + s s s s s P P + + + + + + 0 0 1 d d d d d + +:convert_uw2df Rdd5,rs5 EndPacket is iclass=8 & op2127=0x24 & op0813=0 & op0507=1 & rs5 & Rdd5 & $(END_PACKET) { + tmp:9 = zext(rs5); + Rdd5 = int2float(tmp); + build EndPacket; +} + +# (v5,8) convert_w2df -- "Rdd = convert_w2df ( Rs )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 1 0 0 1 + + s s s s s P P + + + + + + 0 1 0 d d d d d + +:convert_w2df Rdd5,rs5 EndPacket is iclass=8 & op2127=0x24 & op0813=0 & op0507=2 & rs5 & Rdd5 & $(END_PACKET) { + Rdd5 = int2float(rs5); + build EndPacket; +} + +# (v5,14) sfadd -- "Rd = sfadd ( Rs, Rt )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 1 1 0 0 0 s s s s s P P 0 t t t t t 0 0 0 d d d d d + +:sfadd Rd5,rs5,rt5 EndPacket is iclass=14 & op2127=0x58 & op13=0 & op0507=0 & rs5 & rt5 & Rd5 & $(END_PACKET) { + Rd5 = rs5 f+ rt5; + build EndPacket; +} + +# (v5,8) sfclass -- "Pd = sfclass ( Rs, #u5 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 1 0 1 1 1 1 s s s s s P P 0 i i i i i + + + + + + d d + +define pcodeop isClassifiedFloat; + +:sfclass Pd2,rs5,Uimm8_0812 EndPacket is iclass=8 & op2127=0x2f & op13=0 & op0207=0 & Uimm8_0812 & rs5 & Pd2 & $(END_PACKET) { + float:4 = float2float(rs5); + bool:1 = isClassifiedFloat(float,Uimm8_0812); + Pd2 = Pd2 & ((bool != 0) * 0xff); + build EndPacket; +} + +# (v5,12) sfcmp.ge -- "Pd = sfcmp.ge ( Rs, Rt )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 1 1 1 1 1 1 s s s s s P P + t t t t t 0 0 0 + + + d d + +:sfcmp.ge Pd2,rs5,rt5 EndPacket is iclass=12 & op2127=0x3f & op13=0 & op0507=0 & op0204=0 & rs5 & rt5 & Pd2 & $(END_PACKET) { + Pd2 = Pd2 & ((rt5 f<= rs5) * 0xff); + build EndPacket; +} + +# (v5,12) sfcmp.uo -- "Pd = sfcmp.uo ( Rs, Rt )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 1 1 1 1 1 1 s s s s s P P + t t t t t 0 0 1 + + + d d + +:sfcmp.uo Pd2,rs5,rt5 EndPacket is iclass=12 & op2127=0x3f & op13=0 & op0507=1 & op0204=0 & rs5 & rt5 & Pd2 & $(END_PACKET) { + float1:4 = float2float(rs5); + float2:4 = float2float(rt5); + bool:1 = nan(float1) || nan(float2); + Pd2 = Pd2 & ((bool != 0) * 0xff); + build EndPacket; +} + +# (v5,12) sfcmp.eq -- "Pd = sfcmp.eq ( Rs, Rt )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 1 1 1 1 1 1 s s s s s P P + t t t t t 0 1 1 + + + d d + +:sfcmp.eq Pd2,rs5,rt5 EndPacket is iclass=12 & op2127=0x3f & op13=0 & op0507=3 & op0204=0 & rs5 & rt5 & Pd2 & $(END_PACKET) { + Pd2 = Pd2 & ((rt5 f== rs5) * 0xff); + build EndPacket; +} + +# (v5,12) sfcmp.gt -- "Pd = sfcmp.gt ( Rs, Rt )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 0 0 1 1 1 1 1 1 s s s s s P P + t t t t t 1 0 0 + + + d d + +:sfcmp.gt Pd2,rs5,rt5 EndPacket is iclass=12 & op2127=0x3f & op13=0 & op0507=4 & op0204=0 & rs5 & rt5 & Pd2 & $(END_PACKET) { + Pd2 = Pd2 & ((rs5 f> rt5) * 0xff); + build EndPacket; +} + +# (v5,14) sffixupd -- "Rd = sffixupd ( Rs, Rt )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 1 1 1 1 0 s s s s s P P 0 t t t t t 0 0 1 d d d d d +define pcodeop sffixupd; +:sffixupd Rd5,rs5,rt5 EndPacket is iclass=14 & op2127=0x5e & op13=0 & op0507=1 & rs5 & rt5 & Rd5 & $(END_PACKET) { + Rd5 = sffixupd(rs5, rt5); + build EndPacket; +} + +# (v5,14) sffixupn -- "Rd = sffixupn ( Rs, Rt )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 1 1 1 1 0 s s s s s P P 0 t t t t t 0 0 0 d d d d d +define pcodeop sffixupn; +:sffixupn Rd5,rs5,rt5 EndPacket is iclass=14 & op2127=0x5e & op13=0 & op0507=0 & rs5 & rt5 & Rd5 & $(END_PACKET) { + Rd5 = sffixupn(rs5, rt5); + build EndPacket; +} + +# (v5,8) sffixupr -- "Rd = sffixupr ( Rs )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 0 1 1 1 0 1 s s s s s P P + + + + + + 0 0 0 d d d d d +define pcodeop sffixupr; +:sffixupr Rd5,rs5 EndPacket is iclass=8 & op2127=0x5d & op0813=0 & op0507=0 & rs5 & Rd5 & $(END_PACKET) { + Rd5 = sffixupr(rs5); + build EndPacket; +} + +# (v5,13) sfmake -- "Rd = sfmake ( #u10 ) :neg" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 1 1 0 0 1 i + + + + + P P i i i i i i i i i d d d d d + +:sfmake^":neg" Rd5,Uimm16_21_0513 EndPacket is iclass=13 & op2227=0x19 & op1620=0 & Uimm16_21_0513 & Rd5 & $(END_PACKET) { + Rd5 = int2float(-Uimm16_21_0513); # TODO: assumed functionality + build EndPacket; +} + +# (v5,13) sfmake -- "Rd = sfmake ( #u10 ) :pos" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 1 1 0 0 0 i + + + + + P P i i i i i i i i i d d d d d + +:sfmake^":pos" Rd5,Uimm16_21_0513 EndPacket is iclass=13 & op2227=0x18 & op1620=0 & Uimm16_21_0513 & Rd5 & $(END_PACKET) { + Rd5 = int2float(Uimm16_21_0513); # TODO: assumed functionality + build EndPacket; +} + +# (v5,14) sfmax -- "Rd = sfmax ( Rs, Rt )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 1 1 1 0 0 s s s s s P P 0 t t t t t 0 0 0 d d d d d + +:sfmax Rd5,rs5,rt5 EndPacket is iclass=14 & op2127=0x5c & op13=0 & op0507=0 & rs5 & rt5 & Rd5 & $(END_PACKET) { + if (nan(rs5) || (rs5 f< rt5)) goto ; + Rd5 = rs5; + goto ; + + Rd5 = rt5; + + build EndPacket; +} + +# (v5,14) sfmin -- "Rd = sfmin ( Rs, Rt )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 1 1 1 0 0 s s s s s P P 0 t t t t t 0 0 1 d d d d d + +:sfmin Rd5,rs5,rt5 EndPacket is iclass=14 & op2127=0x5c & op13=0 & op0507=1 & rs5 & rt5 & Rd5 & $(END_PACKET) { + if (nan(rs5) || (rt5 f< rs5)) goto ; + Rd5 = rs5; + goto ; + + Rd5 = rt5; + + build EndPacket; +} + +# (v5,14) sfmpy -- "Rd = sfmpy ( Rs, Rt )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 1 1 0 1 0 s s s s s P P 0 t t t t t 0 0 0 d d d d d + +:sfmpy Rd5,rs5,rt5 EndPacket is iclass=14 & op2127=0x5a & op13=0 & op0507=0 & rs5 & rt5 & Rd5 & $(END_PACKET) { + Rd5 = rs5 f* rt5; + build EndPacket; +} + +# (v5,14) sfmpy+= -- "Rx += sfmpy ( Rs, Rt )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 1 0 0 0 s s s s s P P 0 t t t t t 1 0 0 x x x x x + +:sfmpy+= Rd5,rs5,rt5 EndPacket is iclass=14 & op2127=0x78 & op13=0 & op0507=4 & rs5 & rt5 & Rd5 & rd5 & $(END_PACKET) { + Rd5 = rd5 f+ (rs5 f* rt5); + build EndPacket; +} + +# (v5,14) sfmpy+= -- "Rx += sfmpy ( Rs, Rt, Pu ) :scale" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 1 0 1 1 s s s s s P P 0 t t t t t 1 u u x x x x x + +:sfmpy+=^":scale" Rd5,rs5,rt5,pu0506 EndPacket is iclass=14 & op2127=0x7b & op13=0 & op7=1 & pu0506 & rs5 & rt5 & Rd5 & rd5 & $(END_PACKET) { + Rd5 = multiplyAddScale(Rd5, rs5, rt5); + build EndPacket; +} + +# (v5,14) sfmpy-= -- "Rx -= sfmpy ( Rs, Rt )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 1 0 0 0 s s s s s P P 0 t t t t t 1 0 1 x x x x x + +:sfmpy-= Rd5,rs5,rt5 EndPacket is iclass=14 & op2127=0x78 & op13=0 & op0507=5 & rs5 & rt5 & Rd5 & rd5 & $(END_PACKET) { + Rd5 = rd5 f- (rs5 f* rt5); + build EndPacket; +} + + + +# (v5,14) sfmpy+= -- "Rx += sfmpy ( Rs, Rt ) :lib" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 1 0 0 0 s s s s s P P 0 t t t t t 1 1 0 x x x x x + +:sfmpy+=^":lib" Rd5,rs5,rt5 EndPacket is iclass=14 & op2127=0x78 & op13=0 & op0507=6 & rs5 & rt5 & Rd5 & rd5 & $(END_PACKET) { + Rd5 = rd5 f+ (rs5 f* rt5); + build EndPacket; +} + +# (v5,14) sfmpy-= -- "Rx -= sfmpy ( Rs, Rt ) :lib" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 1 1 1 0 0 0 s s s s s P P 0 t t t t t 1 1 1 x x x x x + +:sfmpy-=^":lib" Rd5,rs5,rt5 EndPacket is iclass=14 & op2127=0x78 & op13=0 & op0507=7 & rs5 & rt5 & Rd5 & rd5 & $(END_PACKET) { + Rd5 = rd5 f- (rs5 f* rt5); + build EndPacket; +} + + + + +# (v5,14) sfsub -- "Rd = sfsub ( Rs, Rt )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 1 1 0 0 0 s s s s s P P 0 t t t t t 0 0 1 d d d d d + +:sfsub Rd5,rs5,rt5 EndPacket is iclass=14 & op2127=0x58 & op13=0 & op0507=1 & rs5 & rt5 & Rd5 & $(END_PACKET) { + Rd5 = rs5 f- rt5; + build EndPacket; +} + +# (v5,13) dfclass -- "Pd = dfclass ( Rss, #u5 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 1 1 0 0 1 0 0 s s s s s P P + 0 0 0 i i i i i 1 0 + d d + +:dfclass Pd2,rss5,Uimm8_0509 EndPacket is iclass=13 & op2127=0x64 & op1013=0 & op0204=4 & Uimm8_0509 & rss5 & Pd2 & $(END_PACKET) { + float:8 = float2float(rss5); + result:1 = isClassifiedFloat(float,Uimm8_0509); + Pd2 = Pd2 & result; + build EndPacket; +} + +# (v5,13) dfcmp.eq -- "Pd = dfcmp.eq ( Rss, Rtt )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 0 1 1 1 s s s s s P P + t t t t t 0 0 0 + + + d d + +:dfcmp.eq Pd2,rss5,rtt5 EndPacket is iclass=13 & op2127=0x17 & op13=0 & op0507=0 & op0204=0 & rss5 & rtt5 & Pd2 & $(END_PACKET) { + Pd2 = Pd2 & ((rtt5 f== rss5) * 0xff); + build EndPacket; +} + +# (v5,13) dfcmp.gt -- "Pd = dfcmp.gt ( Rss, Rtt )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 0 1 1 1 s s s s s P P + t t t t t 0 0 1 + + + d d + +:dfcmp.gt Pd2,rss5,rtt5 EndPacket is iclass=13 & op2127=0x17 & op13=0 & op0507=1 & op0204=0 & rss5 & rtt5 & Pd2 & $(END_PACKET) { + Pd2 = Pd2 & ((rss5 f> rtt5) * 0xff); + build EndPacket; +} + +# (v5,13) dfcmp.ge -- "Pd = dfcmp.ge ( Rss, Rtt )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 0 1 1 1 s s s s s P P + t t t t t 0 1 0 + + + d d + +:dfcmp.ge Pd2,rss5,rtt5 EndPacket is iclass=13 & op2127=0x17 & op13=0 & op0507=2 & op0204=0 & rss5 & rtt5 & Pd2 & $(END_PACKET) { + Pd2 = Pd2 & ((rtt5 f<= rss5) * 0xff); + build EndPacket; +} + +# (v5,13) dfcmp.uo -- "Pd = dfcmp.uo ( Rss, Rtt )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 0 0 1 0 1 1 1 s s s s s P P + t t t t t 0 1 1 + + + d d + +:dfcmp.uo Pd2,rss5,rtt5 EndPacket is iclass=13 & op2127=0x17 & op13=0 & op0507=3 & op0204=0 & rss5 & rtt5 & Pd2 & $(END_PACKET) { + float1:8 = float2float(rss5); + float2:8 = float2float(rtt5); + bool:1 = nan(float1) || nan(float2); + Pd2 = Pd2 & ((bool != 0) * 0xff); + build EndPacket; +} + +# (v5,13) dfmake -- "Rdd = dfmake ( #u10 ) :neg" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 1 0 0 1 0 1 i + + + + + P P i i i i i i i i i d d d d d + +:dfmake^":neg" Rdd5,Uimm16_21_0513 EndPacket is iclass=13 & op2227=0x25 & op1620=0 & Uimm16_21_0513 & Rdd5 & $(END_PACKET) { + Rdd5 = int2float(-Uimm16_21_0513); # TODO: assumed functionality + build EndPacket; +} + +# (v5,13) dfmake -- "Rdd = dfmake ( #u10 ) :pos" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 1 1 0 0 1 0 0 i + + + + + P P i i i i i i i i i d d d d d + +:dfmake^":pos" Rdd5,Uimm16_21_0513 EndPacket is iclass=13 & op2227=0x24 & op1620=0 & Uimm16_21_0513 & Rdd5 & $(END_PACKET) { + Rdd5 = int2float(Uimm16_21_0513); # TODO: assumed functionality + build EndPacket; +} + +# +# V65 Floating Point Instructions +# + +# (v65,8) sfinvsqrta -- "Rd,Pe = sfinvsqrta ( Rs )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 1 0 1 1 1 1 1 s s s s s P P + + + + + + 0 e e d d d d d + +:sfinvsqrta Rd5,pu0506,rs5 EndPacket is iclass=8 & op2127=0x5f & op0813=0 & op7=0 & pu0506_ & pu0506 & rs5 & Rd5 & $(END_PACKET) +unimpl + +# (v65,14) sfrecipa -- "Rd,Pe = sfrecipa ( Rs, Rt )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 1 1 1 1 1 s s s s s P P 0 t t t t t 1 e e d d d d d + +:sfrecipa Rd5,Pd0506,rs5,rt5 EndPacket is iclass=14 & op2127=0x5f & op13=0 & op7=1 & Pd0506 & rs5 & rt5 & Rd5 & $(END_PACKET) { + src1:4 = rs5; + src2:4 = rt5; + Rd5 = reciprocal(src1, src2); + Pd0506 = Pd0506 & reciprocalAdjust(src1, src2); + build EndPacket; +} + +# +# V66 Floating Point Instructions +# + +# (v66,14) dfadd -- "Rdd = dfadd ( Rss, Rtt )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 0 0 0 0 s s s s s P P 0 t t t t t 0 1 1 d d d d d + +:dfadd Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x40 & op13=0 & op0507=3 & rss5 & rtt5 & Rdd5 & $(END_PACKET) { + Rdd5 = rss5 f+ rtt5; + build EndPacket; +} + +# (v66,14) dfsub -- "Rdd = dfsub ( Rss, Rtt )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 0 1 0 0 s s s s s P P 0 t t t t t 0 1 1 d d d d d + +:dfsub Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x44 & op13=0 & op0507=3 & rss5 & rtt5 & Rdd5 & $(END_PACKET) { + Rdd5 = rss5 f- rtt5; + build EndPacket; +} + +# +# V67 Floating Point Instructions +# + +# (v67,14) dfmax -- "Rdd = dfmax ( Rss, Rtt )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 0 0 0 1 s s s s s P P 0 t t t t t 0 1 1 d d d d d + +:dfmax Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x41 & op13=0 & op0507=3 & rss5 & rtt5 & Rdd5 & $(END_PACKET) { + if (nan(rss5) || (rss5 f< rtt5)) goto ; + Rdd5 = rss5; + goto ; + + Rdd5 = rtt5; + + build EndPacket; +} + +# (v67,14) dfmin -- "Rdd = dfmin ( Rss, Rtt )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 0 1 1 0 s s s s s P P 0 t t t t t 0 1 1 d d d d d + +:dfmin Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x46 & op13=0 & op0507=3 & rss5 & rtt5 & Rdd5 & $(END_PACKET) { + if (nan(rss5) || (rtt5 f< rss5)) goto ; + Rdd5 = rss5; + goto ; + + Rdd5 = rtt5; + + build EndPacket; +} + +# (v5,14) c -- "Rdd = dfmpyfix ( Rss, Rtt )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 0 0 1 0 s s s s s P P 0 t t t t t 0 1 1 d d d d d + +define pcodeop dfmpyfix; +:dfmpyfix Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x42 & op13=0 & op0507=3 & rss5 & rtt5 & Rdd5 & $(END_PACKET) { + Rdd5 = dfmpyfix(rss5, rtt5); + build EndPacket; +} + +@ifndef ADD_DP_OPS + +# (v67,14) dfmpyhh+= -- "Rxx += dfmpyhh ( Rss, Rtt )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 1 0 1 0 0 s s s s s P P 0 t t t t t 0 1 1 x x x x x + +define pcodeop dfmpyhh; +:dfmpyhh+= Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x54 & op13=0 & op0507=3 & rss5 & rtt5 & Rdd5 & rdd5 & $(END_PACKET) { + Rdd5 = dfmpyhh(rdd5, rss5, rtt5); + build EndPacket; +} + +# (v67,14) dfmpylh+= -- "Rxx += dfmpylh ( Rss, Rtt )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 1 0 0 0 0 s s s s s P P 0 t t t t t 0 1 1 x x x x x + +define pcodeop dfmpylh; +:dfmpylh+= Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x50 & op13=0 & op0507=3 & rss5 & rtt5 & Rdd5 & rdd5 & $(END_PACKET) { + Rdd5 = dfmpylh(rdd5, rss5, rtt5); + build EndPacket; +} + +# (v5,14) dfmpyll -- "Rdd = dfmpyll ( Rss, Rtt )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 0 1 0 1 s s s s s P P 0 t t t t t 0 1 1 d d d d d + +define pcodeop dfmpyll; +:dfmpyll Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x45 & op13=0 & op0507=3 & rss5 & rtt5 & Rdd5 & $(END_PACKET) { + Rdd5 = dfmpyll(rss5, rtt5); + build EndPacket; +} + +@endif # not ADD_DP_OPS + + +############################################################################################################# +# +# WARNING: The following instructions were discovered within various QEMU revisions not associated with a +# specific processor version that we have been able to identify. These instructions are for experimental +# use only and may be intended for QEMU development testing only. +# +############################################################################################################# + +@ifdef ADD_DP_OPS + +# (??,14) dffixupn -- "Rdd = dffixupn ( Rss, Rtt )" +# NOTE: replaces V67 dfmpyll +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 0 1 0 1 s s s s s P P 0 t t t t t 0 1 1 d d d d d + +define pcodeop dffixupn; +:dffixupn Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x45 & op13=0 & op0507=3 & rss5 & rtt5 & Rdd5 & $(END_PACKET) { + Rdd5 = dffixupn(rss5, rtt5); + build EndPacket; +} + +# (??,14) dffixupd -- "Rdd = dffixupd ( Rss, Rtt )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 0 0 1 1 s s s s s P P 0 t t t t t 0 1 1 d d d d d + +define pcodeop dffixupd; +:dffixupd Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x43 & op13=0 & op0507=3 & rss5 & rtt5 & Rdd5 & $(END_PACKET){ + Rdd5 = dffixupd(rss5, rtt5); + build EndPacket; +} + +# (??,14) dfrecipa -- "Rdd,Pe = dfrecipa ( Rss, Rtt )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 0 1 1 1 s s s s s P P 0 t t t t t 0 e e d d d d d + +:dfrecipa Rdd5,pu0506,rss5,rtt5 EndPacket is iclass=14 & op2127=0x47 & op13=0 & op7=0 & pu0506_ & pu0506 & rss5 & rtt5 & Rdd5 & $(END_PACKET) +unimpl + +# (??,14) dfmpyhh -- "Rdd += dfmpyhh ( Rss, Rtt )" +# NOTE: unexplained redfinition of V67 dfmpyhh += +# NOTE: conflicts with dfmpy+= :lib (see below) +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 1 0 0 1 0 s s s s s P P 0 t t t t t 0 1 1 x x x x x +# :dfmpyhh+= Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x52 & op13=0 & op0507=3 & rss5 & rtt5 & Rdd5 & rdd5 & $(END_PACKET) +# unimpl + +# (??,14) dfmpy+= -- "Rxx += dfmpy ( Rss, Rtt )" +# NOTE: replaces V67 dfmpylh += +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 1 0 0 0 0 s s s s s P P 0 t t t t t 0 1 1 x x x x x + +:dfmpy+= Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x50 & op13=0 & op0507=3 & rss5 & rtt5 & Rdd5 & rdd5 & $(END_PACKET) { + Rdd5 = rdd5 f+ (rss5 f* rtt5); + build EndPacket; +} + +# (??,14) dfmpy-= -- "Rxx -= dfmpy ( Rss, Rtt )" +# NOTE: replaces V67 dfmpyhh += +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 1 0 1 0 0 s s s s s P P 0 t t t t t 0 1 1 x x x x x + +:dfmpy-= Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x54 & op13=0 & op0507=3 & rss5 & rtt5 & Rdd5 & rdd5 & $(END_PACKET) { + Rdd5 = rdd5 f- (rss5 f* rtt5); + build EndPacket; +} + +# (??,14) dfmpy+= -- "Rxx += dfmpy ( Rss, Rtt ) :lib" +# NOTE: conflicts with replacement above for dfmpyhh += +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 1 0 0 1 0 s s s s s P P 0 t t t t t 0 1 1 x x x x x + +:dfmpy+=^":lib" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x52 & op13=0 & op0507=3 & rss5 & rtt5 & Rdd5 & rdd5 & $(END_PACKET) { + Rdd5 = rdd5 f+ (rss5 f* rtt5); + build EndPacket; +} + +# (??,14) dfmpy-= -- "Rxx -= dfmpy ( Rss, Rtt ) :lib" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 1 0 1 1 0 s s s s s P P 0 t t t t t 0 1 1 x x x x x + +:dfmpy-=^":lib" Rdd5,rss5,rtt5 EndPacket is iclass=14 & op2127=0x56 & op13=0 & op0507=3 & rss5 & rtt5 & Rdd5 & rdd5 & $(END_PACKET) { + Rdd5 = rdd5 f- (rss5 f* rtt5); + build EndPacket; +} + +# (??,14) dfmpy+= -- "Rxx += dfmpy ( Rss, Rtt, Pu ) :scale" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 1 0 1 1 1 s s s s s P P 0 t t t t t 0 u u x x x x x + +:dfmpy+=^":scale" Rdd5,rss5,rtt5,pu0506 EndPacket is iclass=14 & op2127=0x57 & op13=0 & op7=0 & pu0506 & rss5 & rtt5 & Rdd5 & rdd5 & $(END_PACKET) { + Rdd5 = multiplyAddScale(Rdd5, rss5, rtt5); + build EndPacket; +} + +# (??,8) dffixupr -- "Rdd = dffixupr ( Rss )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 0 0 0 1 1 1 s s s s s P P 0 + + + + + 1 0 0 d d d d d +define pcodeop dffixupr; +:dffixupr Rdd5,rss5 EndPacket is iclass=8 & op2127=0x07 & op0813=0 & op0507=4 & rss5 & Rdd5 & $(END_PACKET) { + Rdd5 = dffixupr(rss5); + build EndPacket; +} + +# (??,8) dfinvsqrta -- "Rdd32 , Pe4 = dfinvsqrta ( Rss32 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 0 0 0 0 0 1 1 1 s s s s s P P 1 + + + + + 0 e e d d d d d + +:dfinvsqrta Rdd5,pu0506,rss5 EndPacket is iclass=8 & op2127=0x07 & op0813=0x20 & op7=0 & pu0506_ & pu0506 & rss5 & Rdd5 & $(END_PACKET) +unimpl + +@endif # ADD_DP_OPS diff --git a/Ghidra/Processors/Hexagon/data/languages/hexagon_hvx.sinc b/Ghidra/Processors/Hexagon/data/languages/hexagon_hvx.sinc new file mode 100644 index 0000000000..0b6ede08fe --- /dev/null +++ b/Ghidra/Processors/Hexagon/data/languages/hexagon_hvx.sinc @@ -0,0 +1,6537 @@ +# Qualcomm Hexagon HVX Instruction Set (V69) + +# NOTES: +# - HVX implemntation based upon V69 +# - HVX hardware supports either 64-byte or 128-byte vector lengths +# - Vector register write are comitted immediately - we assume assembler enforces read-after-write +# hazzards for vector registers so we do not shadow writes. + +# UNDERSTANDING / ASSUMPTIONS: +# - The term "forwarding" indicates that a vector update immediately modifies a tmp shadow +# register which may be read via a subequent .new access within the same execute packet. +# - The vector .cur update is taken to mean a non-forwarding register update that is +# committed to the register file at the end of the execute packet and not available for +# reading via a .new access. +# - All conditional instructions which are conditional are treated as non-forwarding. +# - Unless specified as a .cur update, all unconditional vector register updates are treated +# as "forwarding" and commit to register file and the end of the execute packet. + +# +# Vector Pair Operands (e.g., V0V1 ) +# + +# Vector pair unconditional write (0,4) (new vector store forwarded and comitted) +Vdd5: vdd5 is cond=0 & vdd5 & vdd5_ & SetVNRegVd5 { + export vdd5_; # must be updated unconditionally + <> + vdd5 = vdd5_; +} + +# Vector pair temporary write (0,4) (new vector store forwarded, not comitted) +Vdd5tmp: vdd5^".tmp" is vdd5_ & vdd5 & SetVNRegVd5 { + export vdd5_; # must be updated unconditionally +} + +# destination vector pair (0,4) - unconditional write-only use - see Vdd5 (used for lane naming only) +VddW_0004: Vdd5^".w" is Vdd5 { export Vdd5; } +VddH_0004: Vdd5^".h" is Vdd5 { export Vdd5; } +VddB_0004: Vdd5^".b" is Vdd5 { export Vdd5; } +VddUW_0004: Vdd5^".uw" is Vdd5 { export Vdd5; } +VddUH_0004: Vdd5^".uh" is Vdd5 { export Vdd5; } +VddUB_0004: Vdd5^".ub" is Vdd5 { export Vdd5; } +VddQF32_0004: Vdd5^".qf32" is Vdd5 { export Vdd5; } + +# source vector pair (0,4) - read-only use +Vss_0004:vdd5 is vdd5 { + tmp:$(HVX_VECTOR_PAIR_SIZE) = vdd5; + export tmp; +} + +# read-only use - see Vuu_0812 (used for lane naming only) +VssW_0004:Vss_0004^".w" is Vss_0004 { export Vss_0004; } + +# source vector pair (8,12) - read-only use +Vuu_0812:vuu5 is vuu5 { + tmp:$(HVX_VECTOR_PAIR_SIZE) = vuu5; + export tmp; +} + +# read-only use - see Vuu_0812 (used for lane naming only) +VuuW_0812:Vuu_0812^".w" is Vuu_0812 { export Vuu_0812; } +VuuH_0812:Vuu_0812^".h" is Vuu_0812 { export Vuu_0812; } +VuuB_0812:Vuu_0812^".b" is Vuu_0812 { export Vuu_0812; } +VuuUW_0812:Vuu_0812^".uw" is Vuu_0812 { export Vuu_0812; } +VuuUH_0812:Vuu_0812^".uh" is Vuu_0812 { export Vuu_0812; } +VuuUB_0812:Vuu_0812^".ub" is Vuu_0812 { export Vuu_0812; } +VuuQF32_0812: Vuu_0812^".qf32" is Vuu_0812 { export Vuu_0812; } + +# source vector pair (16,20) - read-only use +Vvv_1620:vvv5 is vvv5 { + tmp:$(HVX_VECTOR_PAIR_SIZE) = vvv5; + export tmp; +} + +# read-only use - see Vvv_1620 (used for lane naming only) +VvvW_1620:Vvv_1620^".w" is Vvv_1620 { export Vvv_1620; } +VvvH_1620:Vvv_1620^".h" is Vvv_1620 { export Vvv_1620; } +VvvB_1620:Vvv_1620^".b" is Vvv_1620 { export Vvv_1620; } +VvvUW_1620:Vvv_1620^".uw" is Vvv_1620 { export Vvv_1620; } +VvvUH_1620:Vvv_1620^".uh" is Vvv_1620 { export Vvv_1620; } +VvvUB_1620:Vvv_1620^".ub" is Vvv_1620 { export Vvv_1620; } + +# +# Single Vector Operands (e.g., V0) +# + +# Vector unconditional write (new vector store forwarded and comitted) +Vd5: vd5 is cond=0 & vd5 & vd5_ & SetVNRegVd5 { + export vd5_; # must be updated unconditionally + <> + vd5 = vd5_; +} + +# Vector .cur unconditional write (not-forwarded, unconditionally committed at end of packet) +Vd5cur: vd5^".cur" is cond=0 & vd5 & vd5_{ + export vd5_; # must be updated unconditionally + <> + vd5 = vd5_; +} +# Vector .cur conditional write (not-forwarded, conditionally committed at end of packet) +Vd5cur: vd5^".cur" is cond=1 & vd5 & vd5_ { + export vd5_; + <> + if (ConditionReg == 0) goto ; + vd5 = vd5_; + +} + +# Vector temporary write (new vector store forwarded, not comitted) +Vd5tmp: vd5^".tmp" is vd5 & vd5_ & SetVNRegVd5 { + export vd5_; +} + +# destination vector - unconditional write-only use - see Vd5 (used for lane naming only) +VdW_0004: Vd5^".w" is Vd5 { export Vd5; } +VdH_0004: Vd5^".h" is Vd5 { export Vd5; } +VdB_0004: Vd5^".b" is Vd5 { export Vd5; } +VdUW_0004: Vd5^".uw" is Vd5 { export Vd5; } +VdUH_0004: Vd5^".uh" is Vd5 { export Vd5; } +VdUB_0004: Vd5^".ub" is Vd5 { export Vd5; } +VdHF_0004: Vd5^".hf" is Vd5 { export Vd5; } +VdSF_0004: Vd5^".sf" is Vd5 { export Vd5; } +VdQF16_0004: Vd5^".qf16" is Vd5 { export Vd5; } +VdQF32_0004: Vd5^".qf32" is Vd5 { export Vd5; } + +# source vector (0,4) - read-only use +Vs_0004: vs5 is vs5 { + tmp:$(HVX_VECTOR_SIZE) = vs5; + export tmp; +} + +# source vector - read-only use - see Vs_0004 (used for lane naming only) +VsW_0004:Vs_0004^".w" is Vs_0004 { export Vs_0004; } +VsH_0004:Vs_0004^".h" is Vs_0004 { export Vs_0004; } +VsB_0004:Vs_0004^".b" is Vs_0004 { export Vs_0004; } + +# source vector (8,12) - read-only use +Vu_0812: vu5 is vu5 { + tmp:$(HVX_VECTOR_SIZE) = vu5; + export tmp; +} + +# source vector - read-only use - see Vu_0812 (used for lane naming only) +VuW_0812: Vu_0812^".w" is Vu_0812 { export Vu_0812; } +VuH_0812: Vu_0812^".h" is Vu_0812 { export Vu_0812; } +VuB_0812: Vu_0812^".b" is Vu_0812 { export Vu_0812; } +VuUW_0812: Vu_0812^".uw" is Vu_0812 { export Vu_0812; } +VuUH_0812: Vu_0812^".uh" is Vu_0812 { export Vu_0812; } +VuUB_0812: Vu_0812^".ub" is Vu_0812 { export Vu_0812; } +VuSF_0812: Vu_0812^".sf" is Vu_0812 { export Vu_0812; } +VuHF_0812: Vu_0812^".hf" is Vu_0812 { export Vu_0812; } +VuQF16_0812: Vu_0812^".qf16" is Vu_0812 { export Vu_0812; } +VuQF32_0812: Vu_0812^".qf32" is Vu_0812 { export Vu_0812; } + +# source vector (16,20) - read-only use +Vv_1620: vv5 is vv5 { + tmp:$(HVX_VECTOR_SIZE) = vv5; + export tmp; +} + +# source vector - read-only use - see Vv_1620 (used for lane naming only) +VvW_1620: Vv_1620^".w" is Vv_1620 { export Vv_1620; } +VvH_1620: Vv_1620^".h" is Vv_1620 { export Vv_1620; } +VvB_1620: Vv_1620^".b" is Vv_1620 { export Vv_1620; } +VvUH_1620: Vv_1620^".uh" is Vv_1620 { export Vv_1620; } +VvUW_1620: Vv_1620^".uw" is Vv_1620 { export Vv_1620; } +VvUB_1620: Vv_1620^".ub" is Vv_1620 { export Vv_1620; } +VvSF_1620: Vv_1620^".sf" is Vv_1620 { export Vv_1620; } +VvHF_1620: Vv_1620^".hf" is Vv_1620 { export Vv_1620; } +VvQF16_1620: Vv_1620^".qf16" is Vv_1620 { export Vv_1620; } +VvQF32_1620: Vv_1620^".qf32" is Vv_1620 { export Vv_1620; } + +# source vector (19,23) - read-only use +Vz_1923: vz5 is vz5 { + tmp:$(HVX_VECTOR_SIZE) = vz5; + export tmp; +} + +# source vector - read-only use - see Vz_1923 (used for lane naming only) +VzW_1923: Vz_1923^".w" is Vz_1923 { export Vz_1923; } +VzH_1923: Vz_1923^".h" is Vz_1923 { export Vz_1923; } +VzB_1923: Vz_1923^".b" is Vz_1923 { export Vz_1923; } +VzUW_1923: Vz_1923^".uw" is Vz_1923 { export Vz_1923; } +VzUH_1923: Vz_1923^".uh" is Vz_1923 { export Vz_1923; } + +# +# General register operand w/ lanes +# + +# source scalar register pair - read-only use - see rxx5 (used for lane naming only) +RttH_1620: rxx5^".h" is rxx5 { tmp:8 = rxx5; export tmp; } +RttUH_1620: rxx5^".uh" is rxx5 { tmp:8 = rxx5; export tmp; } + +# source scalar register - read-only use - see rx5 (used for lane naming only) +RtH_1620: rx5^".h" is rx5 { tmp:4 = rx5; export tmp; } +RtB_1620: rx5^".b" is rx5 { tmp:4 = rx5; export tmp; } +RtUH_1620: rx5^".uh" is rx5 { tmp:4 = rx5; export tmp; } +RtUB_1620: rx5^".ub" is rx5 { tmp:4 = rx5; export tmp; } + +# +# Vector Predicate operands +# + +# Corresponds to Qd4 in documentation (vector predicate destination Q0..Q3, handles unconditional commit) +Qd2: qv0001 is qv0001 & cond=0 { + tmp:$(HVX_PREDICATE_SIZE) = qv0001; + export tmp; + <> + qv0001 = tmp; +} + +# Vector predicate source qv1112 with invert based on op5 +Qv_1112_S05: qv1112 is qv1112 & op5=0 { + tmp:$(HVX_PREDICATE_SIZE) = qv1112; + export tmp; +} +Qv_1112_S05: "!"^qv1112 is qv1112 & op5=1 { + tmp:$(HVX_PREDICATE_SIZE) = ~qv1112; + export tmp; +} + + +# Predicate Register Condition (least significant bit only) + +# map: Ps_0506 -> PuCond0506_S21 +# map: Px_0506 -> pu0506 (read only register use) + +VPuCond0506_S21: ".if("pu0506name")" is op21=0 & pu0506 & pu0506name [cond=1;] { + condition:1 = (pu0506 & 1); + <> + ConditionReg = condition; + <> + ConditionReg = condition; +} +VPuCond0506_S21: ".if(!"pu0506name")" is op21=1 & pu0506 & pu0506name [cond=1;] { + condition:1 = !(pu0506 & 1); + <> + ConditionReg = condition; + <> + ConditionReg = condition; +} + +# Predicate Register Condition (least significant bit only) +# map: Pv_1112 -> PuCond1112_S05 + +VPuCond1112_S05: ".if("pu1112name")" is op5=0 & pu1112 & pu1112name [cond=1;] { + condition:1 = (pu1112 & 1); + <> + ConditionReg = condition; + <> + ConditionReg = condition; +} +VPuCond1112_S05: ".if(!"pu1112name")" is op5=1 & pu1112 & pu1112name [cond=1;] { + condition:1 = !(pu1112 & 1); + <> + ConditionReg = condition; + <> + ConditionReg = condition; +} + + +# Signed immediate s3 +Simm32_0810: "#"^s0810 is s0810 { export *[const]:4 s0810; } + +# Signed immediate s4 (split into s13 and i0810) +Simm32_0810_13: "#"^simm is s13 & i0810 [ simm = (s13 << 3) | i0810; ] { export *[const]:4 simm; } + +# Vector memory (rx++Mu) load/store vector-sized ram address +# -- 'cond=1' context must be set by conditional instructions! +VAlignMemAddrRxAIMu: "("^rx5^"++"^mu^")" is cond=0 & rx5 & rx5_ & mu { + tmp:4 = rx5 + mu; + ptr:4 = rx5 & ~(0x3F); # align offset + export *[ram]:$(HVX_VECTOR_SIZE) ptr; + <> + rx5 = tmp; +} +VAlignMemAddrRxAIMu: "("^rx5^"++"^mu^")" is cond=1 & rx5 & rx5_ & mu { + tmp:4 = rx5 + mu; + ptr:4 = rx5 & ~(0x3F); # align offset + export *[ram]:$(HVX_VECTOR_SIZE) ptr; +<> + if (ConditionReg == 0) goto ; + rx5 = tmp; + +} + +# Vector memory (rx++Mu) unaligned load/store vector-sized ram address +# -- 'cond=1' context must be set by conditional instructions! +VMemAddrRxAIMu: "("^rx5^"++"^mu^")" is cond=0 & rx5 & rx5_ & mu { + tmp:4 = rx5 + mu; + export *[ram]:$(HVX_VECTOR_SIZE) rx5; + <> + rx5 = tmp; +} +VMemAddrRxAIMu: "("^rx5^"++"^mu^")" is cond=1 & rx5 & rx5_ & mu { + tmp:4 = rx5 + mu; + export *[ram]:$(HVX_VECTOR_SIZE) rx5; +<> + if (ConditionReg == 0) goto ; + rx5 = tmp; + +} + +# Vector memory (rx++#s3) load/store vector-sized ram address +# -- 'cond=1' context must be set by conditional instructions! +VAlignMemAddrRxAIS3: "("^rx5^"++"^Simm32_0810^")" is cond=0 & rx5 & rx5_ & Simm32_0810 { + tmp:4 = rx5 + (Simm32_0810 * $(HVX_VECTOR_SIZE) ); + ptr:4 = rx5 & ~(0x3F); # align offset + export *[ram]:$(HVX_VECTOR_SIZE) ptr; + <> + rx5 = tmp; +} +VAlignMemAddrRxAIS3: "("^rx5^"++"^Simm32_0810^")" is cond=1 & rx5 & rx5_ & Simm32_0810 { + tmp:4 = rx5 + (Simm32_0810 * $(HVX_VECTOR_SIZE) ); + ptr:4 = rx5 & ~(0x3F); # align offset + export *[ram]:$(HVX_VECTOR_SIZE) ptr; +<> + if (ConditionReg == 0) goto ; + rx5 = tmp; + +} + +# Vector memory (rx++#s3) unaligned load/store vector-sized ram address +# -- 'cond=1' context must be set by conditional instructions! +VMemAddrRxAIS3: "("^rx5^"++"^Simm32_0810^")" is cond=0 & rx5 & rx5_ & Simm32_0810 { + tmp:4 = rx5 + (Simm32_0810 * $(HVX_VECTOR_SIZE) ); + export *[ram]:$(HVX_VECTOR_SIZE) rx5; + <> + rx5 = tmp; +} +VMemAddrRxAIS3: "("^rx5^"++"^Simm32_0810^")" is cond=1 & rx5 & rx5_ & Simm32_0810 { + tmp:4 = rx5 + (Simm32_0810 * $(HVX_VECTOR_SIZE) ); + export *[ram]:$(HVX_VECTOR_SIZE) rx5; +<> + if (ConditionReg == 0) goto ; + rx5 = tmp; + +} + +# Vector memory (rx+#s4) load/store vector-sized ram address +VAlignMemAddrRxS4: "("^rx5^"+"^Simm32_0810_13^")" is rx5 & Simm32_0810_13 { + ptr:4 = rx5 + (Simm32_0810_13 * $(HVX_VECTOR_SIZE) ); + ptr = ptr & ~(0x3F); # align offset + export *[ram]:$(HVX_VECTOR_SIZE) ptr; +} +VAlignMemAddrRxS4: "("^rx5^")" is rx5 & op0810=0 & op13=0 { + ptr = rx5 & ~(0x3F); # align offset + export *[ram]:$(HVX_VECTOR_SIZE) ptr; +} + +# Vector memory (rx+#s4) unaligned load/store vector-sized ram address +VMemAddrRxS4: "("^rx5^"+"^Simm32_0810_13^")" is rx5 & Simm32_0810_13 { + ptr:4 = rx5 + (Simm32_0810_13 * $(HVX_VECTOR_SIZE) ); + export *[ram]:$(HVX_VECTOR_SIZE) ptr; +} +VMemAddrRxS4: "("^rx5^")" is rx5 & op0810=0 & op13=0 { + export *[ram]:$(HVX_VECTOR_SIZE) rx5; +} + + +# optional nontemporal hint :nt +ntHint22: is op22=0 { } +ntHint22:":nt" is op22=1 { } + +# +# HVX Instructions +# + +# (hvx,1) "vwhist256" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 - - 0 - - 0 0 0 P P 1 - 0 0 1 0 1 0 0 - - - - - + +:vwhist256 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x0 & op1617=0x0 & op13=0x1 & op0911=0x1 & op0508=0x4 & $(END_PACKET) unimpl + +# (hvx,1) vwhist256 -- "vwhist256:sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 - - 0 - - 0 0 0 P P 1 - 0 0 1 1 1 0 0 - - - - - + +:vwhist256^":sat" EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x0 & op1617=0x0 & op13=0x1 & op0911=0x1 & op0508=0xc & $(END_PACKET) unimpl + +# (hvx,1) "vwhist128" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 - - 0 - - 0 0 0 P P 1 - 0 1 0 - 1 0 0 - - - - - + +:vwhist128 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x0 & op1617=0x0 & op13=0x1 & op0911=0x2 & op0507=0x4 & $(END_PACKET) unimpl + +# (hvx,1) vwhist128 -- "vwhist128(#u1)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 - - 0 - - 0 0 0 P P 1 - 0 1 1 i 1 0 0 - - - - - + +:vwhist128 "#"^i8 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x0 & op1617=0x0 & op13=0x1 & op0911=0x3 & op0507=0x4 & i8 & $(END_PACKET) unimpl + +# (hvx,1) vwhist256 -- "vwhist256(Qv4)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 v v 0 - - 0 1 0 P P 1 - - 0 1 0 1 0 0 - - - - - + +:vwhist256 qv2223 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x0 & op1617=0x2 & op13=0x1 & op0810=0x2 & op0507=0x4 & qv2223 & $(END_PACKET) unimpl + +# (hvx,1) vwhist256 -- "vwhist256(Qv4):sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 v v 0 - - 0 1 0 P P 1 - - 0 1 1 1 0 0 - - - - - + +:vwhist256^":sat" qv2223 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x0 & op1617=0x2 & op13=0x1 & op0810=0x3 & op0507=0x4 & qv2223 & $(END_PACKET) unimpl + +# (hvx,1) vwhist128 -- "vwhist128(Qv4)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 v v 0 - - 0 1 0 P P 1 - - 1 0 - 1 0 0 - - - - - + +:vwhist128 qv2223 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x0 & op1617=0x2 & op13=0x1 & op0910=0x2 & op0507=0x4 & qv2223 & $(END_PACKET) unimpl + +# (hvx,1) vwhist128 -- "vwhist128(Qv4,#u1)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 v v 0 - - 0 1 0 P P 1 - - 1 1 i 1 0 0 - - - - - + +:vwhist128 qv2223,"#"^i8 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x0 & op1617=0x2 & op13=0x1 & op0910=0x3 & op0507=0x4 & qv2223 & i8 & $(END_PACKET) unimpl + +# (hvx,1) and -- "Qd4=and(Qs4,Qt4)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 t t 0 - - - 1 1 P P 0 - - - s s 0 0 0 0 0 0 d d + +:and Qd2,qv0809,qv2223 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op1617=0x3 & op13=0x0 & op0207=0x0 & Qd2 & qv0809 & qv2223 & $(END_PACKET) { + Qd2 = qv0809 & qv2223; + build EndPacket; +} + +# (hvx,1) or -- "Qd4=or(Qs4,Qt4)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 t t 0 - - - 1 1 P P 0 - - - s s 0 0 0 0 0 1 d d + +:or Qd2,qv0809,qv2223 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op1617=0x3 & op13=0x0 & op0207=0x1 & Qd2 & qv0809 & qv2223 & $(END_PACKET) { + Qd2 = qv0809 | qv2223; + build EndPacket; +} + +# (hvx,1) xor -- "Qd4=xor(Qs4,Qt4)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 t t 0 - - - 1 1 P P 0 - - - s s 0 0 0 0 1 1 d d + +:xor Qd2,qv0809,qv2223 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op1617=0x3 & op13=0x0 & op0207=0x3 & Qd2 & qv0809 & qv2223 & $(END_PACKET) { + Qd2 = qv0809 ^ qv2223; + build EndPacket; +} + +# (hvx,1) or -- "Qd4=or(Qs4,!Qt4)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 t t 0 - - - 1 1 P P 0 - - - s s 0 0 0 1 0 0 d d + +:or Qd2,qv0809,"!"^qv2223 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op1617=0x3 & op13=0x0 & op0207=0x4 & Qd2 & qv0809 & qv2223 & $(END_PACKET) { + Qd2 = qv0809 | ~qv2223; + build EndPacket; +} + +# (hvx,1) and -- "Qd4=and(Qs4,!Qt4)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 t t 0 - - - 1 1 P P 0 - - - s s 0 0 0 1 0 1 d d + +:and Qd2,qv0809,"!"^qv2223 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op1617=0x3 & op13=0x0 & op0207=0x5 & Qd2 & qv0809 & qv2223 & $(END_PACKET) { + Qd2 = qv0809 & ~qv2223; + build EndPacket; +} + +# (hvx,1) vshuffe -- "Qd4.b=vshuffe(Qs4.h,Qt4.h)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 t t 0 - - - 1 1 P P 0 - - - s s 0 0 0 1 1 0 d d + +define pcodeop vshuffe_QhQh; + +:vshuffe Qd2^".b",qv0809^".h",qv2223^".h" EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op1617=0x3 & op13=0x0 & op0207=0x6 & Qd2 & qv0809 & qv2223 & $(END_PACKET) { + Qd2 = vshuffe_QhQh(qv0809,qv2223); + build EndPacket; +} + +# (hvx,1) vshuffe -- "Qd4.h=vshuffe(Qs4.w,Qt4.w)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 t t 0 - - - 1 1 P P 0 - - - s s 0 0 0 1 1 1 d d + +define pcodeop vshuffe_QwQw; + +:vshuffe Qd2^".h",qv0809^".w",qv2223^".w" EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op1617=0x3 & op13=0x0 & op0207=0x7 & Qd2 & qv0809 & qv2223 & $(END_PACKET) { + Qd2 = vshuffe_QhQh(qv0809,qv2223); + build EndPacket; +} + +# (hvx,1) vcombine -- "if (!Ps) Vdd=vcombine(Vu,Vv)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 1 0 0 1 0 v v v v v P P - u u u u u - s s d d d d d +# +# (hvx,1) vcombine -- "if (Ps) Vdd=vcombine(Vu,Vv)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 1 0 0 1 1 v v v v v P P - u u u u u - s s d d d d d + +define pcodeop vcombine; + +:vcombine^VPuCond0506_S21 vdd5,Vu_0812,Vv_1620 EndPacket is iclass=0x1 & op2227=0x29 & VPuCond0506_S21 & vdd5 & vdd5_ & SetNRegRd5 & Vu_0812 & Vv_1620 & $(END_PACKET) { + build VPuCond0506_S21; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + vdd5_ = vcombine(Vu_0812,Vv_1620); + + <> + if (ConditionReg == 0) goto ; + vdd5 = vdd5_; + +} + +# (hvx,1) vcombine -- "Vdd=vcombine(Vu,Vv)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 0 1 0 v v v v v P P 0 u u u u u 1 1 1 d d d d d + +:vcombine Vdd5,Vu_0812,Vv_1620 EndPacket is iclass=0x1 & op2127=0x7a & op13=0x0 & op0507=0x7 & Vdd5 & Vu_0812 & Vv_1620 & $(END_PACKET) { + Vdd5 = vcombine(Vu_0812,Vv_1620); + build EndPacket; +} + +# (hvx,1) vshuffoe -- "Vdd.h=vshuffoe(Vu.h,Vv.h)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 0 1 0 v v v v v P P 0 u u u u u 1 0 1 d d d d d + +define pcodeop vshuffoe_VhVh; + +:vshuffoe VddH_0004,VuH_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x7a & op13=0x0 & op0507=0x5 & VddH_0004 & VuH_0812 & VvH_1620 & $(END_PACKET) { + VddH_0004 = vshuffoe_VhVh(VuH_0812,VvH_1620); + build EndPacket; +} + +# (hvx,1) vshuffoe -- "Vdd.b=vshuffoe(Vu.b,Vv.b)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 0 1 0 v v v v v P P 0 u u u u u 1 1 0 d d d d d + +define pcodeop vshuffoe_VbVb; + +:vshuffoe VddB_0004,VuB_0812,VvB_1620 EndPacket is iclass=0x1 & op2127=0x7a & op13=0x0 & op0507=0x6 & VddB_0004 & VuB_0812 & VvB_1620 & $(END_PACKET) { + VddB_0004 = vshuffoe_VbVb(VuB_0812,VvB_1620); + build EndPacket; +} + +# (hvx,1) vswap -- "Vdd=vswap(Qt4,Vu,Vv)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 1 0 1 v v v v v P P 1 u u u u u - t t d d d d d + +define pcodeop vswap_QVwVw; + +:vswap Vdd5,qv0506,Vu_0812,Vv_1620 EndPacket is iclass=0x1 & op2127=0x75 & op13=0x1 & Vdd5 & qv0506 & Vu_0812 & Vv_1620 & $(END_PACKET) { + Vdd5 = vswap_QVwVw(qv0506,Vu_0812,Vv_1620); + build EndPacket; +} + +# (hvx,1) vzxt -- "Vdd.uh=vzxt(Vu.ub)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 - - 0 - - - 1 0 P P 0 u u u u u 0 0 1 d d d d d + +define pcodeop vzxt_Vub; + +:vzxt VddUH_0004,VuUB_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op1617=0x2 & op13=0x0 & op0507=0x1 & VddUH_0004 & VuUB_0812 & $(END_PACKET) { + VddUH_0004 = vzxt_Vub(VuUB_0812); + build EndPacket; +} + +# (hvx,1) vzxt -- "Vdd.uw=vzxt(Vu.uh)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 - - 0 - - - 1 0 P P 0 u u u u u 0 1 0 d d d d d + +define pcodeop vzxt_Vuh; + +:vzxt VddUW_0004,VuUH_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op1617=0x2 & op13=0x0 & op0507=0x2 & VddUW_0004 & VuUH_0812 & $(END_PACKET) { + VddUW_0004 = vzxt_Vuh(VuUH_0812); + build EndPacket; +} + +# (hvx,1) vsxt -- "Vdd.h=vsxt(Vu.b)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 - - 0 - - - 1 0 P P 0 u u u u u 0 1 1 d d d d d + +define pcodeop vsxt_Vb; + +:vsxt VddH_0004,VuB_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op1617=0x2 & op13=0x0 & op0507=0x3 & VddH_0004 & VuB_0812 & $(END_PACKET) { + VddH_0004 = vsxt_Vb(VuB_0812); + build EndPacket; +} + +# (hvx,1) vsxt -- "Vdd.w=vsxt(Vu.h)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 - - 0 - - - 1 0 P P 0 u u u u u 1 0 0 d d d d d + +define pcodeop Ww_vsxt_Vh; + +:vsxt VddW_0004,VuH_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op1617=0x2 & op13=0x0 & op0507=0x4 & VddW_0004 & VuH_0812 & $(END_PACKET) { + VddW_0004 = Ww_vsxt_Vh(VuH_0812); + build EndPacket; +} + +# (hvx,1) vadd -- "Vdd.b=vadd(Vuu.b,Vvv.b)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 0 1 1 v v v v v P P 0 u u u u u 1 0 0 d d d d d + +define pcodeop vadd_WbWb; + +:vadd VddB_0004,VuuB_0812,VvvB_1620 EndPacket is iclass=0x1 & op2127=0x63 & op13=0x0 & op0507=0x4 & VddB_0004 & VuuB_0812 & VvvB_1620 & $(END_PACKET) { + VddB_0004 = vadd_WbWb(VuuB_0812,VvvB_1620); + build EndPacket; +} + +# (hvx,1) vadd -- "Vdd.h=vadd(Vuu.h,Vvv.h)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 0 1 1 v v v v v P P 0 u u u u u 1 0 1 d d d d d + +define pcodeop vadd_WhWh; + +:vadd VddH_0004,VuuH_0812,VvvH_1620 EndPacket is iclass=0x1 & op2127=0x63 & op13=0x0 & op0507=0x5 & VddH_0004 & VuuH_0812 & VvvH_1620 & $(END_PACKET) { + VddH_0004 = vadd_WhWh(VuuH_0812,VvvH_1620); + build EndPacket; +} + +# (hvx,1) vadd -- "Vdd.w=vadd(Vuu.w,Vvv.w)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 0 1 1 v v v v v P P 0 u u u u u 1 1 0 d d d d d + +define pcodeop Ww_vadd_WwWw; + +:vadd VddW_0004,VuuW_0812,VvvW_1620 EndPacket is iclass=0x1 & op2127=0x63 & op13=0x0 & op0507=0x6 & VddW_0004 & VuuW_0812 & VvvW_1620 & $(END_PACKET) { + VddW_0004 = Ww_vadd_WwWw(VuuW_0812,VvvW_1620); + build EndPacket; +} + +# (hvx,1) vadd -- "Vdd.ub=vadd(Vuu.ub,Vvv.ub):sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 0 1 1 v v v v v P P 0 u u u u u 1 1 1 d d d d d + +define pcodeop vadd_WubWub_sat; + +:vadd^":sat" VddUB_0004,VuuUB_0812,VvvUB_1620 EndPacket is iclass=0x1 & op2127=0x63 & op13=0x0 & op0507=0x7 & VddUB_0004 & VuuUB_0812 & VvvUB_1620 & $(END_PACKET) { + VddUB_0004 = vadd_WubWub_sat(VuuUB_0812,VvvUB_1620); + build EndPacket; +} + +# (hvx,1) vadd -- "Vdd.uh=vadd(Vuu.uh,Vvv.uh):sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 0 u u u u u 0 0 0 d d d d d + +define pcodeop vadd_WuhWuh_sat; + +:vadd^":sat" VddUH_0004,VuuUH_0812,VvvUH_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x0 & op0507=0x0 & VddUH_0004 & VuuUH_0812 & VvvUH_1620 & $(END_PACKET) { + VddUH_0004 = vadd_WuhWuh_sat(VuuUH_0812,VvvUH_1620); + build EndPacket; +} + +# (hvx,1) vadd -- "Vdd.h=vadd(Vuu.h,Vvv.h):sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 0 u u u u u 0 0 1 d d d d d + +define pcodeop vadd_WhWh_sat; + +:vadd^":sat" VddH_0004,VuuH_0812,VvvH_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x0 & op0507=0x1 & VddH_0004 & VuuH_0812 & VvvH_1620 & $(END_PACKET) { + VddH_0004 = vadd_WhWh_sat(VuuH_0812,VvvH_1620); + build EndPacket; +} + +# (hvx,1) vadd -- "Vdd.w=vadd(Vuu.w,Vvv.w):sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 0 u u u u u 0 1 0 d d d d d + +define pcodeop Ww_vadd_WwWw_sat; + +:vadd^":sat" VddW_0004,VuuW_0812,VvvW_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x0 & op0507=0x2 & VddW_0004 & VuuW_0812 & VvvW_1620 & $(END_PACKET) { + VddW_0004 = Ww_vadd_WwWw_sat(VuuW_0812,VvvW_1620); + build EndPacket; +} + +# (hvx,1) vsub -- "Vdd.b=vsub(Vuu.b,Vvv.b)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 0 u u u u u 0 1 1 d d d d d + +define pcodeop vsub_WbWb; + +:vsub VddB_0004,VuuB_0812,VvvB_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x0 & op0507=0x3 & VddB_0004 & VuuB_0812 & VvvB_1620 & $(END_PACKET) { + VddB_0004 = vsub_WbWb(VuuB_0812,VvvB_1620); + build EndPacket; +} + +# (hvx,1) vsub -- "Vdd.h=vsub(Vuu.h,Vvv.h)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 0 u u u u u 1 0 0 d d d d d + +define pcodeop vsub_WhWh; + +:vsub VddH_0004,VuuH_0812,VvvH_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x0 & op0507=0x4 & VddH_0004 & VuuH_0812 & VvvH_1620 & $(END_PACKET) { + VddH_0004 = vsub_WhWh(VuuH_0812,VvvH_1620); + build EndPacket; +} + +# (hvx,1) vsub -- "Vdd.w=vsub(Vuu.w,Vvv.w)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 0 u u u u u 1 0 1 d d d d d + +define pcodeop Ww_vsub_WwWw; + +:vsub VddW_0004,VuuW_0812,VvvW_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x0 & op0507=0x5 & VddW_0004 & VuuW_0812 & VvvW_1620 & $(END_PACKET) { + VddW_0004 = Ww_vsub_WwWw(VuuW_0812,VvvW_1620); + build EndPacket; +} + +# (hvx,1) vsub -- "Vdd.ub=vsub(Vuu.ub,Vvv.ub):sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 0 u u u u u 1 1 0 d d d d d + +define pcodeop vsub_WubWub_sat; + +:vsub^":sat" VddUB_0004,VuuUB_0812,VvvUB_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x0 & op0507=0x6 & VddUB_0004 & VuuUB_0812 & VvvUB_1620 & $(END_PACKET) { + VddUB_0004 = vsub_WubWub_sat(VuuUB_0812,VvvUB_1620); + build EndPacket; +} + +# (hvx,1) vsub -- "Vdd.uh=vsub(Vuu.uh,Vvv.uh):sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 0 u u u u u 1 1 1 d d d d d + +define pcodeop vsub_WuhWuh_sat; + +:vsub^":sat" VddUH_0004,VuuUH_0812,VvvUH_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x0 & op0507=0x7 & VddUH_0004 & VuuUH_0812 & VvvUH_1620 & $(END_PACKET) { + VddUH_0004 = vsub_WuhWuh_sat(VuuUH_0812,VvvUH_1620); + build EndPacket; +} + +# (hvx,1) vsub -- "Vdd.h=vsub(Vuu.h,Vvv.h):sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 0 1 v v v v v P P 0 u u u u u 0 0 0 d d d d d + +define pcodeop vsub_WhWh_sat; + +:vsub^":sat" VddH_0004,VuuH_0812,VvvH_1620 EndPacket is iclass=0x1 & op2127=0x65 & op13=0x0 & op0507=0x0 & VddH_0004 & VuuH_0812 & VvvH_1620 & $(END_PACKET) { + VddH_0004 = vsub_WhWh_sat(VuuH_0812,VvvH_1620); + build EndPacket; +} + +# (hvx,1) vsub -- "Vdd.w=vsub(Vuu.w,Vvv.w):sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 0 1 v v v v v P P 0 u u u u u 0 0 1 d d d d d + +define pcodeop Ww_vsub_WwWw_sat; + +:vsub^":sat" VddW_0004,VuuW_0812,VvvW_1620 EndPacket is iclass=0x1 & op2127=0x65 & op13=0x0 & op0507=0x1 & VddW_0004 & VuuW_0812 & VvvW_1620 & $(END_PACKET) { + VddW_0004 = Ww_vsub_WwWw_sat(VuuW_0812,VvvW_1620); + build EndPacket; +} + +# (hvx,1) vadd -- "Vdd.b=vadd(Vuu.b,Vvv.b):sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 1 0 1 v v v v v P P 0 u u u u u 0 0 0 d d d d d + +define pcodeop vadd_WbWb_sat; + +:vadd^":sat" VddB_0004,VuuB_0812,VvvB_1620 EndPacket is iclass=0x1 & op2127=0x75 & op13=0x0 & op0507=0x0 & VddB_0004 & VuuB_0812 & VvvB_1620 & $(END_PACKET) { + VddB_0004 = vadd_WbWb_sat(VuuB_0812,VvvB_1620); + build EndPacket; +} + +# (hvx,1) vsub -- "Vdd.b=vsub(Vuu.b,Vvv.b):sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 1 0 1 v v v v v P P 0 u u u u u 0 0 1 d d d d d + +define pcodeop vsub_WbWb_sat; + +:vsub^":sat" VddB_0004,VuuB_0812,VvvB_1620 EndPacket is iclass=0x1 & op2127=0x75 & op13=0x0 & op0507=0x1 & VddB_0004 & VuuB_0812 & VvvB_1620 & $(END_PACKET) { + VddB_0004 = vsub_WbWb_sat(VuuB_0812,VvvB_1620); + build EndPacket; +} + +# (hvx,1) vadd -- "Vdd.uw=vadd(Vuu.uw,Vvv.uw):sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 1 0 1 v v v v v P P 0 u u u u u 0 1 0 d d d d d + +define pcodeop vadd_WuwWuw_sat; + +:vadd^":sat" VddUW_0004,VuuUW_0812,VvvUW_1620 EndPacket is iclass=0x1 & op2127=0x75 & op13=0x0 & op0507=0x2 & VddUW_0004 & VuuUW_0812 & VvvUW_1620 & $(END_PACKET) { + VddUW_0004 = vadd_WuwWuw_sat(VuuUW_0812,VvvUW_1620); + build EndPacket; +} + +# (hvx,1) vsub -- "Vdd.uw=vsub(Vuu.uw,Vvv.uw):sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 1 0 1 v v v v v P P 0 u u u u u 0 1 1 d d d d d + +define pcodeop vsub_WuwWuw_sat; + +:vsub^":sat" VddUW_0004,VuuUW_0812,VvvUW_1620 EndPacket is iclass=0x1 & op2127=0x75 & op13=0x0 & op0507=0x3 & VddUW_0004 & VuuUW_0812 & VvvUW_1620 & $(END_PACKET) { + VddUW_0004 = vsub_WuwWuw_sat(VuuUW_0812,VvvUW_1620); + build EndPacket; +} + +# (hvx,1) not -- "Qd4=not(Qs4)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 - - 0 - - - 1 1 P P 0 - - - s s 0 0 0 0 1 0 d d + +:not Qd2,qv0809 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op1617=0x3 & op13=0x0 & op0207=0x2 & Qd2 & qv0809 & $(END_PACKET) { + Qd2 = ~qv0809; + build EndPacket; +} + +# (hvx,1) vand -- "Vd=vand(Qv4,Vu)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 v v 0 - - 0 1 1 P P 1 u u u u u 0 0 0 d d d d d + +define pcodeop vand_QV; + +:vand Vd5,qv2223,Vu_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x0 & op1617=0x3 & op13=0x1 & op0507=0x0 & Vd5 & qv2223 & Vu_0812 & $(END_PACKET) { + Vd5 = vand_QV(qv2223,Vu_0812); + build EndPacket; +} + +# (hvx,1) vand -- "Vd=vand(!Qv4,Vu)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 v v 0 - - 0 1 1 P P 1 u u u u u 0 0 1 d d d d d + +:vand Vd5,qv2223,Vu_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x0 & op1617=0x3 & op13=0x1 & op0507=0x1 & Vd5 & qv2223 & Vu_0812 & $(END_PACKET) { + Vd5 = vand_QV(~qv2223,Vu_0812); + build EndPacket; +} + +# (hvx,1) vmin -- "Vd.ub=vmin(Vu.ub,Vv.ub)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 0 0 0 v v v v v P P 0 u u u u u 0 0 1 d d d d d + +define pcodeop vmin_VubVub; + +:vmin VdUB_0004,VuUB_0812,VvUB_1620 EndPacket is iclass=0x1 & op2127=0x78 & op13=0x0 & op0507=0x1 & VdUB_0004 & VuUB_0812 & VvUB_1620 & $(END_PACKET) { + VdUB_0004 = vmin_VubVub(VuUB_0812,VvUB_1620); + build EndPacket; +} + +# (hvx,1) vmin -- "Vd.uh=vmin(Vu.uh,Vv.uh)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 0 0 0 v v v v v P P 0 u u u u u 0 1 0 d d d d d + +define pcodeop vmin_VuhVuh; + +:vmin VdUH_0004,VuUH_0812,VvUH_1620 EndPacket is iclass=0x1 & op2127=0x78 & op13=0x0 & op0507=0x2 & VdUH_0004 & VuUH_0812 & VvUH_1620 & $(END_PACKET) { + VdUH_0004 = vmin_VuhVuh(VuUH_0812,VvUH_1620); + build EndPacket; +} + +# (hvx,1) vmin -- "Vd.h=vmin(Vu.h,Vv.h)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 0 0 0 v v v v v P P 0 u u u u u 0 1 1 d d d d d + +define pcodeop vmin_VhVh; + +:vmin VdH_0004,VuH_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x78 & op13=0x0 & op0507=0x3 & VdH_0004 & VuH_0812 & VvH_1620 & $(END_PACKET) { + VdH_0004 = vmin_VhVh(VuH_0812,VvH_1620); + build EndPacket; +} + +# (hvx,1) vmin -- "Vd.w=vmin(Vu.w,Vv.w)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 0 0 0 v v v v v P P 0 u u u u u 1 0 0 d d d d d + +define pcodeop vmin_VwVw; + +:vmin VdW_0004,VuW_0812,VvW_1620 EndPacket is iclass=0x1 & op2127=0x78 & op13=0x0 & op0507=0x4 & VdW_0004 & VuW_0812 & VvW_1620 & $(END_PACKET) { + VdW_0004 = vmin_VwVw(VuW_0812,VvW_1620); + build EndPacket; +} + +# (hvx,1) vmax -- "Vd.ub=vmax(Vu.ub,Vv.ub)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 0 0 0 v v v v v P P 0 u u u u u 1 0 1 d d d d d + +define pcodeop vmax_VubVub; + +:vmax VdUB_0004,VuUB_0812,VvUB_1620 EndPacket is iclass=0x1 & op2127=0x78 & op13=0x0 & op0507=0x5 & VdUB_0004 & VuUB_0812 & VvUB_1620 & $(END_PACKET) { + VdUB_0004 = vmax_VubVub(VuUB_0812,VvUB_1620); + build EndPacket; +} + +# (hvx,1) vmax -- "Vd.uh=vmax(Vu.uh,Vv.uh)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 0 0 0 v v v v v P P 0 u u u u u 1 1 0 d d d d d + +define pcodeop vmax_VuhVuh; + +:vmax VdUH_0004,VuUH_0812,VvUH_1620 EndPacket is iclass=0x1 & op2127=0x78 & op13=0x0 & op0507=0x6 & VdUH_0004 & VuUH_0812 & VvUH_1620 & $(END_PACKET) { + VdUH_0004 = vmax_VuhVuh(VuUH_0812,VvUH_1620); + build EndPacket; +} + +# (hvx,1) vmax -- "Vd.h=vmax(Vu.h,Vv.h)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 0 0 0 v v v v v P P 0 u u u u u 1 1 1 d d d d d + +define pcodeop vmax_VhVh; + +:vmax VdH_0004,VuH_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x78 & op13=0x0 & op0507=0x7 & VdH_0004 & VuH_0812 & VvH_1620 & $(END_PACKET) { + VdH_0004 = vmax_VhVh(VuH_0812,VvH_1620); + build EndPacket; +} + +# (hvx,1) vmax -- "Vd.w=vmax(Vu.w,Vv.w)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 0 0 1 v v v v v P P 0 u u u u u 0 0 0 d d d d d + +define pcodeop vmax_VwVw; + +:vmax VdW_0004,VuW_0812,VvW_1620 EndPacket is iclass=0x1 & op2127=0x79 & op13=0x0 & op0507=0x0 & VdW_0004 & VuW_0812 & VvW_1620 & $(END_PACKET) { + VdW_0004 = vmax_VwVw(VuW_0812,VvW_1620); + build EndPacket; +} + +# (hvx,1) vmin -- "Vd.b=vmin(Vu.b,Vv.b)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 0 0 1 v v v v v P P 0 u u u u u 1 0 0 d d d d d + +define pcodeop vmin_VbVb; + +:vmin VdB_0004,VuB_0812,VvB_1620 EndPacket is iclass=0x1 & op2127=0x79 & op13=0x0 & op0507=0x4 & VdB_0004 & VuB_0812 & VvB_1620 & $(END_PACKET) { + VdB_0004 = vmin_VbVb(VuB_0812,VvB_1620); + build EndPacket; +} + +# (hvx,1) vmax -- "Vd.b=vmax(Vu.b,Vv.b)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 0 0 1 v v v v v P P 0 u u u u u 1 0 1 d d d d d + +define pcodeop vmax_VbVb; + +:vmax VdB_0004,VuB_0812,VvB_1620 EndPacket is iclass=0x1 & op2127=0x79 & op13=0x0 & op0507=0x5 & VdB_0004 & VuB_0812 & VvB_1620 & $(END_PACKET) { + VdB_0004 = vmax_VbVb(VuB_0812,VvB_1620); + build EndPacket; +} + +# (hvx,1) vmax -- "Vd.sf=vmax(Vu.sf,Vv.sf)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 1 1 0 v v v v v P P 1 u u u u u 0 0 1 d d d d d + +define pcodeop vmax_VsfVsf; + +:vmax VdSF_0004,VuSF_0812,VvSF_1620 EndPacket is iclass=0x1 & op2127=0x7e & op13=0x1 & op0507=0x1 & VdSF_0004 & VuSF_0812 & VvSF_1620 & $(END_PACKET) { + VdSF_0004 = vmax_VsfVsf(VuSF_0812,VvSF_1620); + build EndPacket; +} + +# (hvx,1) vmin -- "Vd.sf=vmin(Vu.sf,Vv.sf)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 1 1 0 v v v v v P P 1 u u u u u 0 1 0 d d d d d + +define pcodeop vmin_VsfVsf; + +:vmin VdSF_0004,VuSF_0812,VvSF_1620 EndPacket is iclass=0x1 & op2127=0x7e & op13=0x1 & op0507=0x2 & VdSF_0004 & VuSF_0812 & VvSF_1620 & $(END_PACKET) { + VdSF_0004 = vmin_VsfVsf(VuSF_0812,VvSF_1620); + build EndPacket; +} + +# (hvx,1) vmax -- "Vd.hf=vmax(Vu.hf,Vv.hf)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 1 1 0 v v v v v P P 1 u u u u u 0 1 1 d d d d d + +define pcodeop vmax_VhfVhf; + +:vmax VdHF_0004,VuHF_0812,VvHF_1620 EndPacket is iclass=0x1 & op2127=0x7e & op13=0x1 & op0507=0x3 & VdHF_0004 & VuHF_0812 & VvHF_1620 & $(END_PACKET) { + VdHF_0004 = vmax_VhfVhf(VuHF_0812,VvHF_1620); + build EndPacket; +} + +# (hvx,1) vmin -- "Vd.hf=vmin(Vu.hf,Vv.hf)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 1 1 0 v v v v v P P 1 u u u u u 1 0 0 d d d d d + +define pcodeop vmin_VhfVhf; + +:vmin VdHF_0004,VuHF_0812,VvHF_1620 EndPacket is iclass=0x1 & op2127=0x7e & op13=0x1 & op0507=0x4 & VdHF_0004 & VuHF_0812 & VvHF_1620 & $(END_PACKET) { + VdHF_0004 = vmin_VhfVhf(VuHF_0812,VvHF_1620); + build EndPacket; +} + +# (hvx,1) vabs -- "Vd.h=vabs(Vu.h)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 - - 0 - - - 0 0 P P 0 u u u u u 0 0 0 d d d d d + +define pcodeop vabs_Vh; + +:vabs VdH_0004,VuH_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op1617=0x0 & op13=0x0 & op0507=0x0 & VdH_0004 & VuH_0812 & $(END_PACKET) { + VdH_0004 = vabs_Vh(VuH_0812); + build EndPacket; +} + +# (hvx,1) vabs -- "Vd.h=vabs(Vu.h):sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 - - 0 - - - 0 0 P P 0 u u u u u 0 0 1 d d d d d + +define pcodeop vabs_Vh_sat; + +:vabs^":sat" VdH_0004,VuH_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op1617=0x0 & op13=0x0 & op0507=0x1 & VdH_0004 & VuH_0812 & $(END_PACKET) { + VdH_0004 = vabs_Vh_sat(VuH_0812); + build EndPacket; +} + +# (hvx,1) vabs -- "Vd.w=vabs(Vu.w)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 - - 0 - - - 0 0 P P 0 u u u u u 0 1 0 d d d d d + +define pcodeop vabs_Vw; + +:vabs VdW_0004,VuW_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op1617=0x0 & op13=0x0 & op0507=0x2 & VdW_0004 & VuW_0812 & $(END_PACKET) { + VdW_0004 = vabs_Vw(VuW_0812); + build EndPacket; +} + +# (hvx,1) vabs -- "Vd.w=vabs(Vu.w):sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 - - 0 - - - 0 0 P P 0 u u u u u 0 1 1 d d d d d + +define pcodeop vabs_Vw_sat; + +:vabs^":sat" VdW_0004,VuW_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op1617=0x0 & op13=0x0 & op0507=0x3 & VdW_0004 & VuW_0812 & $(END_PACKET) { + VdW_0004 = vabs_Vw_sat(VuW_0812); + build EndPacket; +} + +# (hvx,1) vabs -- "Vd.b=vabs(Vu.b)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 - - 0 - - - 0 1 P P 0 u u u u u 1 0 0 d d d d d + +define pcodeop vabs_Vb; + +:vabs VdB_0004,VuB_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op1617=0x1 & op13=0x0 & op0507=0x4 & VdB_0004 & VuB_0812 & $(END_PACKET) { + VdB_0004 = vabs_Vb(VuB_0812); + build EndPacket; +} + +# (hvx,1) vabs -- "Vd.b=vabs(Vu.b):sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 - - 0 - - - 0 1 P P 0 u u u u u 1 0 1 d d d d d + +define pcodeop vabs_Vb_sat; + +:vabs^":sat" VdB_0004,VuB_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op1617=0x1 & op13=0x0 & op0507=0x5 & VdB_0004 & VuB_0812 & $(END_PACKET) { + VdB_0004 = vabs_Vb_sat(VuB_0812); + build EndPacket; +} + +# (hvx,1) vadd -- "Vd.w=vadd(Vu.w,Vv.w)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 0 1 0 v v v v v P P 0 u u u u u 0 0 0 d d d d d + +define pcodeop vadd_VwVw; + +:vadd VdW_0004,VuW_0812,VvW_1620 EndPacket is iclass=0x1 & op2127=0x62 & op13=0x0 & op0507=0x0 & VdW_0004 & VuW_0812 & VvW_1620 & $(END_PACKET) { + VdW_0004 = vadd_VwVw(VuW_0812,VvW_1620); + build EndPacket; +} + +# (hvx,1) vadd -- "Vd.ub=vadd(Vu.ub,Vv.ub):sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 0 1 0 v v v v v P P 0 u u u u u 0 0 1 d d d d d + +define pcodeop vadd_VubVub_sat; + +:vadd^":sat" VdUB_0004,VuUB_0812,VvUB_1620 EndPacket is iclass=0x1 & op2127=0x62 & op13=0x0 & op0507=0x1 & VdUB_0004 & VuUB_0812 & VvUB_1620 & $(END_PACKET) { + VdUB_0004 = vadd_VubVub_sat(VuUB_0812,VvUB_1620); + build EndPacket; +} + +# (hvx,1) vadd -- "Vd.uh=vadd(Vu.uh,Vv.uh):sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 0 1 0 v v v v v P P 0 u u u u u 0 1 0 d d d d d + +define pcodeop vadd_VuhVuh_sat; + +:vadd^":sat" VdUH_0004,VuUH_0812,VvUH_1620 EndPacket is iclass=0x1 & op2127=0x62 & op13=0x0 & op0507=0x2 & VdUH_0004 & VuUH_0812 & VvUH_1620 & $(END_PACKET) { + VdUH_0004 = vadd_VuhVuh_sat(VuUH_0812,VvUH_1620); + build EndPacket; +} + +# (hvx,1) vadd -- "Vd.h=vadd(Vu.h,Vv.h):sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 0 1 0 v v v v v P P 0 u u u u u 0 1 1 d d d d d + +define pcodeop vadd_VhVh_sat; + +:vadd^":sat" VdH_0004,VuH_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x62 & op13=0x0 & op0507=0x3 & VdH_0004 & VuH_0812 & VvH_1620 & $(END_PACKET) { + VdH_0004 = vadd_VhVh_sat(VuH_0812,VvH_1620); + build EndPacket; +} + +# (hvx,1) vadd -- "Vd.w=vadd(Vu.w,Vv.w):sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 0 1 0 v v v v v P P 0 u u u u u 1 0 0 d d d d d + +define pcodeop vadd_VwVw_sat; + +:vadd^":sat" VdW_0004,VuW_0812,VvW_1620 EndPacket is iclass=0x1 & op2127=0x62 & op13=0x0 & op0507=0x4 & VdW_0004 & VuW_0812 & VvW_1620 & $(END_PACKET) { + VdW_0004 = vadd_VwVw_sat(VuW_0812,VvW_1620); + build EndPacket; +} + +# (hvx,1) vsub -- "Vd.b=vsub(Vu.b,Vv.b)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 0 1 0 v v v v v P P 0 u u u u u 1 0 1 d d d d d + +define pcodeop vsub_VbVb; + +:vsub VdB_0004,VuB_0812,VvB_1620 EndPacket is iclass=0x1 & op2127=0x62 & op13=0x0 & op0507=0x5 & VdB_0004 & VuB_0812 & VvB_1620 & $(END_PACKET) { + VdB_0004 = vsub_VbVb(VuB_0812,VvB_1620); + build EndPacket; +} + +# (hvx,1) vsub -- "Vd.h=vsub(Vu.h,Vv.h)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 0 1 0 v v v v v P P 0 u u u u u 1 1 0 d d d d d + +define pcodeop vsub_VhVh; + +:vsub VdH_0004,VuH_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x62 & op13=0x0 & op0507=0x6 & VdH_0004 & VuH_0812 & VvH_1620 & $(END_PACKET) { + VdH_0004 = vsub_VhVh(VuH_0812,VvH_1620); + build EndPacket; +} + +# (hvx,1) vsub -- "Vd.w=vsub(Vu.w,Vv.w)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 0 1 0 v v v v v P P 0 u u u u u 1 1 1 d d d d d + +define pcodeop vsub_VwVw; + +:vsub VdW_0004,VuW_0812,VvW_1620 EndPacket is iclass=0x1 & op2127=0x62 & op13=0x0 & op0507=0x7 & VdW_0004 & VuW_0812 & VvW_1620 & $(END_PACKET) { + VdW_0004 = vsub_VwVw(VuW_0812,VvW_1620); + build EndPacket; +} + +# (hvx,1) vsub -- "Vd.ub=vsub(Vu.ub,Vv.ub):sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 0 1 1 v v v v v P P 0 u u u u u 0 0 0 d d d d d + +define pcodeop vsub_VubVub_sat; + +:vsub^":sat" VdUB_0004,VuUB_0812,VvUB_1620 EndPacket is iclass=0x1 & op2127=0x63 & op13=0x0 & op0507=0x0 & VdUB_0004 & VuUB_0812 & VvUB_1620 & $(END_PACKET) { + VdUB_0004 = vsub_VubVub_sat(VuUB_0812,VvUB_1620); + build EndPacket; +} + +# (hvx,1) vsub -- "Vd.uh=vsub(Vu.uh,Vv.uh):sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 0 1 1 v v v v v P P 0 u u u u u 0 0 1 d d d d d + +define pcodeop vsub_VuhVuh_sat; + +:vsub^":sat" VdUH_0004,VuUH_0812,VvUH_1620 EndPacket is iclass=0x1 & op2127=0x63 & op13=0x0 & op0507=0x1 & VdUH_0004 & VuUH_0812 & VvUH_1620 & $(END_PACKET) { + VdUH_0004 = vsub_VuhVuh_sat(VuUH_0812,VvUH_1620); + build EndPacket; +} + +# (hvx,1) vsub -- "Vd.h=vsub(Vu.h,Vv.h):sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 0 1 1 v v v v v P P 0 u u u u u 0 1 0 d d d d d + +define pcodeop vsub_VhVh_sat; + +:vsub^":sat" VdH_0004,VuH_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x63 & op13=0x0 & op0507=0x2 & VdH_0004 & VuH_0812 & VvH_1620 & $(END_PACKET) { + VdH_0004 = vsub_VhVh_sat(VuH_0812,VvH_1620); + build EndPacket; +} + +# (hvx,1) vsub -- "Vd.w=vsub(Vu.w,Vv.w):sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 0 1 1 v v v v v P P 0 u u u u u 0 1 1 d d d d d + +define pcodeop vsub_VwVw_sat; + +:vsub^":sat" VdW_0004,VuW_0812,VvW_1620 EndPacket is iclass=0x1 & op2127=0x63 & op13=0x0 & op0507=0x3 & VdW_0004 & VuW_0812 & VvW_1620 & $(END_PACKET) { + VdW_0004 = vsub_VwVw_sat(VuW_0812,VvW_1620); + build EndPacket; +} + +# (hvx,1) vadd -- "Vd.ub=vadd(Vu.ub,Vv.b):sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 1 0 1 v v v v v P P 0 u u u u u 1 0 0 d d d d d + +define pcodeop vadd_VubVb_sat; + +:vadd^":sat" VdUB_0004,VuUB_0812,VvB_1620 EndPacket is iclass=0x1 & op2127=0x75 & op13=0x0 & op0507=0x4 & VdUB_0004 & VuUB_0812 & VvB_1620 & $(END_PACKET) { + VdUB_0004 = vadd_VubVb_sat(VuUB_0812,VvB_1620); + build EndPacket; +} + +# (hvx,1) vsub -- "Vd.ub=vsub(Vu.ub,Vv.b):sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 1 0 1 v v v v v P P 0 u u u u u 1 0 1 d d d d d + +define pcodeop vsub_VubVb_sat; + +:vsub^":sat" VdUB_0004,VuUB_0812,VvB_1620 EndPacket is iclass=0x1 & op2127=0x75 & op13=0x0 & op0507=0x5 & VdUB_0004 & VuUB_0812 & VvB_1620 & $(END_PACKET) { + VdUB_0004 = vsub_VubVb_sat(VuUB_0812,VvB_1620); + build EndPacket; +} + +# (hvx,1) vadd -- "Vd.b=vadd(Vu.b,Vv.b):sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 0 0 0 v v v v v P P 0 u u u u u 0 0 0 d d d d d + +define pcodeop vadd_VbVb_sat; + +:vadd^":sat" VdB_0004,VuB_0812,VvB_1620 EndPacket is iclass=0x1 & op2127=0x78 & op13=0x0 & op0507=0x0 & VdB_0004 & VuB_0812 & VvB_1620 & $(END_PACKET) { + VdB_0004 = vadd_VbVb_sat(VuB_0812,VvB_1620); + build EndPacket; +} + +# (hvx,1) vsub -- "Vd.b=vsub(Vu.b,Vv.b):sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 0 0 1 v v v v v P P 0 u u u u u 0 1 0 d d d d d + +define pcodeop vsub_VbVb_sat; + +:vsub^":sat" VdB_0004,VuB_0812,VvB_1620 EndPacket is iclass=0x1 & op2127=0x79 & op13=0x0 & op0507=0x2 & VdB_0004 & VuB_0812 & VvB_1620 & $(END_PACKET) { + VdB_0004 = vsub_VbVb_sat(VuB_0812,VvB_1620); + build EndPacket; +} + +# (hvx,1) vadd -- "Vd.uw=vadd(Vu.uw,Vv.uw):sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 0 1 1 v v v v v P P 0 u u u u u 0 0 1 d d d d d + +define pcodeop vadd_VuwVuw_sat; + +:vadd^":sat" VdUW_0004,VuUW_0812,VvUW_1620 EndPacket is iclass=0x1 & op2127=0x7b & op13=0x0 & op0507=0x1 & VdUW_0004 & VuUW_0812 & VvUW_1620 & $(END_PACKET) { + VdUW_0004 = vadd_VuwVuw_sat(VuUW_0812,VvUW_1620); + build EndPacket; +} + +# (hvx,1) vadd -- "Vd.b=vadd(Vu.b,Vv.b)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 1 0 1 v v v v v P P 0 u u u u u 1 1 0 d d d d d + +define pcodeop vadd_VbVb; + +:vadd VdB_0004,VuB_0812,VvB_1620 EndPacket is iclass=0x1 & op2127=0x7d & op13=0x0 & op0507=0x6 & VdB_0004 & VuB_0812 & VvB_1620 & $(END_PACKET) { + VdB_0004 = vadd_VbVb(VuB_0812,VvB_1620); + build EndPacket; +} + +# (hvx,1) vadd -- "Vd.h=vadd(Vu.h,Vv.h)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 1 0 1 v v v v v P P 0 u u u u u 1 1 1 d d d d d + +define pcodeop vadd_VhVh; + +:vadd VdH_0004,VuH_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x7d & op13=0x0 & op0507=0x7 & VdH_0004 & VuH_0812 & VvH_1620 & $(END_PACKET) { + VdH_0004 = vadd_VhVh(VuH_0812,VvH_1620); + build EndPacket; +} + +# (hvx,1) vsub -- "Vd.uw=vsub(Vu.uw,Vv.uw):sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 1 1 0 v v v v v P P 0 u u u u u 1 0 0 d d d d d + +define pcodeop vsub_VuwVuw_sat; + +:vsub^":sat" VdUW_0004,VuUW_0812,VvUW_1620 EndPacket is iclass=0x1 & op2127=0x7e & op13=0x0 & op0507=0x4 & VdUW_0004 & VuUW_0812 & VvUW_1620 & $(END_PACKET) { + VdUW_0004 = vsub_VuwVuw_sat(VuUW_0812,VvUW_1620); + build EndPacket; +} + +# (hvx,1) vadd -- "Vd.w=vadd(Vu.w,Vv.w,Qx4):carry" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 0 1 v v v v v P P 1 u u u u u 0 x x d d d d d + +define pcodeop vsub_VwVwQ_carry; + +:vadd^":carry" VdW_0004,VuW_0812,VvW_1620,qv0506 EndPacket is iclass=0x1 & op2127=0x65 & op13=0x1 & op7=0x0 & VdW_0004 & VuW_0812 & VvW_1620 & qv0506 & $(END_PACKET) { + VdW_0004 = vsub_VwVwQ_carry(VuW_0812,VvW_1620,qv0506); + build EndPacket; +} + +# (hvx,1) vsub -- "Vd.w=vsub(Vu.w,Vv.w,Qx4):carry" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 0 1 v v v v v P P 1 u u u u u 1 x x d d d d d + +define pcodeop vsub_VwVwQ_carry_sat; + +:vsub^":carry" VdW_0004,VuW_0812,VvW_1620,qv0506 EndPacket is iclass=0x1 & op2127=0x65 & op13=0x1 & op7=0x1 & VdW_0004 & VuW_0812 & VvW_1620 & qv0506 & $(END_PACKET) { + VdW_0004 = vsub_VwVwQ_carry_sat(VuW_0812,VvW_1620,qv0506); + build EndPacket; +} + +# (hvx,1) vadd -- "Vd.w=vadd(Vu.w,Vv.w,Qs4):carry:sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 1 1 0 0 v v v v v P P 1 u u u u u 0 s s d d d d d + +define pcodeop vadd_VwVwQ_carry_sat; + +:vadd^":carry:sat" VdW_0004,VuW_0812,VvW_1620,qv0506 EndPacket is iclass=0x1 & op2127=0x6c & op13=0x1 & op7=0x0 & VdW_0004 & VuW_0812 & VvW_1620 & qv0506 & $(END_PACKET) { + VdW_0004 = vadd_VwVwQ_carry_sat(VuW_0812,VvW_1620,qv0506); + build EndPacket; +} + +# (hvx,1) vadd -- "Vd.w,Qe4=vadd(Vu.w,Vv.w):carry" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 1 1 0 1 v v v v v P P 1 u u u u u 0 e e d d d d d + +define pcodeop vadd_VwVw_carryResult; + +:vadd^":carry" VdW_0004,qv0506,VuW_0812,VvW_1620 EndPacket is iclass=0x1 & op2127=0x6d & op13=0x1 & op7=0x0 & VdW_0004 & qv0506 & VuW_0812 & VvW_1620 & $(END_PACKET) { + tmpQ:$(HVX_PREDICATE_SIZE) = vadd_VwVw_carryResult(VuW_0812,VvW_1620); + VdW_0004 = vadd_VwVw(VuW_0812,VvW_1620); + build EndPacket; + <> + qv0506 = tmpQ; +} + +# (hvx,1) vsub -- "Vd.w,Qe4=vsub(Vu.w,Vv.w):carry" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 1 1 0 1 v v v v v P P 1 u u u u u 1 e e d d d d d + +define pcodeop vsub_VwVw_carryResult; + +:vsub^":carry" VdW_0004,qv0506,VuW_0812,VvW_1620 EndPacket is iclass=0x1 & op2127=0x6d & op13=0x1 & op7=0x1 & VdW_0004 & qv0506 & VuW_0812 & VvW_1620 & $(END_PACKET) { + tmpQ:$(HVX_PREDICATE_SIZE) = vsub_VwVw_carryResult(VuW_0812,VvW_1620); + VdW_0004 = vsub_VwVw(VuW_0812,VvW_1620); + build EndPacket; + <> + qv0506 = tmpQ; +} + +# (hvx,1) vand -- "Vd=vand(Vu,Vv)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 0 0 1 v v v v v P P 0 u u u u u 1 0 1 d d d d d + +:vand Vd5,Vu_0812,Vv_1620 EndPacket is iclass=0x1 & op2127=0x61 & op13=0x0 & op0507=0x5 & Vd5 & Vu_0812 & Vv_1620 & $(END_PACKET) { + Vd5 = Vu_0812 & Vv_1620; + build EndPacket; +} + +# (hvx,1) vor -- "Vd=vor(Vu,Vv)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 0 0 1 v v v v v P P 0 u u u u u 1 1 0 d d d d d + +:vor Vd5,Vu_0812,Vv_1620 EndPacket is iclass=0x1 & op2127=0x61 & op13=0x0 & op0507=0x6 & Vd5 & Vu_0812 & Vv_1620 & $(END_PACKET) { + Vd5 = Vu_0812 | Vv_1620; + build EndPacket; +} + +# (hvx,1) vxor -- "Vd=vxor(Vu,Vv)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 0 0 1 v v v v v P P 0 u u u u u 1 1 1 d d d d d + +:vxor Vd5,Vu_0812,Vv_1620 EndPacket is iclass=0x1 & op2127=0x61 & op13=0x0 & op0507=0x7 & Vd5 & Vu_0812 & Vv_1620 & $(END_PACKET) { + Vd5 = Vu_0812 ^ Vv_1620; + build EndPacket; +} + +# (hvx,1) vnot -- "Vd=vnot(Vu)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 - - 0 - - - 0 0 P P 0 u u u u u 1 0 0 d d d d d + +:vnot Vd5,Vu_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op1617=0x0 & op13=0x0 & op0507=0x4 & Vd5 & Vu_0812 & $(END_PACKET) { + Vd5 = ~Vu_0812; + build EndPacket; +} + +# (hvx,1) "if (Ps) Vd=Vu" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 1 0 0 0 0 - - - - - P P - u u u u u - s s d d d d d +# +# (hvx,1) "if (!Ps) Vd=Vu" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 1 0 0 0 1 - - - - - P P - u u u u u - s s d d d d d + +:assign^VPuCond0506_S21 vd5,Vu_0812 EndPacket is iclass=0x1 & op2227=0x28 & VPuCond0506_S21 & vd5 & vd5_ & SetVNRegVd5 & Vu_0812 & $(END_PACKET) [ cond=1; ] { + build VPuCond0506_S21; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + vd5_ = Vu_0812; + + <> + if (ConditionReg == 0) goto ; + vd5 = vd5_; + +} + +# (hvx,1) "Vd=Vu" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 - - 0 - - 0 1 1 P P 1 u u u u u 1 1 1 d d d d d + +:assign Vd5,Vu_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x0 & op1617=0x3 & op13=0x1 & op0507=0x7 & Vd5 & Vu_0812 & $(END_PACKET) [ cond=0; ] { + Vd5 = Vu_0812; # Vd5 handles unconditional commit + build EndPacket; +} + +# (hvx,1) "Vd.tmp=Vu" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 - - 0 - - - 0 1 P P 0 u u u u u 1 1 0 d d d d d + +:assign Vd5tmp,Vu_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op1617=0x1 & op13=0x0 & op0507=0x6 & Vd5tmp & Vu_0812 & $(END_PACKET) { + Vd5tmp = Vu_0812; + build EndPacket; +} + +# (hvx,1) vcombine -- "Vdd.tmp=vcombine(Vu,Vv)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 1 0 1 v v v v v P P 0 u u u u u 1 1 1 d d d d d + +:vcombine Vdd5tmp,Vu_0812,Vv_1620 EndPacket is iclass=0x1 & op2127=0x75 & op13=0x0 & op0507=0x7 & Vdd5tmp & Vu_0812 & Vv_1620 & $(END_PACKET) { + Vdd5tmp = vcombine(Vu_0812,Vv_1620); + build EndPacket; +} + +# (hvx,1) vavg -- "Vd.ub=vavg(Vu.ub,Vv.ub)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 1 0 v v v v v P P 0 u u u u u 1 0 0 d d d d d + +define pcodeop vavg_VubVub; + +:vavg VdUB_0004,VuUB_0812,VvUB_1620 EndPacket is iclass=0x1 & op2127=0x66 & op13=0x0 & op0507=0x4 & VdUB_0004 & VuUB_0812 & VvUB_1620 & $(END_PACKET) { + VdUB_0004 = vavg_VubVub(VuUB_0812,VvUB_1620); + build EndPacket; +} + +# (hvx,1) vavg -- "Vd.uh=vavg(Vu.uh,Vv.uh)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 1 0 v v v v v P P 0 u u u u u 1 0 1 d d d d d + +define pcodeop vavg_VuhVuh; + +:vavg VdUH_0004,VuUH_0812,VvUH_1620 EndPacket is iclass=0x1 & op2127=0x66 & op13=0x0 & op0507=0x5 & VdUH_0004 & VuUH_0812 & VvUH_1620 & $(END_PACKET) { + VdUH_0004 = vavg_VuhVuh(VuUH_0812,VvUH_1620); + build EndPacket; +} + +# (hvx,1) vavg -- "Vd.h=vavg(Vu.h,Vv.h)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 1 0 v v v v v P P 0 u u u u u 1 1 0 d d d d d + +define pcodeop vavg_VhVh; + +:vavg VdH_0004,VuH_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x66 & op13=0x0 & op0507=0x6 & VdH_0004 & VuH_0812 & VvH_1620 & $(END_PACKET) { + VdH_0004 = vavg_VhVh(VuH_0812,VvH_1620); + build EndPacket; +} + +# (hvx,1) vavg -- "Vd.w=vavg(Vu.w,Vv.w)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 1 0 v v v v v P P 0 u u u u u 1 1 1 d d d d d + +define pcodeop vavg_VwVw; + +:vavg VdW_0004,VuW_0812,VvW_1620 EndPacket is iclass=0x1 & op2127=0x66 & op13=0x0 & op0507=0x7 & VdW_0004 & VuW_0812 & VvW_1620 & $(END_PACKET) { + VdW_0004 = vavg_VwVw(VuW_0812,VvW_1620); + build EndPacket; +} + +# (hvx,1) vnavg -- "Vd.b=vnavg(Vu.ub,Vv.ub)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 1 1 v v v v v P P 0 u u u u u 0 0 0 d d d d d + +define pcodeop vnavg_VubVub; + +:vnavg VdB_0004,VuUB_0812,VvUB_1620 EndPacket is iclass=0x1 & op2127=0x67 & op13=0x0 & op0507=0x0 & VdB_0004 & VuUB_0812 & VvUB_1620 & $(END_PACKET) { + VdB_0004 = vnavg_VubVub(VuUB_0812,VvUB_1620); + build EndPacket; +} + +# (hvx,1) vnavg -- "Vd.h=vnavg(Vu.h,Vv.h)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 1 1 v v v v v P P 0 u u u u u 0 0 1 d d d d d + +define pcodeop vnavg_VhVh; + +:vnavg VdH_0004,VuH_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x67 & op13=0x0 & op0507=0x1 & VdH_0004 & VuH_0812 & VvH_1620 & $(END_PACKET) { + VdH_0004 = vnavg_VhVh(VuH_0812,VvH_1620); + build EndPacket; +} + +# (hvx,1) vnavg -- "Vd.w=vnavg(Vu.w,Vv.w)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 1 1 v v v v v P P 0 u u u u u 0 1 0 d d d d d + +define pcodeop vnavg_VwVw; + +:vnavg VdW_0004,VuW_0812,VvW_1620 EndPacket is iclass=0x1 & op2127=0x67 & op13=0x0 & op0507=0x2 & VdW_0004 & VuW_0812 & VvW_1620 & $(END_PACKET) { + VdW_0004 = vnavg_VwVw(VuW_0812,VvW_1620); + build EndPacket; +} + +# (hvx,1) vavg -- "Vd.ub=vavg(Vu.ub,Vv.ub):rnd" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 1 1 v v v v v P P 0 u u u u u 0 1 1 d d d d d + +define pcodeop vavg_VubVub_rnd; + +:vavg^":rnd" VdUB_0004,VuUB_0812,VvUB_1620 EndPacket is iclass=0x1 & op2127=0x67 & op13=0x0 & op0507=0x3 & VdUB_0004 & VuUB_0812 & VvUB_1620 & $(END_PACKET) { + VdUB_0004 = vavg_VubVub_rnd(VuUB_0812,VvUB_1620); + build EndPacket; +} + +# (hvx,1) vavg -- "Vd.uh=vavg(Vu.uh,Vv.uh):rnd" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 1 1 v v v v v P P 0 u u u u u 1 0 0 d d d d d + +define pcodeop vavg_VuhVuh_rnd; + +:vavg^":rnd" VdUH_0004,VuUH_0812,VvUH_1620 EndPacket is iclass=0x1 & op2127=0x67 & op13=0x0 & op0507=0x4 & VdUH_0004 & VuUH_0812 & VvUH_1620 & $(END_PACKET) { + VdUH_0004 = vavg_VuhVuh_rnd(VuUH_0812,VvUH_1620); + build EndPacket; +} + +# (hvx,1) vavg -- "Vd.h=vavg(Vu.h,Vv.h):rnd" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 1 1 v v v v v P P 0 u u u u u 1 0 1 d d d d d + +define pcodeop vavg_VhVh_rnd; + +:vavg^":rnd" VdH_0004,VuH_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x67 & op13=0x0 & op0507=0x5 & VdH_0004 & VuH_0812 & VvH_1620 & $(END_PACKET) { + VdH_0004 = vavg_VhVh_rnd(VuH_0812,VvH_1620); + build EndPacket; +} + +# (hvx,1) vavg -- "Vd.w=vavg(Vu.w,Vv.w):rnd" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 1 1 v v v v v P P 0 u u u u u 1 1 0 d d d d d + +define pcodeop vavg_VwVw_rnd; + +:vavg^":rnd" VdW_0004,VuW_0812,VvW_1620 EndPacket is iclass=0x1 & op2127=0x67 & op13=0x0 & op0507=0x6 & VdW_0004 & VuW_0812 & VvW_1620 & $(END_PACKET) { + VdW_0004 = vavg_VwVw_rnd(VuW_0812,VvW_1620); + build EndPacket; +} + +# (hvx,1) vavg -- "Vd.uw=vavg(Vu.uw,Vv.uw)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 0 0 0 v v v v v P P 1 u u u u u 0 1 0 d d d d d + +define pcodeop vavg_VuwVuw; + +:vavg VdUW_0004,VuUW_0812,VvUW_1620 EndPacket is iclass=0x1 & op2127=0x78 & op13=0x1 & op0507=0x2 & VdUW_0004 & VuUW_0812 & VvUW_1620 & $(END_PACKET) { + VdUW_0004 = vavg_VuwVuw(VuUW_0812,VvUW_1620); + build EndPacket; +} + +# (hvx,1) vavg -- "Vd.uw=vavg(Vu.uw,Vv.uw):rnd" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 0 0 0 v v v v v P P 1 u u u u u 0 1 1 d d d d d + +define pcodeop vavg_VuwVuw_rnd; + +:vavg^":rnd" VdUW_0004,VuUW_0812,VvUW_1620 EndPacket is iclass=0x1 & op2127=0x78 & op13=0x1 & op0507=0x3 & VdUW_0004 & VuUW_0812 & VvUW_1620 & $(END_PACKET) { + VdUW_0004 = vavg_VuwVuw_rnd(VuUW_0812,VvUW_1620); + build EndPacket; +} + +# (hvx,1) vavg -- "Vd.b=vavg(Vu.b,Vv.b)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 0 0 0 v v v v v P P 1 u u u u u 1 0 0 d d d d d + +define pcodeop vavg_VbVb; + +:vavg VdB_0004,VuB_0812,VvB_1620 EndPacket is iclass=0x1 & op2127=0x78 & op13=0x1 & op0507=0x4 & VdB_0004 & VuB_0812 & VvB_1620 & $(END_PACKET) { + VdB_0004 = vavg_VbVb(VuB_0812,VvB_1620); + build EndPacket; +} + +# (hvx,1) vavg -- "Vd.b=vavg(Vu.b,Vv.b):rnd" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 0 0 0 v v v v v P P 1 u u u u u 1 0 1 d d d d d + +define pcodeop vavg_VbVb_rnd; + +:vavg^":rnd" VdB_0004,VuB_0812,VvB_1620 EndPacket is iclass=0x1 & op2127=0x78 & op13=0x1 & op0507=0x5 & VdB_0004 & VuB_0812 & VvB_1620 & $(END_PACKET) { + VdB_0004 = vavg_VbVb_rnd(VuB_0812,VvB_1620); + build EndPacket; +} + +# (hvx,1) vnavg -- "Vd.b=vnavg(Vu.b,Vv.b)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 0 0 0 v v v v v P P 1 u u u u u 1 1 0 d d d d d + +define pcodeop vnavg_VbVb; + +:vnavg VdB_0004,VuB_0812,VvB_1620 EndPacket is iclass=0x1 & op2127=0x78 & op13=0x1 & op0507=0x6 & VdB_0004 & VuB_0812 & VvB_1620 & $(END_PACKET) { + VdB_0004 = vnavg_VbVb(VuB_0812,VvB_1620); + build EndPacket; +} + +# (hvx,1) vcmp.eq -- "Qd4=vcmp.eq(Vu.b,Vv.b)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 1 0 0 v v v v v P P 0 u u u u u 0 0 0 0 0 0 d d + +define pcodeop vcmp_eq_VbVb; + +:vcmp.eq Qd2,VuB_0812,VvB_1620 EndPacket is iclass=0x1 & op2127=0x7c & op13=0x0 & op0207=0x0 & Qd2 & VuB_0812 & VvB_1620 & $(END_PACKET) { + Qd2 = vcmp_eq_VbVb(VuB_0812,VvB_1620); + build EndPacket; +} + +# (hvx,1) vcmp.eq -- "Qd4=vcmp.eq(Vu.h,Vv.h)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 1 0 0 v v v v v P P 0 u u u u u 0 0 0 0 0 1 d d + +define pcodeop vcmp_eq_VhVh; + +:vcmp.eq Qd2,VuH_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x7c & op13=0x0 & op0207=0x1 & Qd2 & VuH_0812 & VvH_1620 & $(END_PACKET) { + Qd2 = vcmp_eq_VhVh(VuH_0812,VvH_1620); + build EndPacket; +} + +# (hvx,1) vcmp.eq -- "Qd4=vcmp.eq(Vu.w,Vv.w)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 1 0 0 v v v v v P P 0 u u u u u 0 0 0 0 1 0 d d + +define pcodeop vcmp_eq_VwVw; + +:vcmp.eq Qd2,VuW_0812,VvW_1620 EndPacket is iclass=0x1 & op2127=0x7c & op13=0x0 & op0207=0x2 & Qd2 & VuW_0812 & VvW_1620 & $(END_PACKET) { + Qd2 = vcmp_eq_VwVw(VuW_0812,VvW_1620); + build EndPacket; +} + +# (hvx,1) vcmp.gt -- "Qd4=vcmp.gt(Vu.b,Vv.b)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 1 0 0 v v v v v P P 0 u u u u u 0 0 0 1 0 0 d d + +define pcodeop vcmp_gt_VbVb; + +:vcmp.gt Qd2,VuB_0812,VvB_1620 EndPacket is iclass=0x1 & op2127=0x7c & op13=0x0 & op0207=0x4 & Qd2 & VuB_0812 & VvB_1620 & $(END_PACKET) { + Qd2 = vcmp_gt_VbVb(VuB_0812,VvB_1620); + build EndPacket; +} + +# (hvx,1) vcmp.gt -- "Qd4=vcmp.gt(Vu.h,Vv.h)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 1 0 0 v v v v v P P 0 u u u u u 0 0 0 1 0 1 d d + +define pcodeop vcmp_gt_VhVh; + +:vcmp.gt Qd2,VuH_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x7c & op13=0x0 & op0207=0x5 & Qd2 & VuH_0812 & VvH_1620 & $(END_PACKET) { + Qd2 = vcmp_gt_VhVh(VuH_0812,VvH_1620); + build EndPacket; +} + +# (hvx,1) vcmp.gt -- "Qd4=vcmp.gt(Vu.w,Vv.w)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 1 0 0 v v v v v P P 0 u u u u u 0 0 0 1 1 0 d d + +define pcodeop vcmp_gt_VwVw; + +:vcmp.gt Qd2,VuW_0812,VvW_1620 EndPacket is iclass=0x1 & op2127=0x7c & op13=0x0 & op0207=0x6 & Qd2 & VuW_0812 & VvW_1620 & $(END_PACKET) { + Qd2 = vcmp_gt_VwVw(VuW_0812,VvW_1620); + build EndPacket; +} + +# (hvx,1) vcmp.gt -- "Qd4=vcmp.gt(Vu.ub,Vv.ub)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 1 0 0 v v v v v P P 0 u u u u u 0 0 1 0 0 0 d d + +define pcodeop vcmp_gt_VubVub; + +:vcmp.gt Qd2,VuUB_0812,VvUB_1620 EndPacket is iclass=0x1 & op2127=0x7c & op13=0x0 & op0207=0x8 & Qd2 & VuUB_0812 & VvUB_1620 & $(END_PACKET) { + Qd2 = vcmp_gt_VubVub(VuUB_0812,VvUB_1620); + build EndPacket; +} + +# (hvx,1) vcmp.gt -- "Qd4=vcmp.gt(Vu.uh,Vv.uh)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 1 0 0 v v v v v P P 0 u u u u u 0 0 1 0 0 1 d d + +define pcodeop vcmp_gt_VuhVuh; + +:vcmp.gt Qd2,VuUH_0812,VvUH_1620 EndPacket is iclass=0x1 & op2127=0x7c & op13=0x0 & op0207=0x9 & Qd2 & VuUH_0812 & VvUH_1620 & $(END_PACKET) { + Qd2 = vcmp_gt_VuhVuh(VuUH_0812,VvUH_1620); + build EndPacket; +} + +# (hvx,1) vcmp.gt -- "Qd4=vcmp.gt(Vu.uw,Vv.uw)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 1 0 0 v v v v v P P 0 u u u u u 0 0 1 0 1 0 d d + +define pcodeop vcmp_gt_VuwVuw; + +:vcmp.gt Qd2,VuUW_0812,VvUW_1620 EndPacket is iclass=0x1 & op2127=0x7c & op13=0x0 & op0207=0xa & Qd2 & VuUW_0812 & VvUW_1620 & $(END_PACKET) { + Qd2 = vcmp_gt_VuwVuw(VuUW_0812,VvUW_1620); + build EndPacket; +} + +# (hvx,1) vcmp.eq -- "Qx4&=vcmp.eq(Vu.b,Vv.b)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 0 0 0 0 0 x x + +define pcodeop vcmp_eqand_QVbVb; + +:vcmp.eq Qd2,VuB_0812,VvB_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x1 & op0207=0x0 & Qd2 & VuB_0812 & VvB_1620 & $(END_PACKET) { + Qd2 = vcmp_eqand_QVbVb(Qd2,VuB_0812,VvB_1620); + build EndPacket; +} + +# (hvx,1) vcmp.eq -- "Qx4&=vcmp.eq(Vu.h,Vv.h)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 0 0 0 0 1 x x + +define pcodeop vcmp_eqand_QVhVh; + +:vcmp.eq Qd2,VuH_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x1 & op0207=0x1 & Qd2 & VuH_0812 & VvH_1620 & $(END_PACKET) { + Qd2 = vcmp_eqand_QVhVh(Qd2,VuH_0812,VvH_1620); + build EndPacket; +} + +# (hvx,1) vcmp.eq -- "Qx4&=vcmp.eq(Vu.w,Vv.w)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 0 0 0 1 0 x x + +define pcodeop vcmp_eqand_QVwVw; + +:vcmp.eq Qd2,VuW_0812,VvW_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x1 & op0207=0x2 & Qd2 & VuW_0812 & VvW_1620 & $(END_PACKET) { + Qd2 = vcmp_eqand_QVwVw(Qd2,VuW_0812,VvW_1620); + build EndPacket; +} + +# (hvx,1) vcmp.gt -- "Qx4&=vcmp.gt(Vu.b,Vv.b)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 0 0 1 0 0 x x + +define pcodeop vcmp_gtand_QVbVb; + +:vcmp.gt Qd2,VuB_0812,VvB_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x1 & op0207=0x4 & Qd2 & VuB_0812 & VvB_1620 & $(END_PACKET) { + Qd2 = vcmp_gtand_QVbVb(Qd2,VuB_0812,VvB_1620); + build EndPacket; +} + +# (hvx,1) vcmp.gt -- "Qx4&=vcmp.gt(Vu.h,Vv.h)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 0 0 1 0 1 x x + +define pcodeop vcmp_gtand_QVhVh; + +:vcmp.gt Qd2,VuH_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x1 & op0207=0x5 & Qd2 & VuH_0812 & VvH_1620 & $(END_PACKET) { + Qd2 = vcmp_gtand_QVhVh(Qd2,VuH_0812,VvH_1620); + build EndPacket; +} + +# (hvx,1) vcmp.gt -- "Qx4&=vcmp.gt(Vu.w,Vv.w)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 0 0 1 1 0 x x + +define pcodeop vcmp_gtand_QVwVw; + +:vcmp.gt Qd2,VuW_0812,VvW_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x1 & op0207=0x6 & Qd2 & VuW_0812 & VvW_1620 & $(END_PACKET) { + Qd2 = vcmp_gtand_QVwVw(Qd2,VuW_0812,VvW_1620); + build EndPacket; +} + +# (hvx,1) vcmp.gt -- "Qx4&=vcmp.gt(Vu.ub,Vv.ub)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 0 1 0 0 0 x x + +define pcodeop vcmp_gtand_QVubVub; + +:vcmp.gt Qd2,VuUB_0812,VvUB_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x1 & op0207=0x8 & Qd2 & VuUB_0812 & VvUB_1620 & $(END_PACKET) { + Qd2 = vcmp_gtand_QVubVub(Qd2,VuUB_0812,VvUB_1620); + build EndPacket; +} + +# (hvx,1) vcmp.gt -- "Qx4&=vcmp.gt(Vu.uh,Vv.uh)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 0 1 0 0 1 x x + +define pcodeop vcmp_gtand_QVuhVuh; + +:vcmp.gt Qd2,VuUH_0812,VvUH_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x1 & op0207=0x9 & Qd2 & VuUH_0812 & VvUH_1620 & $(END_PACKET) { + Qd2 = vcmp_gtand_QVuhVuh(Qd2,VuUH_0812,VvUH_1620); + build EndPacket; +} + +# (hvx,1) vcmp.gt -- "Qx4&=vcmp.gt(Vu.uw,Vv.uw)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 0 1 0 1 0 x x + +define pcodeop vcmp_gtand_QVuwVuw; + +:vcmp.gt Qd2,VuUW_0812,VvUW_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x1 & op0207=0xa & Qd2 & VuUW_0812 & VvUW_1620 & $(END_PACKET) { + Qd2 = vcmp_gtand_QVuwVuw(Qd2,VuUW_0812,VvUW_1620); + build EndPacket; +} + +# (hvx,1) vcmp.gt -- "Qx4|=vcmp.gt(Vu.sf,Vv.sf)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 0 1 1 0 0 x x + +define pcodeop vcmp_gtor_QVsfVsf; + +:vcmp.gt|= Qd2,VuSF_0812,VvSF_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x1 & op0207=0xc & Qd2 & VuSF_0812 & VvSF_1620 & $(END_PACKET) { + Qd2 = vcmp_gtor_QVsfVsf(Qd2,VuSF_0812,VvSF_1620); + build EndPacket; +} + +# (hvx,1) vcmp.gt -- "Qx4|=vcmp.gt(Vu.hf,Vv.hf)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 0 1 1 0 1 x x + +define pcodeop vcmp_gtor_QVhfVhf; + +:vcmp.gt|= Qd2,VuHF_0812,VvHF_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x1 & op0207=0xd & Qd2 & VuHF_0812 & VvHF_1620 & $(END_PACKET) { + Qd2 = vcmp_gtor_QVhfVhf(Qd2,VuHF_0812,VvHF_1620); + build EndPacket; +} + +# (hvx,1) vcmp.eq -- "Qx4|=vcmp.eq(Vu.b,Vv.b)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 1 0 0 0 0 x x + +define pcodeop vcmp_eqor_QVbVb; + +:vcmp.eq|= Qd2,VuB_0812,VvB_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x1 & op0207=0x10 & Qd2 & VuB_0812 & VvB_1620 & $(END_PACKET) { + Qd2 = vcmp_eqor_QVbVb(Qd2,VuB_0812,VvB_1620); + build EndPacket; +} + +# (hvx,1) vcmp.eq -- "Qx4|=vcmp.eq(Vu.h,Vv.h)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 1 0 0 0 1 x x + +define pcodeop vcmp_eqor_QVhVh; + +:vcmp.eq|= Qd2,VuH_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x1 & op0207=0x11 & Qd2 & VuH_0812 & VvH_1620 & $(END_PACKET) { + Qd2 = vcmp_eqor_QVhVh(Qd2,VuH_0812,VvH_1620); + build EndPacket; +} + +# (hvx,1) vcmp.eq -- "Qx4|=vcmp.eq(Vu.w,Vv.w)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 1 0 0 1 0 x x + +define pcodeop vcmp_eqor_QVwVw; + +:vcmp.eq|= Qd2,VuW_0812,VvW_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x1 & op0207=0x12 & Qd2 & VuW_0812 & VvW_1620 & $(END_PACKET) { + Qd2 = vcmp_eqor_QVwVw(Qd2,VuW_0812,VvW_1620); + build EndPacket; +} + +# (hvx,1) vcmp.gt -- "Qx4|=vcmp.gt(Vu.b,Vv.b)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 1 0 1 0 0 x x + +define pcodeop vcmp_gtor_QVbVb; + +:vcmp.gt|= Qd2,VuB_0812,VvB_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x1 & op0207=0x14 & Qd2 & VuB_0812 & VvB_1620 & $(END_PACKET) { + Qd2 = vcmp_gtor_QVbVb(Qd2,VuB_0812,VvB_1620); + build EndPacket; +} + +# (hvx,1) vcmp.gt -- "Qx4|=vcmp.gt(Vu.h,Vv.h)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 1 0 1 0 1 x x + +define pcodeop vcmp_gtor_QVhVh; + +:vcmp.gt|= Qd2,VuH_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x1 & op0207=0x15 & Qd2 & VuH_0812 & VvH_1620 & $(END_PACKET) { + Qd2 = vcmp_gtor_QVhVh(Qd2,VuH_0812,VvH_1620); + build EndPacket; +} + +# (hvx,1) vcmp.gt -- "Qx4|=vcmp.gt(Vu.w,Vv.w)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 1 0 1 1 0 x x + +define pcodeop vcmp_gtor_QVwVw; + +:vcmp.gt|= Qd2,VuW_0812,VvW_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x1 & op0207=0x16 & Qd2 & VuW_0812 & VvW_1620 & $(END_PACKET) { + Qd2 = vcmp_gtor_QVwVw(Qd2,VuW_0812,VvW_1620); + build EndPacket; +} + +# (hvx,1) vcmp.gt -- "Qx4|=vcmp.gt(Vu.ub,Vv.ub)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 1 1 0 0 0 x x + +define pcodeop vcmp_gtor_QVubVub; + +:vcmp.gt|= Qd2,VuUB_0812,VvUB_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x1 & op0207=0x18 & Qd2 & VuUB_0812 & VvUB_1620 & $(END_PACKET) { + Qd2 = vcmp_gtor_QVubVub(Qd2,VuUB_0812,VvUB_1620); + build EndPacket; +} + +# (hvx,1) vcmp.gt -- "Qx4|=vcmp.gt(Vu.uh,Vv.uh)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 1 1 0 0 1 x x + +define pcodeop vcmp_gtor_QVuhVuh; + +:vcmp.gt|= Qd2,VuUH_0812,VvUH_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x1 & op0207=0x19 & Qd2 & VuUH_0812 & VvUH_1620 & $(END_PACKET) { + Qd2 = vcmp_gtor_QVuhVuh(Qd2,VuUH_0812,VvUH_1620); + build EndPacket; +} + +# (hvx,1) vcmp.gt -- "Qx4|=vcmp.gt(Vu.uw,Vv.uw)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 1 1 0 1 0 x x + +define pcodeop vcmp_gtor_QVuwVuw; + +:vcmp.gt|= Qd2,VuUW_0812,VvUW_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x1 & op0207=0x1a & Qd2 & VuUW_0812 & VvUW_1620 & $(END_PACKET) { + Qd2 = vcmp_gtor_QVuwVuw(Qd2,VuUW_0812,VvUW_1620); + build EndPacket; +} + +# (hvx,1) vcmp.gt -- "Qd4=vcmp.gt(Vu.sf,Vv.sf)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 1 1 1 0 0 d d + +define pcodeop vcmp_gt_VsfVsf; + +:vcmp.gt Qd2,VuSF_0812,VvSF_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x1 & op0207=0x1c & Qd2 & VuSF_0812 & VvSF_1620 & $(END_PACKET) { + Qd2 = vcmp_gt_VsfVsf(VuSF_0812,VvSF_1620); + build EndPacket; +} + +# (hvx,1) vcmp.gt -- "Qd4=vcmp.gt(Vu.hf,Vv.hf)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 1 1 1 0 1 d d + +define pcodeop vcmp_gt_VhfVhf; + +:vcmp.gt Qd2,VuHF_0812,VvHF_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x1 & op0207=0x1d & Qd2 & VuHF_0812 & VvHF_1620 & $(END_PACKET) { + Qd2 = vcmp_gt_VhfVhf(VuHF_0812,VvHF_1620); + build EndPacket; +} + +# (hvx,1) vcmp.eq -- "Qx4^=vcmp.eq(Vu.b,Vv.b)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 1 0 0 0 0 0 x x + +define pcodeop vcmp_eqxacc_QVbVb; + +:vcmp.eq^"^=" Qd2,VuB_0812,VvB_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x1 & op0207=0x20 & Qd2 & VuB_0812 & VvB_1620 & $(END_PACKET) { + Qd2 = vcmp_eqxacc_QVbVb(Qd2,VuB_0812,VvB_1620); + build EndPacket; +} + +# (hvx,1) vcmp.eq -- "Qx4^=vcmp.eq(Vu.h,Vv.h)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 1 0 0 0 0 1 x x + +define pcodeop vcmp_eqxacc_QVhVh; + +:vcmp.eq^"^=" Qd2,VuH_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x1 & op0207=0x21 & Qd2 & VuH_0812 & VvH_1620 & $(END_PACKET) { + Qd2 = vcmp_eqxacc_QVhVh(Qd2,VuH_0812,VvH_1620); + build EndPacket; +} + +# (hvx,1) vcmp.eq -- "Qx4^=vcmp.eq(Vu.w,Vv.w)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 1 0 0 0 1 0 x x + +define pcodeop vcmp_eqxacc_QVwVw; + +:vcmp.eq^"^=" Qd2,VuW_0812,VvW_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x1 & op0207=0x22 & Qd2 & VuW_0812 & VvW_1620 & $(END_PACKET) { + Qd2 = vcmp_eqxacc_QVwVw(Qd2,VuW_0812,VvW_1620); + build EndPacket; +} + +# (hvx,1) vcmp.gt -- "Qx4^=vcmp.gt(Vu.b,Vv.b)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 1 0 0 1 0 0 x x + +define pcodeop vcmp_gtxacc_QVbVb; + +:vcmp.gt^"^=" Qd2,VuB_0812,VvB_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x1 & op0207=0x24 & Qd2 & VuB_0812 & VvB_1620 & $(END_PACKET) { + Qd2 = vcmp_gtxacc_QVbVb(Qd2,VuB_0812,VvB_1620); + build EndPacket; +} + +# (hvx,1) vcmp.gt -- "Qx4^=vcmp.gt(Vu.h,Vv.h)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 1 0 0 1 0 1 x x + +define pcodeop vcmp_gtxacc_QVhVh; + +:vcmp.gt^"^=" Qd2,VuH_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x1 & op0207=0x25 & Qd2 & VuH_0812 & VvH_1620 & $(END_PACKET) { + Qd2 = vcmp_gtxacc_QVhVh(Qd2,VuH_0812,VvH_1620); + build EndPacket; +} + +# (hvx,1) vcmp.gt -- "Qx4^=vcmp.gt(Vu.w,Vv.w)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 1 0 0 1 1 0 x x + +define pcodeop vcmp_gtxacc_QVwVw; + +:vcmp.gt^"^=" Qd2,VuW_0812,VvW_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x1 & op0207=0x26 & Qd2 & VuW_0812 & VvW_1620 & $(END_PACKET) { + Qd2 = vcmp_gtxacc_QVwVw(Qd2,VuW_0812,VvW_1620); + build EndPacket; +} + +# (hvx,1) vcmp.gt -- "Qx4^=vcmp.gt(Vu.ub,Vv.ub)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 1 0 1 0 0 0 x x + +define pcodeop vcmp_gtxacc_QVubVub; + +:vcmp.gt^"^=" Qd2,VuUB_0812,VvUB_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x1 & op0207=0x28 & Qd2 & VuUB_0812 & VvUB_1620 & $(END_PACKET) { + Qd2 = vcmp_gtxacc_QVubVub(Qd2,VuUB_0812,VvUB_1620); + build EndPacket; +} + +# (hvx,1) vcmp.gt -- "Qx4^=vcmp.gt(Vu.uh,Vv.uh)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 1 0 1 0 0 1 x x + +define pcodeop vcmp_gtxacc_QVuhVuh; + +:vcmp.gt^"^=" Qd2,VuUH_0812,VvUH_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x1 & op0207=0x29 & Qd2 & VuUH_0812 & VvUH_1620 & $(END_PACKET) { + Qd2 = vcmp_gtxacc_QVuhVuh(Qd2,VuUH_0812,VvUH_1620); + build EndPacket; +} + +# (hvx,1) vcmp.gt -- "Qx4^=vcmp.gt(Vu.uw,Vv.uw)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 1 0 1 0 1 0 x x + +define pcodeop vcmp_gtxacc_QVuwVuw; + +:vcmp.gt^"^=" Qd2,VuUW_0812,VvUW_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x1 & op0207=0x2a & Qd2 & VuUW_0812 & VvUW_1620 & $(END_PACKET) { + Qd2 = vcmp_gtxacc_QVuwVuw(Qd2,VuUW_0812,VvUW_1620); + build EndPacket; +} + +# (hvx,1) vcmp.gt -- "Qx4&=vcmp.gt(Vu.sf,Vv.sf)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 1 1 0 0 1 0 x x + +define pcodeop vcmp_gtand_QVsfVsf; + +:vcmp.gt^"&=" Qd2,VuSF_0812,VvSF_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x1 & op0207=0x32 & Qd2 & VuSF_0812 & VvSF_1620 & $(END_PACKET) { + Qd2 = vcmp_gtand_QVsfVsf(Qd2,VuSF_0812,VvSF_1620); + build EndPacket; +} + +# (hvx,1) vcmp.gt -- "Qx4&=vcmp.gt(Vu.hf,Vv.hf)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 1 1 0 0 1 1 x x + +define pcodeop vcmp_gtand_QVhfVhf; + +:vcmp.gt^"&=" Qd2,VuHF_0812,VvHF_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x1 & op0207=0x33 & Qd2 & VuHF_0812 & VvHF_1620 & $(END_PACKET) { + Qd2 = vcmp_gtand_QVhfVhf(Qd2,VuHF_0812,VvHF_1620); + build EndPacket; +} + +# (hvx,1) vcmp.gt -- "Qx4^=vcmp.gt(Vu.sf,Vv.sf)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 1 1 1 0 1 0 x x + +define pcodeop vcmp_gtxacc_QVsfVsf; + +:vcmp.gt^"^=" Qd2,VuSF_0812,VvSF_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x1 & op0207=0x3a & Qd2 & VuSF_0812 & VvSF_1620 & $(END_PACKET) { + Qd2 = vcmp_gtxacc_QVsfVsf(Qd2,VuSF_0812,VvSF_1620); + build EndPacket; +} + +# (hvx,1) vcmp.gt -- "Qx4^=vcmp.gt(Vu.hf,Vv.hf)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 1 1 1 0 1 1 x x + +define pcodeop vcmp_gtxacc_QVhfVhf; + +:vcmp.gt^"^=" Qd2,VuHF_0812,VvHF_1620 EndPacket is iclass=0x1 & op2127=0x64 & op13=0x1 & op0207=0x3b & Qd2 & VuHF_0812 & VvHF_1620 & $(END_PACKET) { + Qd2 = vcmp_gtxacc_QVhfVhf(Qd2,VuHF_0812,VvHF_1620); + build EndPacket; +} + +# (hvx,1) "if (Qv4) Vx.b+=Vu.b" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 v v 0 - - 0 0 1 P P 1 u u u u u 0 0 0 x x x x x + +define pcodeop condnac_QnVbVb; + +:accum^".if("^qv2223^")+=" VsB_0004,VuB_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x0 & op1617=0x1 & op13=0x1 & op0507=0x0 & qv2223 & Vd5 & VsB_0004 & VuB_0812 & $(END_PACKET) { + Vd5 = condnac_QnVbVb(qv2223,VsB_0004,VuB_0812); + build EndPacket; +} + +# (hvx,1) "if (Qv4) Vx.h+=Vu.h" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 v v 0 - - 0 0 1 P P 1 u u u u u 0 0 1 x x x x x + +define pcodeop condnac_QnVhVh; + +:accum^".if("^qv2223^")+=" VsH_0004,VuH_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x0 & op1617=0x1 & op13=0x1 & op0507=0x1 & qv2223 & Vd5 & VsH_0004 & VuH_0812 & $(END_PACKET) { + Vd5 = condnac_QnVhVh(qv2223,VsH_0004,VuH_0812); + build EndPacket; +} + +# (hvx,1) "if (Qv4) Vx.w+=Vu.w" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 v v 0 - - 0 0 1 P P 1 u u u u u 0 1 0 x x x x x + +define pcodeop condnac_QnVwVw; + +:accum^".if("^qv2223^")+=" VsW_0004,VuW_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x0 & op1617=0x1 & op13=0x1 & op0507=0x2 & qv2223 & Vd5 & VsW_0004 & VuW_0812 & $(END_PACKET) { + Vd5 = condnac_QnVwVw(qv2223,VsW_0004,VuW_0812); + build EndPacket; +} + +# (hvx,1) "if (!Qv4) Vx.b+=Vu.b" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 v v 0 - - 0 0 1 P P 1 u u u u u 0 1 1 x x x x x + +:accum^".if(!"^qv2223^")+=" VsB_0004,VuB_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x0 & op1617=0x1 & op13=0x1 & op0507=0x3 & qv2223 & Vd5 & VsB_0004 & VuB_0812 & $(END_PACKET) { + Vd5 = condnac_QnVbVb(~qv2223,VsB_0004,VuB_0812); + build EndPacket; +} + +# (hvx,1) "if (!Qv4) Vx.h+=Vu.h" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 v v 0 - - 0 0 1 P P 1 u u u u u 1 0 0 x x x x x + +:accum^".if(!"^qv2223^")+=" VsH_0004,VuH_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x0 & op1617=0x1 & op13=0x1 & op0507=0x4 & qv2223 & Vd5 & VsH_0004 & VuH_0812 & $(END_PACKET) { + Vd5 = condnac_QnVhVh(~qv2223,VsH_0004,VuH_0812); + build EndPacket; +} + +# (hvx,1) "if (!Qv4) Vx.w+=Vu.w" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 v v 0 - - 0 0 1 P P 1 u u u u u 1 0 1 x x x x x + +:accum^".if(!"^qv2223^")+=" VsW_0004,VuW_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x0 & op1617=0x1 & op13=0x1 & op0507=0x5 & qv2223 & Vd5 & VsW_0004 & VuW_0812 & $(END_PACKET) { + Vd5 = condnac_QnVwVw(~qv2223,VsW_0004,VuW_0812); + build EndPacket; +} + +# (hvx,1) "if (Qv4) Vx.b-=Vu.b" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 v v 0 - - 0 0 1 P P 1 u u u u u 1 1 0 x x x x x + +define pcodeop condnac_QVbVb; + +:accum^".if("^qv2223^")-=" VsB_0004,VuB_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x0 & op1617=0x1 & op13=0x1 & op0507=0x6 & qv2223 & Vd5 & VsB_0004 & VuB_0812 & $(END_PACKET) { + Vd5 = condnac_QVbVb(qv2223,VsB_0004,VuB_0812); + build EndPacket; +} + +# (hvx,1) "if (!Qv4) Vx.b-=Vu.b" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 v v 0 - - 0 1 0 P P 1 u u u u u 0 0 1 x x x x x + +:accum^".if(!"^qv2223^")-=" VsB_0004,VuB_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x0 & op1617=0x2 & op13=0x1 & op0507=0x1 & qv2223 & Vd5 & VsB_0004 & VuB_0812 & $(END_PACKET) { + Vd5 = condnac_QVbVb(~qv2223,VsB_0004,VuB_0812); + build EndPacket; +} + +# (hvx,1) "if (Qv4) Vx.h-=Vu.h" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 v v 0 - - 0 0 1 P P 1 u u u u u 1 1 1 x x x x x + +define pcodeop condnac_QVhVh; + +:accum^".if("^qv2223^")-=" VsH_0004,VuH_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x0 & op1617=0x1 & op13=0x1 & op0507=0x7 & qv2223 & Vd5 & VsH_0004 & VuH_0812 & $(END_PACKET) { + Vd5 = condnac_QVhVh(qv2223,VsH_0004,VuH_0812); + build EndPacket; +} + +# (hvx,1) "if (!Qv4) Vx.h-=Vu.h" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 v v 0 - - 0 1 0 P P 1 u u u u u 0 1 0 x x x x x + +:accum^".if(!"^qv2223^")-=" VsH_0004,VuH_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x0 & op1617=0x2 & op13=0x1 & op0507=0x2 & qv2223 & Vd5 & VsH_0004 & VuH_0812 & $(END_PACKET) { + Vd5 = condnac_QVhVh(~qv2223,VsH_0004,VuH_0812); + build EndPacket; +} + + +# (hvx,1) "if (Qv4) Vx.w-=Vu.w" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 v v 0 - - 0 1 0 P P 1 u u u u u 0 0 0 x x x x x + +define pcodeop condnac_QVwVw; + +:accum^".if("^qv2223^")-=" VsW_0004,VuW_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x0 & op1617=0x2 & op13=0x1 & op0507=0x0 & qv2223 & Vd5 & VsW_0004 & VuW_0812 & $(END_PACKET) { + Vd5 = condnac_QVwVw(qv2223,VsW_0004,VuW_0812); + build EndPacket; +} + +# (hvx,1) "if (!Qv4) Vx.w-=Vu.w" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 v v 0 - - 0 1 0 P P 1 u u u u u 0 1 1 x x x x x + +:accum^".if(!"^qv2223^")-=" VsW_0004,VuW_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x0 & op1617=0x2 & op13=0x1 & op0507=0x3 & qv2223 & Vd5 & VsW_0004 & VuW_0812 & $(END_PACKET) { + Vd5 = condnac_QVwVw(~qv2223,VsW_0004,VuW_0812); + build EndPacket; +} + +# (hvx,1) vmux -- "Vd=vmux(Qt4,Vu,Vv)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 1 1 1 v v v v v P P 1 u u u u u - t t d d d d d + +define pcodeop vmux_QVV; + +:vmux Vd5,qv0506,Vu_0812,Vv_1620 EndPacket is iclass=0x1 & op2127=0x77 & op13=0x1 & Vd5 & qv0506 & Vu_0812 & Vv_1620 & $(END_PACKET) { + Vd5 = vmux_QVV(qv0506,Vu_0812,Vv_1620); + build EndPacket; +} + +# (hvx,1) vsatdw -- "Vd.w=vsatdw(Vu.w,Vv.w)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 1 1 0 0 v v v v v P P 1 u u u u u 1 1 1 d d d d d + +define pcodeop vsatdw_VwVw; + +:vsatdw VdW_0004,VuW_0812,VvW_1620 EndPacket is iclass=0x1 & op2127=0x6c & op13=0x1 & op0507=0x7 & VdW_0004 & VuW_0812 & VvW_1620 & $(END_PACKET) { + VdW_0004 = vsatdw_VwVw(VuW_0812,VvW_1620); + build EndPacket; +} + +# (hvx,1) vsat -- "Vd.uh=vsat(Vu.uw,Vv.uw)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 0 0 1 v v v v v P P 0 u u u u u 1 1 0 d d d d d + +define pcodeop Vuh_vsat_VuwVuw; + +:vsat VdUH_0004,VuUW_0812,VvUW_1620 EndPacket is iclass=0x1 & op2127=0x79 & op13=0x0 & op0507=0x6 & VdUH_0004 & VuUW_0812 & VvUW_1620 & $(END_PACKET) { + VdUH_0004 = Vuh_vsat_VuwVuw(VuUW_0812,VvUW_1620); + build EndPacket; +} + +# (hvx,1) vsat -- "Vd.ub=vsat(Vu.h,Vv.h)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 0 1 1 v v v v v P P 0 u u u u u 0 1 0 d d d d d + +define pcodeop Vub_vsat_VhVh; + +:vsat VdUB_0004,VuH_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x7b & op13=0x0 & op0507=0x2 & VdUB_0004 & VuH_0812 & VvH_1620 & $(END_PACKET) { + VdUB_0004 = Vub_vsat_VhVh(VuH_0812,VvH_1620); + build EndPacket; +} + +# (hvx,1) vsat -- "Vd.h=vsat(Vu.w,Vv.w)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 0 1 1 v v v v v P P 0 u u u u u 0 1 1 d d d d d + +define pcodeop Vh_vsat_VwVw; + +:vsat VdH_0004,VuW_0812,VvW_1620 EndPacket is iclass=0x1 & op2127=0x7b & op13=0x0 & op0507=0x3 & VdH_0004 & VuW_0812 & VvW_1620 & $(END_PACKET) { + VdH_0004 = Vh_vsat_VwVw(VuW_0812,VvW_1620); + build EndPacket; +} + +# (hvx,1) vshuffe -- "Vd.b=vshuffe(Vu.b,Vv.b)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 0 1 0 v v v v v P P 0 u u u u u 0 0 1 d d d d d + +define pcodeop vshuffe_VbVb; + +:vshuffe VdB_0004,VuB_0812,VvB_1620 EndPacket is iclass=0x1 & op2127=0x7a & op13=0x0 & op0507=0x1 & VdB_0004 & VuB_0812 & VvB_1620 & $(END_PACKET) { + VdB_0004 = vshuffe_VbVb(VuB_0812,VvB_1620); + build EndPacket; +} + +# (hvx,1) vshuffo -- "Vd.b=vshuffo(Vu.b,Vv.b)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 0 1 0 v v v v v P P 0 u u u u u 0 1 0 d d d d d + +define pcodeop vshuffo_VbVb; + +:vshuffo VdB_0004,VuB_0812,VvB_1620 EndPacket is iclass=0x1 & op2127=0x7a & op13=0x0 & op0507=0x2 & VdB_0004 & VuB_0812 & VvB_1620 & $(END_PACKET) { + VdB_0004 = vshuffo_VbVb(VuB_0812,VvB_1620); + build EndPacket; +} + +# (hvx,1) vshuffe -- "Vd.h=vshuffe(Vu.h,Vv.h)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 0 1 0 v v v v v P P 0 u u u u u 0 1 1 d d d d d + +define pcodeop vshuffe_VhVh; + +:vshuffe VdH_0004,VuH_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x7a & op13=0x0 & op0507=0x3 & VdH_0004 & VuH_0812 & VvH_1620 & $(END_PACKET) { + VdH_0004 = vshuffe_VhVh(VuH_0812,VvH_1620); + build EndPacket; +} + +# (hvx,1) vshuffo -- "Vd.h=vshuffo(Vu.h,Vv.h)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 0 1 0 v v v v v P P 0 u u u u u 1 0 0 d d d d d + +define pcodeop vshuffo_VhVh; + +:vshuffo VdH_0004,VuH_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x7a & op13=0x0 & op0507=0x4 & VdH_0004 & VuH_0812 & VvH_1620 & $(END_PACKET) { + VdH_0004 = vshuffo_VhVh(VuH_0812,VvH_1620); + build EndPacket; +} + +# (hvx,9) vextract -- "Rd=vextract(Vu,Rs)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 1 0 0 1 0 0 0 0 s s s s s P P 0 u u u u u 0 0 1 d d d d d + +:vextract Rd5,Vu_0812,rx5 EndPacket is iclass=0x9 & op2127=0x10 & op13=0x0 & op0507=0x1 & Rd5 & Vu_0812 & rx5 & $(END_PACKET) { + # solo instruction in packet - assume .tmp vector not relavent + wordOff:4 = rx5 & ($(HVX_VECTOR_SIZE) - 1) & ~0x3; + vptr:4 = $(HVX_VECTOR_BASE) + wordOff; + Rd5 = *[register]:4 vptr; + build EndPacket; +} + +# (hvx,2) vgather -- "vtmp.h=vgather(Rt,Mu,Vvv.w).h" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 1 1 1 0 0 0 t t t t t P P u - - 0 1 0 - - - v v v v v + +define pcodeop vgather_RMWw; + +:vgather.h rx5,mu,VssW_0004 EndPacket is iclass=0x2 & op2127=0x78 & op0810=0x2 & rx5 & mu & VssW_0004 & Vd5tmp & $(END_PACKET) { + Vd5tmp = vgather_RMWw(rx5,mu,VssW_0004); + build EndPacket; +} + +# (hvx,2) vgather -- "if (Qs4) vtmp.h=vgather(Rt,Mu,Vvv.w).h" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 1 1 1 0 0 0 t t t t t P P u - - 1 1 0 - s s v v v v v + +define pcodeop vgather_QRMWw; + +:vgather.h^".if("^qv0506^")" rx5,mu,VssW_0004 EndPacket is iclass=0x2 & op2127=0x78 & op0810=0x6 & qv0506 & rx5 & mu & VssW_0004 & Vd5tmp & $(END_PACKET) { + Vd5tmp = vgather_QRMWw(qv0506,rx5,mu,VssW_0004); # conditional handled within vgatherIf function + build EndPacket; +} + +# (hvx,2) vgather -- "vtmp.w=vgather(Rt,Mu,Vv.w).w" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 1 1 1 0 0 0 t t t t t P P u - - 0 0 0 - - - v v v v v + +define pcodeop vgather_RMVw; + +:vgather.w rx5,mu,VsW_0004 EndPacket is iclass=0x2 & op2127=0x78 & op0810=0x0 & rx5 & mu & VsW_0004 & Vd5tmp & $(END_PACKET) { + Vd5tmp = vgather_RMVw(rx5,mu,VsW_0004); + build EndPacket; +} + +# (hvx,2) vgather -- "vtmp.h=vgather(Rt,Mu,Vv.h).h" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 1 1 1 0 0 0 t t t t t P P u - - 0 0 1 - - - v v v v v + +define pcodeop vgather_RMVh; + +:vgather.h rx5,mu,VsH_0004 EndPacket is iclass=0x2 & op2127=0x78 & op0810=0x1 & rx5 & mu & VsH_0004 & Vd5tmp & $(END_PACKET) { + Vd5tmp = vgather_RMVh(rx5,mu,VsH_0004); + build EndPacket; +} + +# (hvx,2) vgather -- "if (Qs4) vtmp.w=vgather(Rt,Mu,Vv.w).w" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 1 1 1 0 0 0 t t t t t P P u - - 1 0 0 - s s v v v v v + +# NOTES: +# - Rt identifies a memory source area to be gathered into temp vector +# - Mu identifies length-1 of memory region in bytes +# - Vv.w or Vv.h identifies bytes offsets into the memory region +# - vgather must be paired with vmem Vtmp.new store + +define pcodeop vgather_QRMVw; + +:vgather.w^".if("^qv0506^")" rx5,mu,VsW_0004 EndPacket is iclass=0x2 & op2127=0x78 & op0810=0x4 & qv0506 & rx5 & mu & VsW_0004 & Vd5tmp & $(END_PACKET) { + Vd5tmp = vgather_QRMVw(qv0506,rx5,mu,VsW_0004); # conditional handled within vgatherIf function + build EndPacket; +} + +# (hvx,2) vgather -- "if (Qs4) vtmp.h=vgather(Rt,Mu,Vv.h).h" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 1 1 1 0 0 0 t t t t t P P u - - 1 0 1 - s s v v v v v + +define pcodeop vgather_QRMVh; + +:vgather.h^".if("^qv0506^")" rx5,mu,VsH_0004 EndPacket is iclass=0x2 & op2127=0x78 & op0810=0x5 & qv0506 & rx5 & mu & VsH_0004 & Vd5tmp & $(END_PACKET) { + Vd5tmp = vgather_QRMVh(qv0506,rx5,mu,VsH_0004); # conditional handled within vgatherIf function + build EndPacket; +} + +# (hvx,2) vmem -- "Vd=vmem(Rt+#s4)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 0 0 0 0 t t t t t P P i 0 0 i i i 0 0 0 d d d d d +# +# (hvx,2) vmem -- "Vd=vmem(Rt+#s4):nt" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 0 0 1 0 t t t t t P P i 0 0 i i i 0 0 0 d d d d d + +:vmem^ntHint22 Vd5,VAlignMemAddrRxS4 EndPacket is iclass=0x2 & op21=0 & op2327=0x10 & op1112=0x0 & op0507=0x0 & ntHint22 & Vd5 & VAlignMemAddrRxS4 & $(END_PACKET) [ cond=0; ] { + Vd5 = VAlignMemAddrRxS4; # Vd5 handles forwarding commit + build EndPacket; +} + +# (hvx,2) vmem -- "if (Pv) Vd=vmem(Rt+#s4)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 0 1 0 0 t t t t t P P i v v i i i 0 1 0 d d d d d +# +# (hvx,2) vmem -- "if (!Pv) Vd=vmem(Rt+#s4)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 0 1 0 0 t t t t t P P i v v i i i 0 1 1 d d d d d +# +# (hvx,2) vmem -- "if (Pv) Vd=vmem(Rt+#s4):nt" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 0 1 1 0 t t t t t P P i v v i i i 0 1 0 d d d d d +# +# (hvx,2) vmem -- "if (!Pv) Vd=vmem(Rt+#s4):nt" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 0 1 1 0 t t t t t P P i v v i i i 0 1 1 d d d d d + +:vmem^VPuCond1112_S05^ntHint22 vd5,VAlignMemAddrRxS4 EndPacket is iclass=0x2 & op21=0 & op2327=0x11 & op0607=0x1 & VPuCond1112_S05 & ntHint22 & vd5 & vd5_ & SetVNRegVd5 & VAlignMemAddrRxS4 & $(END_PACKET) { + build VPuCond1112_S05; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + vd5_ = VAlignMemAddrRxS4; + + <> + if (ConditionReg == 0) goto ; + vd5 = vd5_; + +} + +# (hvx,2) vmem -- "Vd=vmem(Rx++#s3)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 1 0 0 0 x x x x x P P - 0 0 i i i 0 0 0 d d d d d +# +# (hvx,2) vmem -- "Vd=vmem(Rx++#s3):nt" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 1 0 1 0 x x x x x P P - 0 0 i i i 0 0 0 d d d d d + +:vmem^ntHint22 Vd5,VAlignMemAddrRxAIS3 EndPacket is iclass=0x2 & op21=0 & op2327=0x12 & op1112=0x0 & op0507=0x0 & ntHint22 & Vd5 & VAlignMemAddrRxAIS3 & $(END_PACKET) [ cond=0; ] { + Vd5 = VAlignMemAddrRxAIS3; # Vd5 handles forwarding commit + build EndPacket; +} + +# (hvx,2) vmem -- "if (Pv) Vd=vmem(Rx++#s3)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 1 1 0 0 x x x x x P P - v v i i i 0 1 0 d d d d d +# +# (hvx,2) vmem -- "if (!Pv) Vd=vmem(Rx++#s3)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 1 1 0 0 x x x x x P P - v v i i i 0 1 1 d d d d d +# +# (hvx,2) vmem -- "if (Pv) Vd=vmem(Rx++#s3):nt" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 1 1 1 0 x x x x x P P - v v i i i 0 1 0 d d d d d +# +# (hvx,2) vmem -- "if (!Pv) Vd=vmem(Rx++#s3):nt" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 1 1 1 0 x x x x x P P - v v i i i 0 1 1 d d d d d + +:vmem^VPuCond1112_S05^ntHint22 vd5,VAlignMemAddrRxAIS3 EndPacket is iclass=0x2 & op21=0 & op2327=0x13 & op0607=0x1 & VPuCond1112_S05 & ntHint22 & vd5 & vd5_ & SetVNRegVd5 & VAlignMemAddrRxAIS3 & $(END_PACKET) [ cond=1; ] { + build VPuCond1112_S05; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + vd5_ = VAlignMemAddrRxAIS3; + + <> + if (ConditionReg == 0) goto ; + vd5 = vd5_; + +} + +# (hvx,2) vmem -- "Vd=vmem(Rx++Mu)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 1 1 0 0 0 x x x x x P P u 0 0 - - - 0 0 0 d d d d d +# +# (hvx,2) vmem -- "Vd=vmem(Rx++Mu):nt" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 1 1 0 1 0 x x x x x P P u 0 0 - - - 0 0 0 d d d d d + +:vmem^ntHint22 Vd5,VAlignMemAddrRxAIMu EndPacket is iclass=0x2 & op21=0 & op2327=0x16 & op1112=0x0 & op0507=0x0 & ntHint22 & Vd5 & VAlignMemAddrRxAIMu & $(END_PACKET) [ cond=0; ] { + Vd5 = VAlignMemAddrRxAIMu; # Vd5 handles forwarding commit + build EndPacket; +} + +# (hvx,2) vmem -- "if (Pv) Vd=vmem(Rx++Mu)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 1 1 1 0 0 x x x x x P P u v v - - - 0 1 0 d d d d d +# +# (hvx,2) vmem -- "if (!Pv) Vd=vmem(Rx++Mu)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 1 1 1 0 0 x x x x x P P u v v - - - 0 1 1 d d d d d +# +# (hvx,2) vmem -- "if (Pv) Vd=vmem(Rx++Mu):nt" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 1 1 1 1 0 x x x x x P P u v v - - - 0 1 0 d d d d d +# +# (hvx,2) vmem -- "if (!Pv) Vd=vmem(Rx++Mu):nt" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 1 1 1 1 0 x x x x x P P u v v - - - 0 1 1 d d d d d + +:vmem^VPuCond1112_S05^ntHint22 vd5,VAlignMemAddrRxAIMu EndPacket is iclass=0x2 & op21=0 & op2327=0x17 & op0607=0x1 & VPuCond1112_S05 & ntHint22 & vd5 & vd5_ & SetVNRegVd5 & VAlignMemAddrRxAIMu & $(END_PACKET) [ cond=1; ] { + build VPuCond1112_S05; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + vd5_ = VAlignMemAddrRxAIMu; + + <> + if (ConditionReg == 0) goto ; + vd5 = vd5_; + +} + +# (hvx,2) vmem -- "Vd.cur=vmem(Rt+#s4)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 0 0 0 0 t t t t t P P i 0 0 i i i 0 0 1 d d d d d +# +# (hvx,2) vmem -- "Vd.cur=vmem(Rt+#s4):nt" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 0 0 1 0 t t t t t P P i 0 0 i i i 0 0 1 d d d d d + +:vmem^ntHint22 Vd5cur,VAlignMemAddrRxS4 EndPacket is iclass=0x2 & op21=0 & op2327=0x10 & op1112=0x0 & op0507=0x1 & ntHint22 & Vd5cur & VAlignMemAddrRxS4 & $(END_PACKET) [ cond = 0; ] { + Vd5cur = VAlignMemAddrRxS4; + build EndPacket; +} + +# (hvx,2) vmem -- "if (Pv) Vd.cur=vmem(Rt+#s4)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 0 1 0 0 t t t t t P P i v v i i i 1 0 0 d d d d d +# +# (hvx,2) vmem -- "if (!Pv) Vd.cur=vmem(Rt+#s4)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 0 1 0 0 t t t t t P P i v v i i i 1 0 1 d d d d d +# +# (hvx,2) vmem -- "if (Pv) Vd.cur=vmem(Rt+#s4):nt" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 0 1 1 0 t t t t t P P i v v i i i 1 0 0 d d d d d +# +# (hvx,2) vmem -- "if (!Pv) Vd.cur=vmem(Rt+#s4):nt" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 0 1 1 0 t t t t t P P i v v i i i 1 0 1 d d d d d + +:vmem^VPuCond1112_S05^ntHint22 Vd5cur,VAlignMemAddrRxS4 EndPacket is iclass=0x2 & op21=0 & op2327=0x11 & op0607=0x2 & VPuCond1112_S05 & ntHint22 & Vd5cur & VAlignMemAddrRxS4 & $(END_PACKET) [ cond=1; ] { + build VPuCond1112_S05; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + Vd5cur = VAlignMemAddrRxS4; + +} + +# (hvx,2) vmem -- "Vd.cur=vmem(Rx++#s3)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 1 0 0 0 x x x x x P P - 0 0 i i i 0 0 1 d d d d d +# +# (hvx,2) vmem -- "Vd.cur=vmem(Rx++#s3):nt" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 1 0 1 0 x x x x x P P - 0 0 i i i 0 0 1 d d d d d +# + +:vmem^ntHint22 Vd5cur,VAlignMemAddrRxAIS3 EndPacket is iclass=0x2 & op21=0 & op2327=0x12 & op1112=0x0 & op0507=0x1 & ntHint22 & Vd5cur & VAlignMemAddrRxAIS3 & $(END_PACKET) [ cond=0; ] { + Vd5cur = VAlignMemAddrRxAIS3; + build EndPacket; +} + +# (hvx,2) vmem -- "if (Pv) Vd.cur=vmem(Rx++#s3)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 1 1 0 0 x x x x x P P - v v i i i 1 0 0 d d d d d +# +# (hvx,2) vmem -- "if (!Pv) Vd.cur=vmem(Rx++#s3)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 1 1 0 0 x x x x x P P - v v i i i 1 0 1 d d d d d +# +# (hvx,2) vmem -- "if (Pv) Vd.cur=vmem(Rx++#s3):nt" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 1 1 1 0 x x x x x P P - v v i i i 1 0 0 d d d d d +# +# (hvx,2) vmem -- "if (!Pv) Vd.cur=vmem(Rx++#s3):nt" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 1 1 1 0 x x x x x P P - v v i i i 1 0 1 d d d d d + +:vmem^VPuCond1112_S05^ntHint22 Vd5cur,VAlignMemAddrRxAIS3 EndPacket is iclass=0x2 & op21=0 & op2327=0x13 & op0607=0x2 & VPuCond1112_S05 & ntHint22 & Vd5cur & VAlignMemAddrRxAIS3 & $(END_PACKET) [ cond=1; ] { + build VPuCond1112_S05; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + Vd5cur = VAlignMemAddrRxAIS3; + +} + +# (hvx,2) vmem -- "Vd.cur=vmem(Rx++Mu)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 1 1 0 0 0 x x x x x P P u 0 0 - - - 0 0 1 d d d d d +# +# (hvx,2) vmem -- "Vd.cur=vmem(Rx++Mu):nt" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 1 1 0 1 0 x x x x x P P u 0 0 - - - 0 0 1 d d d d d + +:vmem^ntHint22 Vd5cur,VAlignMemAddrRxAIMu EndPacket is iclass=0x2 & op21=0 & op2327=0x16 & op1112=0x0 & op0507=0x1 & ntHint22 & Vd5cur & VAlignMemAddrRxAIMu & $(END_PACKET) [ cond=0;] { + Vd5cur = VAlignMemAddrRxAIMu; + build EndPacket; +} + +# (hvx,2) vmem -- "if (Pv) Vd.cur=vmem(Rx++Mu)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 1 1 1 0 0 x x x x x P P u v v - - - 1 0 0 d d d d d +# +# (hvx,2) vmem -- "if (!Pv) Vd.cur=vmem(Rx++Mu)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 1 1 1 0 0 x x x x x P P u v v - - - 1 0 1 d d d d d +# +# (hvx,2) vmem -- "if (Pv) Vd.cur=vmem(Rx++Mu):nt" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 1 1 1 1 0 x x x x x P P u v v - - - 1 0 0 d d d d d +# +# (hvx,2) vmem -- "if (!Pv) Vd.cur=vmem(Rx++Mu):nt" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 1 1 1 1 0 x x x x x P P u v v - - - 1 0 1 d d d d d + +:vmem^VPuCond1112_S05^ntHint22 Vd5cur,VAlignMemAddrRxAIMu EndPacket is iclass=0x2 & op21=0 & op2327=0x17 & op0607=0x2 & VPuCond1112_S05 & ntHint22 & Vd5cur & VAlignMemAddrRxAIMu & $(END_PACKET) [ cond=1; ] { + build VPuCond1112_S05; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + Vd5cur = VAlignMemAddrRxAIMu; + +} + +# (hvx,2) vmem -- "Vd.tmp=vmem(Rt+#s4)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 0 0 0 0 t t t t t P P i 0 0 i i i 0 1 0 d d d d d +# +# (hvx,2) vmem -- "Vd.tmp=vmem(Rt+#s4):nt" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 0 0 1 0 t t t t t P P i 0 0 i i i 0 1 0 d d d d d + +:vmem^ntHint22 Vd5tmp,VAlignMemAddrRxS4 EndPacket is iclass=0x2 & op21=0 & op2327=0x10 & op1112=0x0 & op0507=0x2 & ntHint22 & Vd5tmp & VAlignMemAddrRxS4 & $(END_PACKET) { + Vd5tmp = VAlignMemAddrRxS4; + build EndPacket; +} + +# (hvx,2) vmem -- "if (Pv) Vd.tmp=vmem(Rt+#s4)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 0 1 0 0 t t t t t P P i v v i i i 1 1 0 d d d d d +# +# (hvx,2) vmem -- "if (!Pv) Vd.tmp=vmem(Rt+#s4)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 0 1 0 0 t t t t t P P i v v i i i 1 1 1 d d d d d +# +# (hvx,2) vmem -- "if (Pv) Vd.tmp=vmem(Rt+#s4):nt" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 0 1 1 0 t t t t t P P i v v i i i 1 1 0 d d d d d +# (hvx,2) vmem -- "if (!Pv) Vd.tmp=vmem(Rt+#s4):nt" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 0 1 1 0 t t t t t P P i v v i i i 1 1 1 d d d d d + +:vmem^VPuCond1112_S05^ntHint22 Vd5tmp,VAlignMemAddrRxS4 EndPacket is iclass=0x2 & op21=0 & op2327=0x11 & op0607=0x3 & VPuCond1112_S05 & ntHint22 & Vd5tmp & VAlignMemAddrRxS4 & $(END_PACKET) { + build VPuCond1112_S05; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + Vd5tmp = VAlignMemAddrRxS4; + +} + +# (hvx,2) vmem -- "Vd.tmp=vmem(Rx++#s3)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 1 0 0 0 x x x x x P P - 0 0 i i i 0 1 0 d d d d d +# +# (hvx,2) vmem -- "Vd.tmp=vmem(Rx++#s3):nt" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 1 0 1 0 x x x x x P P - 0 0 i i i 0 1 0 d d d d d + +:vmem^ntHint22 Vd5tmp,VAlignMemAddrRxAIS3 EndPacket is iclass=0x2 & op21=0 & op2327=0x12 & op1112=0x0 & op0507=0x2 & ntHint22 & Vd5tmp & VAlignMemAddrRxAIS3 & $(END_PACKET) [ cond=0; ] { + Vd5tmp = VAlignMemAddrRxAIS3; + build EndPacket; +} + +# (hvx,2) vmem -- "if (Pv) Vd.tmp=vmem(Rx++#s3)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 1 1 0 0 x x x x x P P - v v i i i 1 1 0 d d d d d +# +# (hvx,2) vmem -- "if (!Pv) Vd.tmp=vmem(Rx++#s3)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 1 1 0 0 x x x x x P P - v v i i i 1 1 1 d d d d d +# +# (hvx,2) vmem -- "if (Pv) Vd.tmp=vmem(Rx++#s3):nt" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 1 1 1 0 x x x x x P P - v v i i i 1 1 0 d d d d d +# +# (hvx,2) vmem -- "if (!Pv) Vd.tmp=vmem(Rx++#s3):nt" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 1 1 1 0 x x x x x P P - v v i i i 1 1 1 d d d d d + +:vmem^VPuCond1112_S05^ntHint22 Vd5tmp,VAlignMemAddrRxAIS3 EndPacket is iclass=0x2 & op21=0 & op2327=0x13 & op0607=0x3 & VPuCond1112_S05 & ntHint22 & Vd5tmp & VAlignMemAddrRxAIS3 & $(END_PACKET) [ cond=1; ] { + build VPuCond1112_S05; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + Vd5tmp = VAlignMemAddrRxAIS3; + +} + +# (hvx,2) vmem -- "Vd.tmp=vmem(Rx++Mu)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 1 1 0 0 0 x x x x x P P u 0 0 - - - 0 1 0 d d d d d +# +# (hvx,2) vmem -- "Vd.tmp=vmem(Rx++Mu):nt" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 1 1 0 1 0 x x x x x P P u 0 0 - - - 0 1 0 d d d d d + +:vmem^ntHint22 Vd5tmp,VAlignMemAddrRxAIMu EndPacket is iclass=0x2 & op21=0 & op2327=0x16 & op1112=0x0 & op0507=0x2 & ntHint22 & Vd5tmp & VAlignMemAddrRxAIMu & $(END_PACKET) [ cond=0; ] { + Vd5tmp = VAlignMemAddrRxAIMu; + build EndPacket; +} + +# (hvx,2) vmem -- "if (Pv) Vd.tmp=vmem(Rx++Mu)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 1 1 1 0 0 x x x x x P P u v v - - - 1 1 0 d d d d d +# +# (hvx,2) vmem -- "if (!Pv) Vd.tmp=vmem(Rx++Mu)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 1 1 1 0 0 x x x x x P P u v v - - - 1 1 1 d d d d d +# +# (hvx,2) vmem -- "if (Pv) Vd.tmp=vmem(Rx++Mu):nt" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 1 1 1 1 0 x x x x x P P u v v - - - 1 1 0 d d d d d +# +# (hvx,2) vmem -- "if (!Pv) Vd.tmp=vmem(Rx++Mu):nt" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 1 1 1 1 0 x x x x x P P u v v - - - 1 1 1 d d d d d + +:vmem^VPuCond1112_S05^ntHint22 Vd5tmp,VAlignMemAddrRxAIMu EndPacket is iclass=0x2 & op21=0 & op2327=0x17 & op0607=0x3 & VPuCond1112_S05 & ntHint22 & Vd5tmp & VAlignMemAddrRxAIMu & $(END_PACKET) [ cond=1; ] { + build VPuCond1112_S05; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + Vd5tmp = VAlignMemAddrRxAIMu; + +} + +# (hvx,2) vmemu -- "Vd=vmemu(Rt+#s4)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 0 0 0 0 t t t t t P P i 0 0 i i i 1 1 1 d d d d d + +:vmemu Vd5,VMemAddrRxS4 EndPacket is iclass=0x2 & op2127=0x40 & op1112=0x0 & op0507=0x7 & Vd5 & VMemAddrRxS4 & $(END_PACKET) { + Vd5 = VMemAddrRxS4; # Vd5 handles forwarding commit + build EndPacket; +} + +# (hvx,2) vmemu -- "Vd=vmemu(Rx++#s3)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 1 0 0 0 x x x x x P P - 0 0 i i i 1 1 1 d d d d d + +:vmemu Vd5,VMemAddrRxAIS3 EndPacket is iclass=0x2 & op2127=0x48 & op1112=0x0 & op0507=0x7 & Vd5 & VMemAddrRxAIS3 & $(END_PACKET) [ cond=0; ] { + Vd5 = VMemAddrRxAIS3; # Vd5 handles forwarding commit + build EndPacket; +} + +# (hvx,2) vmemu -- "Vd=vmemu(Rx++Mu)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 1 1 0 0 0 x x x x x P P u 0 0 - - - 1 1 1 d d d d d + +:vmemu Vd5,VMemAddrRxAIMu EndPacket is iclass=0x2 & op2127=0x58 & op1112=0x0 & op0507=0x7 & Vd5 & VMemAddrRxAIMu & $(END_PACKET) [ cond=0; ] { + Vd5 = VMemAddrRxAIMu; # Vd5 handles forwarding commit + build EndPacket; +} + +# (hvx,1) v6mpy -- "Vxx.w+=v6mpy(Vuu.ub,Vvv.b,#u2):v" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 0 0 1 v v v v v P P 1 u u u u u 0 i i x x x x x + +define pcodeop Ww_v6mpyacc_WwWubWbI_v; + +:v6mpy+=^":v" VddW_0004,VuuUB_0812,VvvB_1620,Uimm2_0506 EndPacket is iclass=0x1 & op2127=0x79 & op13=0x1 & op7=0x0 & vss5 & VddW_0004 & VuuUB_0812 & VvvB_1620 & Uimm2_0506 & $(END_PACKET) { + VddW_0004 = Ww_v6mpyacc_WwWubWbI_v(vss5,VuuUB_0812,VvvB_1620,Uimm2_0506); + build EndPacket; +} + +# (hvx,1) v6mpy -- "Vxx.w+=v6mpy(Vuu.ub,Vvv.b,#u2):h" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 0 0 1 v v v v v P P 1 u u u u u 1 i i x x x x x + +define pcodeop Ww_v6mpyacc_WwWubWbI_h; + +:v6mpy+=^":h" VddW_0004,VuuUB_0812,VvvB_1620,Uimm2_0506 EndPacket is iclass=0x1 & op2127=0x79 & op13=0x1 & op7=0x1 & vss5 & VddW_0004 & VuuUB_0812 & VvvB_1620 & Uimm2_0506 & $(END_PACKET) { + VddW_0004 = Ww_v6mpyacc_WwWubWbI_h(vss5,VuuUB_0812,VvvB_1620,Uimm2_0506); + build EndPacket; +} + +# (hvx,1) v6mpy -- "Vdd.w=v6mpy(Vuu.ub,Vvv.b,#u2):v" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 0 1 0 v v v v v P P 1 u u u u u 0 i i d d d d d + +define pcodeop Ww_v6mpy_WubWbI_v; + +:v6mpy^":v" VddW_0004,VuuUB_0812,VvvB_1620,Uimm2_0506 EndPacket is iclass=0x1 & op2127=0x7a & op13=0x1 & op7=0x0 & VddW_0004 & VuuUB_0812 & VvvB_1620 & Uimm2_0506 & $(END_PACKET) { + VddW_0004 = Ww_v6mpy_WubWbI_v(VuuUB_0812,VvvB_1620,Uimm2_0506); + build EndPacket; +} + +# (hvx,1) v6mpy -- "Vdd.w=v6mpy(Vuu.ub,Vvv.b,#u2):h" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 0 1 0 v v v v v P P 1 u u u u u 1 i i d d d d d + +define pcodeop Ww_v6mpy_WubWbI_h; + +:v6mpy^":h" VddW_0004,VuuUB_0812,VvvB_1620,Uimm2_0506 EndPacket is iclass=0x1 & op2127=0x7a & op13=0x1 & op7=0x1 & VddW_0004 & VuuUB_0812 & VvvB_1620 & Uimm2_0506 & $(END_PACKET) { + VddW_0004 = Ww_v6mpy_WubWbI_h(VuuUB_0812,VvvB_1620,Uimm2_0506); + build EndPacket; +} + +# (hvx,1) vadd -- "Vxx.w+=vadd(Vu.h,Vv.h)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 0 0 1 v v v v v P P 1 u u u u u 0 1 0 x x x x x + +define pcodeop Ww_vaddacc_WwVhVh; + +:vadd+= VddW_0004,VuH_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x61 & op13=0x1 & op0507=0x2 & vss5 & VddW_0004 & VuH_0812 & VvH_1620 & $(END_PACKET) { + VddW_0004 = Ww_vaddacc_WwVhVh(vss5,VuH_0812,VvH_1620); + build EndPacket; +} + +# (hvx,1) vadd -- "Vxx.w+=vadd(Vu.uh,Vv.uh)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 0 1 0 v v v v v P P 1 u u u u u 1 0 0 x x x x x + +define pcodeop Ww_vaddacc_WwVuhVuh; + +:vadd+= VddW_0004,VuUH_0812,VvUH_1620 EndPacket is iclass=0x1 & op2127=0x62 & op13=0x1 & op0507=0x4 & vss5 & VddW_0004 & VuUH_0812 & VvUH_1620 & $(END_PACKET) { + VddW_0004 = Ww_vaddacc_WwVuhVuh(vss5,VuUH_0812,VvUH_1620); + build EndPacket; +} + +# (hvx,1) vadd -- "Vxx.h+=vadd(Vu.ub,Vv.ub)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 0 1 0 v v v v v P P 1 u u u u u 1 0 1 x x x x x + +define pcodeop Wh_vaddacc_WhVubVub; + +:vadd+= VddH_0004,VuUB_0812,VvUB_1620 EndPacket is iclass=0x1 & op2127=0x62 & op13=0x1 & op0507=0x5 & vss5 & VddH_0004 & VuUB_0812 & VvUB_1620 & $(END_PACKET) { + VddH_0004 = Wh_vaddacc_WhVubVub(vss5,VuUB_0812,VvUB_1620); + build EndPacket; +} + +# (hvx,1) vadd -- "Vdd.h=vadd(Vu.ub,Vv.ub)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 0 1 v v v v v P P 0 u u u u u 0 1 0 d d d d d + +define pcodeop Wh_vadd_VubVub; + +:vadd VddH_0004,VuUB_0812,VvUB_1620 EndPacket is iclass=0x1 & op2127=0x65 & op13=0x0 & op0507=0x2 & VddH_0004 & VuUB_0812 & VvUB_1620 & $(END_PACKET) { + VddH_0004 = Wh_vadd_VubVub(VuUB_0812,VvUB_1620); + build EndPacket; +} + +# (hvx,1) vadd -- "Vdd.w=vadd(Vu.uh,Vv.uh)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 0 1 v v v v v P P 0 u u u u u 0 1 1 d d d d d + +define pcodeop Ww_vadd_VuhVuh; + +:vadd VddW_0004,VuUH_0812,VvUH_1620 EndPacket is iclass=0x1 & op2127=0x65 & op13=0x0 & op0507=0x3 & VddW_0004 & VuUH_0812 & VvUH_1620 & $(END_PACKET) { + VddW_0004 = Ww_vadd_VuhVuh(VuUH_0812,VvUH_1620); + build EndPacket; +} + +# (hvx,1) vadd -- "Vdd.w=vadd(Vu.h,Vv.h)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 0 1 v v v v v P P 0 u u u u u 1 0 0 d d d d d + +define pcodeop Ww_vadd_VhVh; + +:vadd VddW_0004,VuH_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x65 & op13=0x0 & op0507=0x4 & VddW_0004 & VuH_0812 & VvH_1620 & $(END_PACKET) { + VddW_0004 = Ww_vadd_VhVh(VuH_0812,VvH_1620); + build EndPacket; +} + +# (hvx,1) vsub -- "Vdd.h=vsub(Vu.ub,Vv.ub)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 0 1 v v v v v P P 0 u u u u u 1 0 1 d d d d d + +define pcodeop Wh_vsub_VubVub; + +:vsub VddH_0004,VuUB_0812,VvUB_1620 EndPacket is iclass=0x1 & op2127=0x65 & op13=0x0 & op0507=0x5 & VddH_0004 & VuUB_0812 & VvUB_1620 & $(END_PACKET) { + VddH_0004 = Wh_vsub_VubVub(VuUB_0812,VvUB_1620); + build EndPacket; +} + +# (hvx,1) vsub -- "Vdd.w=vsub(Vu.uh,Vv.uh)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 0 1 v v v v v P P 0 u u u u u 1 1 0 d d d d d + +define pcodeop Ww_vsub_VuhVuh; + +:vsub VddW_0004,VuUH_0812,VvUH_1620 EndPacket is iclass=0x1 & op2127=0x65 & op13=0x0 & op0507=0x6 & VddW_0004 & VuUH_0812 & VvUH_1620 & $(END_PACKET) { + VddW_0004 = Ww_vsub_VuhVuh(VuUH_0812,VvUH_1620); + build EndPacket; +} + +# (hvx,1) vsub -- "Vdd.w=vsub(Vu.h,Vv.h)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 0 1 v v v v v P P 0 u u u u u 1 1 1 d d d d d + +define pcodeop Ww_vsub_VhVh; + +:vsub VddW_0004,VuH_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x65 & op13=0x0 & op0507=0x7 & VddW_0004 & VuH_0812 & VvH_1620 & $(END_PACKET) { + VddW_0004 = Ww_vsub_VhVh(VuH_0812,VvH_1620); + build EndPacket; +} + +# (hvx,1) vdmpy -- "Vdd.h=vdmpy(Vuu.ub,Rt.b)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 0 0 0 t t t t t P P 0 u u u u u 1 1 1 d d d d d + +define pcodeop Ww_vdmpy_WubRb; + +:vdmpy VddH_0004,VuuUB_0812,RtB_1620 EndPacket is iclass=0x1 & op2127=0x48 & op13=0x0 & op0507=0x7 & VddH_0004 & VuuUB_0812 & RtB_1620 & $(END_PACKET) { + VddH_0004 = Ww_vdmpy_WubRb(VuuUB_0812,RtB_1620); + build EndPacket; +} + +# (hvx,1) vdmpy -- "Vxx.h+=vdmpy(Vuu.ub,Rt.b)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 0 0 0 t t t t t P P 1 u u u u u 1 1 1 x x x x x + +define pcodeop vdmpyacc_WhWubRb; + +:vdmpy+= VddH_0004,VuuUB_0812,RtB_1620 EndPacket is iclass=0x1 & op2127=0x48 & op13=0x1 & op0507=0x7 & vss5 & VddH_0004 & VuuUB_0812 & RtB_1620 & $(END_PACKET) { + VddH_0004 = vdmpyacc_WhWubRb(vss5,VuuUB_0812,RtB_1620); + build EndPacket; +} + +# (hvx,1) vdmpy -- "Vd.w=vdmpy(Vuu.h,Rt.uh,#1):sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 0 0 1 t t t t t P P 0 u u u u u 0 0 1 d d d d d + +define pcodeop Vw_vdmpy_WhRuh_sat; + +:vdmpy^":sat" VdW_0004,VuuH_0812,RtUH_1620 EndPacket is iclass=0x1 & op2127=0x49 & op13=0x0 & op0507=0x1 & VdW_0004 & VuuH_0812 & RtUH_1620 & $(END_PACKET) { + VdW_0004 = Vw_vdmpy_WhRuh_sat(VuuH_0812,RtUH_1620); + build EndPacket; +} + +# (hvx,1) vdmpy -- "Vd.w=vdmpy(Vuu.h,Rt.h):sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 0 0 1 t t t t t P P 0 u u u u u 0 1 1 d d d d d + +define pcodeop Vw_vdmpy_WhRh_sat; + +:vdmpy^":sat" VdW_0004,VuuH_0812,RtH_1620 EndPacket is iclass=0x1 & op2127=0x49 & op13=0x0 & op0507=0x3 & VdW_0004 & VuuH_0812 & RtH_1620 & $(END_PACKET) { + VdW_0004 = Vw_vdmpy_WhRh_sat(VuuH_0812,RtH_1620); + build EndPacket; +} + +# (hvx,1) vdmpy -- "Vdd.w=vdmpy(Vuu.h,Rt.b)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 0 0 1 t t t t t P P 0 u u u u u 1 0 0 d d d d d + +define pcodeop Ww_vdmpy_WhRb; + +:vdmpy VddW_0004,VuuH_0812,RtB_1620 EndPacket is iclass=0x1 & op2127=0x49 & op13=0x0 & op0507=0x4 & VddW_0004 & VuuH_0812 & RtB_1620 & $(END_PACKET) { + VddW_0004 = Ww_vdmpy_WhRb(VuuH_0812,RtB_1620); + build EndPacket; +} + +# (hvx,1) vdmpy -- "Vx.w+=vdmpy(Vuu.h,Rt.uh,#1):sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 0 0 1 t t t t t P P 1 u u u u u 0 0 1 x x x x x + +define pcodeop vdmpyacc_VwWhRuh_sat; + +:vdmpy+=^":sat" VdW_0004,VuuH_0812,RtUH_1620 EndPacket is iclass=0x1 & op2127=0x49 & op13=0x1 & op0507=0x1 & vs5 & VdW_0004 & VuuH_0812 & RtUH_1620 & $(END_PACKET) { + VdW_0004 = vdmpyacc_VwWhRuh_sat(vs5,VuuH_0812,RtUH_1620); + build EndPacket; +} + +# (hvx,1) vdmpy -- "Vx.w+=vdmpy(Vuu.h,Rt.h):sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 0 0 1 t t t t t P P 1 u u u u u 0 1 0 x x x x x + +define pcodeop vdmpyacc_VwWhRh_sat; + +:vdmpy+=^":sat" VdW_0004,VuuH_0812,RtH_1620 EndPacket is iclass=0x1 & op2127=0x49 & op13=0x1 & op0507=0x2 & vs5 & VdW_0004 & VuuH_0812 & RtH_1620 & $(END_PACKET) { + VdW_0004 = vdmpyacc_VwWhRh_sat(vs5,VuuH_0812,RtH_1620); + build EndPacket; +} + +# (hvx,1) vdmpy -- "Vxx.w+=vdmpy(Vuu.h,Rt.b)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 0 0 1 t t t t t P P 1 u u u u u 1 0 0 x x x x x + +define pcodeop vdmpyacc_WwWhRb; + +:vdmpy+= VddW_0004,VuuH_0812,RtB_1620 EndPacket is iclass=0x1 & op2127=0x49 & op13=0x1 & op0507=0x4 & vss5 & VddW_0004 & VuuH_0812 & RtB_1620 & $(END_PACKET) { + VddW_0004 = vdmpyacc_WwWhRb(vss5,VuuH_0812,RtB_1620); + build EndPacket; +} + +# (hvx,1) vdmpy -- "Vx.w+=vdmpy(Vu.h,Vv.h):sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 0 0 0 v v v v v P P 1 u u u u u 0 1 1 x x x x x + +define pcodeop vdmpyacc_VwVhVh_sat; + +:vdmpy+=^":sat" VdW_0004,VuH_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x60 & op13=0x1 & op0507=0x3 & vs5 & VdW_0004 & VuH_0812 & VvH_1620 & $(END_PACKET) { + VdW_0004 = vdmpyacc_VwVhVh_sat(vs5,VuH_0812,VvH_1620); + build EndPacket; +} + +# (hvx,1) vlut4 -- "Vd.h=vlut4(Vu.uh,Rtt.h)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 0 1 1 t t t t t P P 0 u u u u u 1 0 0 d d d d d + +define pcodeop vlut4_VuhPh; + +:vlut4 VdH_0004,VuUH_0812,RttH_1620 EndPacket is iclass=0x1 & op2127=0x4b & op13=0x0 & op0507=0x4 & VdH_0004 & VuUH_0812 & RttH_1620 & $(END_PACKET) { + VdH_0004 = vlut4_VuhPh(VuUH_0812,RttH_1620); + build EndPacket; +} + +# (hvx,1) vmpa -- "Vx.h=vmpa(Vx.h,Vu.h,Rtt.h):sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 1 0 0 t t t t t P P 1 u u u u u 1 0 0 x x x x x + +define pcodeop vmpa_VhVhVhPh_sat; + +:vmpa^":sat" VdH_0004,VsH_0004,VuH_0812,RttH_1620 EndPacket is iclass=0x1 & op2127=0x4c & op13=0x1 & op0507=0x4 & VdH_0004 & VsH_0004 & VuH_0812 & RttH_1620 & $(END_PACKET) { + VdH_0004 = vmpa_VhVhVhPh_sat(VsH_0004,VuH_0812,RttH_1620); + build EndPacket; +} + +# (hvx,1) vmpa -- "Vx.h=vmpa(Vx.h,Vu.uh,Rtt.uh):sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 1 0 0 t t t t t P P 1 u u u u u 1 0 1 x x x x x + +define pcodeop vmpa_VhVhVuhPuh_sat; + +:vmpa^":sat" VdH_0004,VsH_0004,VuUH_0812,RttUH_1620 EndPacket is iclass=0x1 & op2127=0x4c & op13=0x1 & op0507=0x5 & VdH_0004 & VsH_0004 & VuUH_0812 & RttUH_1620 & $(END_PACKET) { + VdH_0004 = vmpa_VhVhVuhPuh_sat(VsH_0004,VuUH_0812,RttUH_1620); + build EndPacket; +} + +# (hvx,1) vmps -- "Vx.h=vmps(Vx.h,Vu.uh,Rtt.uh):sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 1 0 0 t t t t t P P 1 u u u u u 1 1 0 x x x x x + +define pcodeop vmps_VhVhVuhPuh_sat; + +:vmps^":sat" VdH_0004,VsH_0004,VuUH_0812,RttUH_1620 EndPacket is iclass=0x1 & op2127=0x4c & op13=0x1 & op0507=0x6 & VdH_0004 & VsH_0004 & VuUH_0812 & RttUH_1620 & $(END_PACKET) { + VdH_0004 = vmps_VhVhVuhPuh_sat(VsH_0004,VuUH_0812,RttUH_1620); + build EndPacket; +} + +# (hvx,1) vmpa -- "Vdd.h=vmpa(Vuu.ub,Rt.b)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 0 0 1 t t t t t P P 0 u u u u u 1 1 0 d d d d d + +define pcodeop vmpa_WubRb; + +:vmpa VddH_0004,VuuUB_0812,RtB_1620 EndPacket is iclass=0x1 & op2127=0x49 & op13=0x0 & op0507=0x6 & VddH_0004 & VuuUB_0812 & RtB_1620 & $(END_PACKET) { + VddH_0004 = vmpa_WubRb(VuuUB_0812,RtB_1620); + build EndPacket; +} + +# (hvx,1) vmpa -- "Vdd.w=vmpa(Vuu.h,Rt.b)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 0 0 1 t t t t t P P 0 u u u u u 1 1 1 d d d d d + +define pcodeop vmpa_WhRb; + +:vmpa VddW_0004,VuuH_0812,RtB_1620 EndPacket is iclass=0x1 & op2127=0x49 & op13=0x0 & op0507=0x7 & VddW_0004 & VuuH_0812 & RtB_1620 & $(END_PACKET) { + VddW_0004 = vmpa_WhRb(VuuH_0812,RtB_1620); + build EndPacket; +} + +# (hvx,1) vmpa -- "Vxx.h+=vmpa(Vuu.ub,Rt.b)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 0 0 1 t t t t t P P 1 u u u u u 1 1 0 x x x x x + +define pcodeop vmpaacc_WhWubRb; + +:vmpa+= VddH_0004,VuuUB_0812,RtB_1620 EndPacket is iclass=0x1 & op2127=0x49 & op13=0x1 & op0507=0x6 & vss5 & VddH_0004 & VuuUB_0812 & RtB_1620 & $(END_PACKET) { + VddH_0004 = vmpaacc_WhWubRb(vss5,VuuUB_0812,RtB_1620); + build EndPacket; +} + +# (hvx,1) vmpa -- "Vxx.w+=vmpa(Vuu.h,Rt.b)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 0 0 1 t t t t t P P 1 u u u u u 1 1 1 x x x x x + +define pcodeop vmpaacc_WwWhRb; + +:vmpa+= VddW_0004,VuuH_0812,RtB_1620 EndPacket is iclass=0x1 & op2127=0x49 & op13=0x1 & op0507=0x7 & vss5 & VddW_0004 & VuuH_0812 & RtB_1620 & $(END_PACKET) { + VddW_0004 = vmpaacc_WwWhRb(vss5,VuuH_0812,RtB_1620); + build EndPacket; +} + +# (hvx,1) vmpa -- "Vdd.h=vmpa(Vuu.ub,Rt.ub)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 0 1 1 t t t t t P P 0 u u u u u 0 1 1 d d d d d + +define pcodeop vmpa_WubRub; + +:vmpa VddH_0004,VuuUB_0812,RtUB_1620 EndPacket is iclass=0x1 & op2127=0x4b & op13=0x0 & op0507=0x3 & VddH_0004 & VuuUB_0812 & RtUB_1620 & $(END_PACKET) { + VddH_0004 = vmpa_WubRub(VuuUB_0812,RtUB_1620); + build EndPacket; +} + +# (hvx,1) vmpa -- "Vdd.w=vmpa(Vuu.uh,Rt.b)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 1 0 0 t t t t t P P 0 u u u u u 1 0 1 d d d d d + +define pcodeop vmpa_WuhRb; + +:vmpa VddW_0004,VuuUH_0812,RtB_1620 EndPacket is iclass=0x1 & op2127=0x4c & op13=0x0 & op0507=0x5 & VddW_0004 & VuuUH_0812 & RtB_1620 & $(END_PACKET) { + VddW_0004 = vmpa_WuhRb(VuuUH_0812,RtB_1620); + build EndPacket; +} + +# (hvx,1) vmpa -- "Vxx.w+=vmpa(Vuu.uh,Rt.b)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 1 0 0 t t t t t P P 1 u u u u u 0 1 0 x x x x x + +define pcodeop vmpaacc_WwWuhRb; + +:vmpa+= VddW_0004,VuuUH_0812,RtB_1620 EndPacket is iclass=0x1 & op2127=0x4c & op13=0x1 & op0507=0x2 & vss5 & VddW_0004 & VuuUH_0812 & RtB_1620 & $(END_PACKET) { + VddW_0004 = vmpaacc_WwWuhRb(vss5,VuuUH_0812,RtB_1620); + build EndPacket; +} + +# (hvx,1) vmpa -- "Vxx.h+=vmpa(Vuu.ub,Rt.ub)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 1 0 1 t t t t t P P 1 u u u u u 1 0 0 x x x x x + +define pcodeop vmpaacc_WhWubRub; + +:vmpa+= VddH_0004,VuuUB_0812,RtUB_1620 EndPacket is iclass=0x1 & op2127=0x4d & op13=0x1 & op0507=0x4 & vss5 & VddH_0004 & VuuUB_0812 & RtUB_1620 & $(END_PACKET) { + VddH_0004 = vmpaacc_WhWubRub(vss5,VuuUB_0812,RtUB_1620); + build EndPacket; +} + +# (hvx,1) vmpa -- "Vdd.h=vmpa(Vuu.ub,Vvv.b)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 0 0 1 v v v v v P P 0 u u u u u 0 1 1 d d d d d + +define pcodeop vmpa_WubWb; + +:vmpa VddH_0004,VuuUB_0812,VvvB_1620 EndPacket is iclass=0x1 & op2127=0x61 & op13=0x0 & op0507=0x3 & VddH_0004 & VuuUB_0812 & VvvB_1620 & $(END_PACKET) { + VddH_0004 = vmpa_WubWb(VuuUB_0812,VvvB_1620); + build EndPacket; +} + +# (hvx,1) vmpa -- "Vdd.h=vmpa(Vuu.ub,Vvv.ub)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 1 1 v v v v v P P 0 u u u u u 1 1 1 d d d d d + +define pcodeop vmpa_WubWub; + +:vmpa VddH_0004,VuuUB_0812,VvvUB_1620 EndPacket is iclass=0x1 & op2127=0x67 & op13=0x0 & op0507=0x7 & VddH_0004 & VuuUB_0812 & VvvUB_1620 & $(END_PACKET) { + VddH_0004 = vmpa_WubWub(VuuUB_0812,VvvUB_1620); + build EndPacket; +} + +# (hvx,1) vmpy -- "Vdd.h=vmpy(Vu.ub,Rt.b)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 0 0 1 t t t t t P P 0 u u u u u 1 0 1 d d d d d + +define pcodeop vmpy_VubRb; + +:vmpy VddH_0004,VuUB_0812,RtB_1620 EndPacket is iclass=0x1 & op2127=0x49 & op13=0x0 & op0507=0x5 & VddH_0004 & VuUB_0812 & RtB_1620 & $(END_PACKET) { + VddH_0004 = vmpy_VubRb(VuUB_0812,RtB_1620); + build EndPacket; +} + +# (hvx,1) vmpy -- "Vxx.h+=vmpy(Vu.ub,Rt.b)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 0 0 1 t t t t t P P 1 u u u u u 1 0 1 x x x x x + +define pcodeop vmpyacc_WhVubRb; + +:vmpy+= VddH_0004,VuUB_0812,RtB_1620 EndPacket is iclass=0x1 & op2127=0x49 & op13=0x1 & op0507=0x5 & vss5 & VddH_0004 & VuUB_0812 & RtB_1620 & $(END_PACKET) { + VddH_0004 = vmpyacc_WhVubRb(vss5,VuUB_0812,RtB_1620); + build EndPacket; +} + +# (hvx,1) vmpy -- "Vdd.w=vmpy(Vu.h,Rt.h)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 0 1 0 t t t t t P P 0 u u u u u 0 0 0 d d d d d + +define pcodeop vmpy_VhRh; + +:vmpy VddW_0004,VuH_0812,RtH_1620 EndPacket is iclass=0x1 & op2127=0x4a & op13=0x0 & op0507=0x0 & VddW_0004 & VuH_0812 & RtH_1620 & $(END_PACKET) { + VddW_0004 = vmpy_VhRh(VuH_0812,RtH_1620); + build EndPacket; +} + +# (hvx,1) vmpy -- "Vdd.uw=vmpy(Vu.uh,Rt.uh)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 0 1 0 t t t t t P P 0 u u u u u 0 1 1 d d d d d + +define pcodeop vmpy_VuhRuh; + +:vmpy VddUW_0004,VuUH_0812,RtUH_1620 EndPacket is iclass=0x1 & op2127=0x4a & op13=0x0 & op0507=0x3 & VddUW_0004 & VuUH_0812 & RtUH_1620 & $(END_PACKET) { + VddUW_0004 = vmpy_VuhRuh(VuUH_0812,RtUH_1620); + build EndPacket; +} + +# (hvx,1) vmpy -- "Vxx.w+=vmpy(Vu.h,Rt.h):sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 0 1 0 t t t t t P P 1 u u u u u 0 0 0 x x x x x + +define pcodeop vmpyacc_WwVhRh_sat; + +:vmpy+=^":sat" VddW_0004,VuH_0812,RtH_1620 EndPacket is iclass=0x1 & op2127=0x4a & op13=0x1 & op0507=0x0 & vss5 & VddW_0004 & VuH_0812 & RtH_1620 & $(END_PACKET) { + VddW_0004 = vmpyacc_WwVhRh_sat(vss5,VuH_0812,RtH_1620); + build EndPacket; +} + +# (hvx,1) vmpy -- "Vxx.uw+=vmpy(Vu.uh,Rt.uh)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 0 1 0 t t t t t P P 1 u u u u u 0 0 1 x x x x x + +define pcodeop vmpyacc_WuwVuhRuh; + +:vmpy+= VddUW_0004,VuUH_0812,RtUH_1620 EndPacket is iclass=0x1 & op2127=0x4a & op13=0x1 & op0507=0x1 & vss5 & VddUW_0004 & VuUH_0812 & RtUH_1620 & $(END_PACKET) { + VddUW_0004 = vmpyacc_WuwVuhRuh(vss5,VuUH_0812,RtUH_1620); + build EndPacket; +} + +# (hvx,1) vmpy -- "Vxx.uh+=vmpy(Vu.ub,Rt.ub)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 1 0 0 t t t t t P P 1 u u u u u 0 0 0 x x x x x + +define pcodeop vmpyacc_WuhVubRub; + +:vmpy+= VddUH_0004,VuUB_0812,RtUB_1620 EndPacket is iclass=0x1 & op2127=0x4c & op13=0x1 & op0507=0x0 & vss5 & VddUH_0004 & VuUB_0812 & RtUB_1620 & $(END_PACKET) { + VddUH_0004 = vmpyacc_WuhVubRub(vss5,VuUB_0812,RtUB_1620); + build EndPacket; +} + +# (hvx,1) vmpy -- "Vxx.w+=vmpy(Vu.h,Rt.h)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 1 0 1 t t t t t P P 1 u u u u u 1 1 0 x x x x x + +define pcodeop vmpyacc_WwVhRh; + +:vmpy+= VddW_0004,VuH_0812,RtH_1620 EndPacket is iclass=0x1 & op2127=0x4d & op13=0x1 & op0507=0x6 & vss5 & VddW_0004 & VuH_0812 & RtH_1620 & $(END_PACKET) { + VddW_0004 = vmpyacc_WwVhRh(vss5,VuH_0812,RtH_1620); + build EndPacket; +} + +# (hvx,1) vmpy -- "Vdd.uh=vmpy(Vu.ub,Rt.ub)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 1 1 0 t t t t t P P 0 u u u u u 0 0 0 d d d d d + +define pcodeop vmpy_VubRub; + +:vmpy VddUH_0004,VuUB_0812,RtUB_1620 EndPacket is iclass=0x1 & op2127=0x4e & op13=0x0 & op0507=0x0 & VddUH_0004 & VuUB_0812 & RtUB_1620 & $(END_PACKET) { + VddUH_0004 = vmpy_VubRub(VuUB_0812,RtUB_1620); + build EndPacket; +} + +# (hvx,1) vmpy -- "Vdd.h=vmpy(Vu.b,Vv.b)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 0 0 0 v v v v v P P 0 u u u u u 1 0 0 d d d d d + +define pcodeop vmpy_VbVb; + +:vmpy VddH_0004,VuB_0812,VvB_1620 EndPacket is iclass=0x1 & op2127=0x60 & op13=0x0 & op0507=0x4 & VddH_0004 & VuB_0812 & VvB_1620 & $(END_PACKET) { + VddH_0004 = vmpy_VbVb(VuB_0812,VvB_1620); + build EndPacket; +} + +# (hvx,1) vmpy -- "Vdd.uh=vmpy(Vu.ub,Vv.ub)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 0 0 0 v v v v v P P 0 u u u u u 1 0 1 d d d d d + +define pcodeop vmpy_VubVub; + +:vmpy VddUH_0004,VuUB_0812,VvUB_1620 EndPacket is iclass=0x1 & op2127=0x60 & op13=0x0 & op0507=0x5 & VddUH_0004 & VuUB_0812 & VvUB_1620 & $(END_PACKET) { + VddUH_0004 = vmpy_VubVub(VuUB_0812,VvUB_1620); + build EndPacket; +} + +# (hvx,1) vmpy -- "Vdd.h=vmpy(Vu.ub,Vv.b)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 0 0 0 v v v v v P P 0 u u u u u 1 1 0 d d d d d + +define pcodeop vmpy_VubVb; + +:vmpy VddH_0004,VuUB_0812,VvB_1620 EndPacket is iclass=0x1 & op2127=0x60 & op13=0x0 & op0507=0x6 & VddH_0004 & VuUB_0812 & VvB_1620 & $(END_PACKET) { + VddH_0004 = vmpy_VubVb(VuUB_0812,VvB_1620); + build EndPacket; +} + +# (hvx,1) vmpy -- "Vxx.h+=vmpy(Vu.b,Vv.b)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 0 0 0 v v v v v P P 1 u u u u u 1 0 0 x x x x x + +define pcodeop vmpyacc_WhVbVb; + +:vmpy+= VddH_0004,VuB_0812,VvB_1620 EndPacket is iclass=0x1 & op2127=0x60 & op13=0x1 & op0507=0x4 & vss5 & VddH_0004 & VuB_0812 & VvB_1620 & $(END_PACKET) { + VddH_0004 = vmpyacc_WhVbVb(vss5,VuB_0812,VvB_1620); + build EndPacket; +} + +# (hvx,1) vmpy -- "Vxx.uh+=vmpy(Vu.ub,Vv.ub)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 0 0 0 v v v v v P P 1 u u u u u 1 0 1 x x x x x + +define pcodeop vmpyacc_WuhVubVub; + +:vmpy+= VddUH_0004,VuUB_0812,VvUB_1620 EndPacket is iclass=0x1 & op2127=0x60 & op13=0x1 & op0507=0x5 & vss5 & VddUH_0004 & VuUB_0812 & VvUB_1620 & $(END_PACKET) { + VddUH_0004 = vmpyacc_WuhVubVub(vss5,VuUB_0812,VvUB_1620); + build EndPacket; +} + +# (hvx,1) vmpy -- "Vxx.h+=vmpy(Vu.ub,Vv.b)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 0 0 0 v v v v v P P 1 u u u u u 1 1 0 x x x x x + +define pcodeop vmpyacc_WhVubVb; + +:vmpy+= VddH_0004,VuUB_0812,VvB_1620 EndPacket is iclass=0x1 & op2127=0x60 & op13=0x1 & op0507=0x6 & vss5 & VddH_0004 & VuUB_0812 & VvB_1620 & $(END_PACKET) { + VddH_0004 = vmpyacc_WhVubVb(vss5,VuUB_0812,VvB_1620); + build EndPacket; +} + +# (hvx,1) vmpy -- "Vdd.uw=vmpy(Vu.uh,Vv.uh)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 0 0 1 v v v v v P P 0 u u u u u 0 0 0 d d d d d + +define pcodeop vmpy_VuhVuh; + +:vmpy VddUW_0004,VuUH_0812,VvUH_1620 EndPacket is iclass=0x1 & op2127=0x61 & op13=0x0 & op0507=0x0 & VddUW_0004 & VuUH_0812 & VvUH_1620 & $(END_PACKET) { + VddUW_0004 = vmpy_VuhVuh(VuUH_0812,VvUH_1620); + build EndPacket; +} + +# (hvx,1) vmpy -- "Vxx.uw+=vmpy(Vu.uh,Vv.uh)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 0 0 1 v v v v v P P 1 u u u u u 0 0 0 x x x x x + +define pcodeop vmpyacc_WuwVuhVuh; + +:vmpy+= VddUW_0004,VuUH_0812,VvUH_1620 EndPacket is iclass=0x1 & op2127=0x61 & op13=0x1 & op0507=0x0 & vss5 & VddUW_0004 & VuUH_0812 & VvUH_1620 & $(END_PACKET) { + VddUW_0004 = vmpyacc_WuwVuhVuh(vss5,VuUH_0812,VvUH_1620); + build EndPacket; +} + +# (hvx,1) vmpy -- "Vdd.qf32=vmpy(Vu.qf16,Vv.hf)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 1 0 0 v v v v v P P 1 u u u u u 0 0 0 d d d d d + +define pcodeop Wqf32_vmpy_Vqf16Vhf; + +:vmpy VddQF32_0004,VuQF16_0812,VvHF_1620 EndPacket is iclass=0x1 & op2127=0x7c & op13=0x1 & op0507=0x0 & VddQF32_0004 & VuQF16_0812 & VvHF_1620 & $(END_PACKET) { + VddQF32_0004 = Wqf32_vmpy_Vqf16Vhf(VuQF16_0812,VvHF_1620); + build EndPacket; +} + +# (hvx,1) vmpy -- "Vd.qf16=vmpy(Vu.qf16,Vv.qf16)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 1 1 1 v v v v v P P 1 u u u u u 0 1 1 d d d d d + +define pcodeop vmpy_Vqf16Vqf16; + +:vmpy VdQF16_0004,VuQF16_0812,VvQF16_1620 EndPacket is iclass=0x1 & op2127=0x7f & op13=0x1 & op0507=0x3 & VdQF16_0004 & VuQF16_0812 & VvQF16_1620 & $(END_PACKET) { + VdQF16_0004 = vmpy_Vqf16Vqf16(VuQF16_0812,VvQF16_1620); + build EndPacket; +} + +# (hvx,1) vmpy -- "Vd.qf16=vmpy(Vu.hf,Vv.hf)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 1 1 1 v v v v v P P 1 u u u u u 1 0 0 d d d d d + +define pcodeop vmpy_VhfVhf; + +:vmpy VdQF16_0004,VuHF_0812,VvHF_1620 EndPacket is iclass=0x1 & op2127=0x7f & op13=0x1 & op0507=0x4 & VdQF16_0004 & VuHF_0812 & VvHF_1620 & $(END_PACKET) { + VdQF16_0004 = vmpy_VhfVhf(VuHF_0812,VvHF_1620); + build EndPacket; +} + +# (hvx,1) vmpy -- "Vd.qf16=vmpy(Vu.qf16,Vv.hf)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 1 1 1 v v v v v P P 1 u u u u u 1 0 1 d d d d d + +define pcodeop vmpy_Vqf16Vhf; + +:vmpy VdQF16_0004,VuQF16_0812,VvHF_1620 EndPacket is iclass=0x1 & op2127=0x7f & op13=0x1 & op0507=0x5 & VdQF16_0004 & VuQF16_0812 & VvHF_1620 & $(END_PACKET) { + VdQF16_0004 = vmpy_Vqf16Vhf(VuQF16_0812,VvHF_1620); + build EndPacket; +} + +# (hvx,1) vmpy -- "Vdd.qf32=vmpy(Vu.qf16,Vv.qf16)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 1 1 1 v v v v v P P 1 u u u u u 1 1 0 d d d d d + +define pcodeop Wqf32_vmpy_Vqf16Vqf16; + +:vmpy VddQF32_0004,VuQF16_0812,VvQF16_1620 EndPacket is iclass=0x1 & op2127=0x7f & op13=0x1 & op0507=0x6 & VddQF32_0004 & VuQF16_0812 & VvQF16_1620 & $(END_PACKET) { + VddQF32_0004 = Wqf32_vmpy_Vqf16Vqf16(VuQF16_0812,VvQF16_1620); + build EndPacket; +} + +# (hvx,1) vmpy -- "Vdd.qf32=vmpy(Vu.hf,Vv.hf)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 1 1 1 v v v v v P P 1 u u u u u 1 1 1 d d d d d + +define pcodeop Wqf32_vmpy_VhfVhf; + +:vmpy VddQF32_0004,VuHF_0812,VvHF_1620 EndPacket is iclass=0x1 & op2127=0x7f & op13=0x1 & op0507=0x7 & VddQF32_0004 & VuHF_0812 & VvHF_1620 & $(END_PACKET) { + VddQF32_0004 = Wqf32_vmpy_VhfVhf(VuHF_0812,VvHF_1620); + build EndPacket; +} + +# (hvx,1) vmpyi -- "Vd.h=vmpyi(Vu.h,Vv.h)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 0 0 1 v v v v v P P 0 u u u u u 1 0 0 d d d d d + +define pcodeop vmpyi_VhVh; + +:vmpyi VdH_0004,VuH_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x61 & op13=0x0 & op0507=0x4 & VdH_0004 & VuH_0812 & VvH_1620 & $(END_PACKET) { + VdH_0004 = vmpyi_VhVh(VuH_0812,VvH_1620); + build EndPacket; +} + +# (hvx,1) vmpyi -- "Vx.h+=vmpyi(Vu.h,Vv.h)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 0 0 1 v v v v v P P 1 u u u u u 1 0 0 x x x x x + +define pcodeop vmpyiacc_VhVhVh; + +:vmpyi+= VdH_0004,VuH_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x61 & op13=0x1 & op0507=0x4 & vs5 & VdH_0004 & VuH_0812 & VvH_1620 & $(END_PACKET) { + VdH_0004 = vmpyiacc_VhVhVh(vs5,VuH_0812,VvH_1620); + build EndPacket; +} + +# (hvx,1) vmpyie -- "Vx.w+=vmpyie(Vu.w,Vv.uh)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 0 0 1 v v v v v P P 1 u u u u u 1 0 1 x x x x x + +define pcodeop vmpyieacc_VwVwVuh; + +:vmpyie+= VdW_0004,VuW_0812,VvUH_1620 EndPacket is iclass=0x1 & op2127=0x61 & op13=0x1 & op0507=0x5 & vs5 & VdW_0004 & VuW_0812 & VvUH_1620 & $(END_PACKET) { + VdW_0004 = vmpyieacc_VwVwVuh(vs5,VuW_0812,VvUH_1620); + build EndPacket; +} + +# (hvx,1) vmpyie -- "Vx.w+=vmpyie(Vu.w,Vv.h)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 0 1 0 v v v v v P P 1 u u u u u 0 0 0 x x x x x + +define pcodeop vmpyieacc_VwVwVh; + +:vmpyie+= VdW_0004,VuW_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x62 & op13=0x1 & op0507=0x0 & vs5 & VdW_0004 & VuW_0812 & VvH_1620 & $(END_PACKET) { + VdW_0004 = vmpyieacc_VwVwVh(vs5,VuW_0812,VvH_1620); + build EndPacket; +} + +# (hvx,1) vmpyie -- "Vd.w=vmpyie(Vu.w,Vv.uh)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 1 1 0 v v v v v P P 0 u u u u u 0 0 0 d d d d d + +define pcodeop vmpyie_VwVuh; + +:vmpyie VdW_0004,VuW_0812,VvUH_1620 EndPacket is iclass=0x1 & op2127=0x7e & op13=0x0 & op0507=0x0 & VdW_0004 & VuW_0812 & VvUH_1620 & $(END_PACKET) { + VdW_0004 = vmpyie_VwVuh(VuW_0812,VvUH_1620); + build EndPacket; +} + +# (hvx,1) vmpyio -- "Vd.w=vmpyio(Vu.w,Vv.h)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 1 1 0 v v v v v P P 0 u u u u u 0 0 1 d d d d d + +define pcodeop vmpyio_VwVh; + +:vmpyio VdW_0004,VuW_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x7e & op13=0x0 & op0507=0x1 & VdW_0004 & VuW_0812 & VvH_1620 & $(END_PACKET) { + VdW_0004 = vmpyio_VwVh(VuW_0812,VvH_1620); + build EndPacket; +} + +# (hvx,1) vmpyi -- "Vx.w+=vmpyi(Vu.w,Rt.h)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 0 1 0 t t t t t P P 1 u u u u u 0 1 1 x x x x x + +define pcodeop vmpyiacc_VwVwRh; + +:vmpyi+= VdW_0004,VuW_0812,RtH_1620 EndPacket is iclass=0x1 & op2127=0x4a & op13=0x1 & op0507=0x3 & vs5 & VdW_0004 & VuW_0812 & RtH_1620 & $(END_PACKET) { + VdW_0004 = vmpyiacc_VwVwRh(vs5,VuW_0812,RtH_1620); + build EndPacket; +} + +# (hvx,1) vmpyi -- "Vd.w=vmpyi(Vu.w,Rt.h)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 1 0 0 t t t t t P P 0 u u u u u 1 1 1 d d d d d + +define pcodeop vmpyi_VwRh; + +:vmpyi VdW_0004,VuW_0812,RtH_1620 EndPacket is iclass=0x1 & op2127=0x4c & op13=0x0 & op0507=0x7 & VdW_0004 & VuW_0812 & RtH_1620 & $(END_PACKET) { + VdW_0004 = vmpyi_VwRh(VuW_0812,RtH_1620); + build EndPacket; +} + +# (hvx,1) vmpy -- "Vd.qf32=vmpy(Vu.qf32,Vv.qf32)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 1 1 1 v v v v v P P 1 u u u u u 0 0 0 d d d d d + +define pcodeop vmpy_Vqf32Vqf32; + +:vmpy VdQF32_0004,VuQF32_0812,VvQF32_1620 EndPacket is iclass=0x1 & op2127=0x7f & op13=0x1 & op0507=0x0 & VdQF32_0004 & VuQF32_0812 & VvQF32_1620 & $(END_PACKET) { + VdQF32_0004 = vmpy_Vqf32Vqf32(VuQF32_0812,VvQF32_1620); + build EndPacket; +} + +# (hvx,1) vmpy -- "Vd.qf32=vmpy(Vu.sf,Vv.sf)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 1 1 1 v v v v v P P 1 u u u u u 0 0 1 d d d d d + +define pcodeop vmpy_VsfVsf; + +:vmpy VdQF32_0004,VuSF_0812,VvSF_1620 EndPacket is iclass=0x1 & op2127=0x7f & op13=0x1 & op0507=0x1 & VdQF32_0004 & VuSF_0812 & VvSF_1620 & $(END_PACKET) { + VdQF32_0004 = vmpy_VsfVsf(VuSF_0812,VvSF_1620); + build EndPacket; +} + +# (hvx,1) vmpyo -- "Vxx+=vmpyo(Vu.w,Vv.h)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 0 0 1 v v v v v P P 1 u u u u u 0 1 1 x x x x x + +define pcodeop vmpyoacc_WVwVh; + +:vmpyo+= Vdd5,VuW_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x61 & op13=0x1 & op0507=0x3 & vss5 & Vdd5 & VuW_0812 & VvH_1620 & $(END_PACKET) { + Vdd5 = vmpyoacc_WVwVh(vss5,VuW_0812,VvH_1620); + build EndPacket; +} + +# (hvx,1) vmpyo -- "Vx.w+=vmpyo(Vu.w,Vv.h):<<1:sat:shift" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 0 0 1 v v v v v P P 1 u u u u u 1 1 0 x x x x x + +define pcodeop vmpyoacc_VwVwVh_s1_sat_shift; + +:vmpyo+=^":<<1:sat:shift" VdW_0004,VuW_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x61 & op13=0x1 & op0507=0x6 & vs5 & VdW_0004 & VuW_0812 & VvH_1620 & $(END_PACKET) { + VdW_0004 = vmpyoacc_VwVwVh_s1_sat_shift(vs5,VuW_0812,VvH_1620); + build EndPacket; +} + +# (hvx,1) vmpyo -- "Vx.w+=vmpyo(Vu.w,Vv.h):<<1:rnd:sat:shift" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 0 0 1 v v v v v P P 1 u u u u u 1 1 1 x x x x x + +define pcodeop vmpyoacc_VwVwVh_s1_rnd_sat_shift; + +:vmpyo+=^":<<1:rnd:sat:shift" VdW_0004,VuW_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x61 & op13=0x1 & op0507=0x7 & vs5 & VdW_0004 & VuW_0812 & VvH_1620 & $(END_PACKET) { + VdW_0004 = vmpyoacc_VwVwVh_s1_rnd_sat_shift(vs5,VuW_0812,VvH_1620); + build EndPacket; +} + +# (hvx,1) vmpye -- "Vdd=vmpye(Vu.w,Vv.uh)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 1 0 1 v v v v v P P 0 u u u u u 1 1 0 d d d d d + +define pcodeop W_vmpye_VwVuh; + +:vmpye Vdd5,VuW_0812,VvUH_1620 EndPacket is iclass=0x1 & op2127=0x75 & op13=0x0 & op0507=0x6 & Vdd5 & VuW_0812 & VvUH_1620 & $(END_PACKET) { + Vdd5 = W_vmpye_VwVuh(VuW_0812,VvUH_1620); + build EndPacket; +} + +# (hvx,1) vmpyo -- "Vd.w=vmpyo(Vu.w,Vv.h):<<1:rnd:sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 0 1 0 v v v v v P P 0 u u u u u 0 0 0 d d d d d + +define pcodeop vmpyo_VwVh_s1_rnd_sat; + +:vmpyo^":<<1:rnd:sat" VdW_0004,VuW_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x7a & op13=0x0 & op0507=0x0 & VdW_0004 & VuW_0812 & VvH_1620 & $(END_PACKET) { + VdW_0004 = vmpyo_VwVh_s1_rnd_sat(VuW_0812,VvH_1620); + build EndPacket; +} + +# (hvx,1) vmpye -- "Vd.w=vmpye(Vu.w,Vv.uh)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 1 1 1 v v v v v P P 0 u u u u u 1 0 1 d d d d d + +define pcodeop vmpye_VwVuh; + +:vmpye VdW_0004,VuW_0812,VvUH_1620 EndPacket is iclass=0x1 & op2127=0x7f & op13=0x0 & op0507=0x5 & VdW_0004 & VuW_0812 & VvUH_1620 & $(END_PACKET) { + VdW_0004 = vmpye_VwVuh(VuW_0812,VvUH_1620); + build EndPacket; +} + +# (hvx,1) vmpyo -- "Vd.w=vmpyo(Vu.w,Vv.h):<<1:sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 1 1 1 v v v v v P P 0 u u u u u 1 1 1 d d d d d + +define pcodeop vmpyo_VwVh_s1_sat; + +:vmpyo^":<<1:sat" VdW_0004,VuW_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x7f & op13=0x0 & op0507=0x7 & VdW_0004 & VuW_0812 & VvH_1620 & $(END_PACKET) { + VdW_0004 = vmpyo_VwVh_s1_sat(VuW_0812,VvH_1620); + build EndPacket; +} + +# (hvx,1) vrmpy -- "Vdd.w=vrmpy(Vuu.ub,Rt.b,#u1)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 0 1 0 t t t t t P P 0 u u u u u 1 0 i d d d d d + +define pcodeop vrmpy_WubRbI; + +:vrmpy VddW_0004,VuuUB_0812,RtB_1620,Uimm1_05 EndPacket is iclass=0x1 & op2127=0x4a & op13=0x0 & op0607=0x2 & VddW_0004 & VuuUB_0812 & RtB_1620 & Uimm1_05 & $(END_PACKET) { + VddW_0004 = vrmpy_WubRbI(VuuUB_0812,RtB_1620,Uimm1_05); + build EndPacket; +} + +# (hvx,1) vrmpy -- "Vxx.w+=vrmpy(Vuu.ub,Rt.b,#u1)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 0 1 0 t t t t t P P 1 u u u u u 1 0 i x x x x x + +define pcodeop vrmpyacc_WwWubRbI; + +:vrmpy+= VddW_0004,VuuUB_0812,RtB_1620,Uimm1_05 EndPacket is iclass=0x1 & op2127=0x4a & op13=0x1 & op0607=0x2 & vss5 & VddW_0004 & VuuUB_0812 & RtB_1620 & Uimm1_05 & $(END_PACKET) { + VddW_0004 = vrmpyacc_WwWubRbI(vss5,VuuUB_0812,RtB_1620,Uimm1_05); + build EndPacket; +} + +# (hvx,1) vrmpy -- "Vxx.uw+=vrmpy(Vuu.ub,Rt.ub,#u1)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 0 1 1 t t t t t P P 1 u u u u u 1 1 i x x x x x + +define pcodeop vrmpyacc_WuwWubRubI; + +:vrmpy+= VddUW_0004,VuuUB_0812,RtUB_1620,Uimm1_05 EndPacket is iclass=0x1 & op2127=0x4b & op13=0x1 & op0607=0x3 & vss5 & VddUW_0004 & VuuUB_0812 & RtUB_1620 & Uimm1_05 & $(END_PACKET) { + VddUW_0004 = vrmpyacc_WuwWubRubI(vss5,VuuUB_0812,RtUB_1620,Uimm1_05); + build EndPacket; +} + +# (hvx,1) vrmpy -- "Vdd.uw=vrmpy(Vuu.ub,Rt.ub,#u1)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 1 0 1 t t t t t P P 0 u u u u u 1 1 i d d d d d + +define pcodeop vrmpy_WubRubI; + +:vrmpy VddUW_0004,VuuUB_0812,RtUB_1620,Uimm1_05 EndPacket is iclass=0x1 & op2127=0x4d & op13=0x0 & op0607=0x3 & VddUW_0004 & VuuUB_0812 & RtUB_1620 & Uimm1_05 & $(END_PACKET) { + VddUW_0004 = vrmpy_WubRubI(VuuUB_0812,RtUB_1620,Uimm1_05); + build EndPacket; +} + +# (hvx,1) vrmpy -- "Vx.uw+=vrmpy(Vu.ub,Vv.ub)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 0 0 0 v v v v v P P 1 u u u u u 0 0 0 x x x x x + +define pcodeop vrmpyacc_VuwVubVub; + +:vrmpy+= VdUW_0004,VuUB_0812,VvUB_1620 EndPacket is iclass=0x1 & op2127=0x60 & op13=0x1 & op0507=0x0 & vs5 & VdUW_0004 & VuUB_0812 & VvUB_1620 & $(END_PACKET) { + VdUW_0004 = vrmpyacc_VuwVubVub(vs5,VuUB_0812,VvUB_1620); + build EndPacket; +} + +# (hvx,1) vrmpy -- "Vx.w+=vrmpy(Vu.b,Vv.b)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 0 0 0 v v v v v P P 1 u u u u u 0 0 1 x x x x x + +define pcodeop vrmpyacc_VwVbVb; + +:vrmpy+= VdW_0004,VuB_0812,VvB_1620 EndPacket is iclass=0x1 & op2127=0x60 & op13=0x1 & op0507=0x1 & vs5 & VdW_0004 & VuB_0812 & VvB_1620 & $(END_PACKET) { + VdW_0004 = vrmpyacc_VwVbVb(vs5,VuB_0812,VvB_1620); + build EndPacket; +} + +# (hvx,1) vrmpy -- "Vx.w+=vrmpy(Vu.ub,Vv.b)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 0 0 0 v v v v v P P 1 u u u u u 0 1 0 x x x x x + +define pcodeop vrmpyacc_VwVubVb; + +:vrmpy+= VdW_0004,VuUB_0812,VvB_1620 EndPacket is iclass=0x1 & op2127=0x60 & op13=0x1 & op0507=0x2 & vs5 & VdW_0004 & VuUB_0812 & VvB_1620 & $(END_PACKET) { + VdW_0004 = vrmpyacc_VwVubVb(vs5,VuUB_0812,VvB_1620); + build EndPacket; +} + +# (hvx,1) vtmpy -- "Vdd.h=vtmpy(Vuu.b,Rt.b)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 0 0 0 t t t t t P P 0 u u u u u 0 0 0 d d d d d + +define pcodeop vtmpy_WbRb; + +:vtmpy VddH_0004,VuuB_0812,RtB_1620 EndPacket is iclass=0x1 & op2127=0x48 & op13=0x0 & op0507=0x0 & VddH_0004 & VuuB_0812 & RtB_1620 & $(END_PACKET) { + VddH_0004 = vtmpy_WbRb(VuuB_0812,RtB_1620); + build EndPacket; +} + +# (hvx,1) vtmpy -- "Vdd.h=vtmpy(Vuu.ub,Rt.b)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 0 0 0 t t t t t P P 0 u u u u u 0 0 1 d d d d d + +define pcodeop vtmpy_WubRb; + +:vtmpy VddH_0004,VuuUB_0812,RtB_1620 EndPacket is iclass=0x1 & op2127=0x48 & op13=0x0 & op0507=0x1 & VddH_0004 & VuuUB_0812 & RtB_1620 & $(END_PACKET) { + VddH_0004 = vtmpy_WubRb(VuuUB_0812,RtB_1620); + build EndPacket; +} + +# (hvx,1) vtmpy -- "Vxx.h+=vtmpy(Vuu.b,Rt.b)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 0 0 0 t t t t t P P 1 u u u u u 0 0 0 x x x x x + +define pcodeop vtmpyacc_WhWbRb; + +:vtmpy+= VddH_0004,VuuB_0812,RtB_1620 EndPacket is iclass=0x1 & op2127=0x48 & op13=0x1 & op0507=0x0 & vss5 & VddH_0004 & VuuB_0812 & RtB_1620 & $(END_PACKET) { + VddH_0004 = vtmpyacc_WhWbRb(vss5,VuuB_0812,RtB_1620); + build EndPacket; +} + +# (hvx,1) vtmpy -- "Vxx.h+=vtmpy(Vuu.ub,Rt.b)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 0 0 0 t t t t t P P 1 u u u u u 0 0 1 x x x x x + +define pcodeop vtmpyacc_WhWubRb; + +:vtmpy+= VddH_0004,VuuUB_0812,RtB_1620 EndPacket is iclass=0x1 & op2127=0x48 & op13=0x1 & op0507=0x1 & vss5 & VddH_0004 & VuuUB_0812 & RtB_1620 & $(END_PACKET) { + VddH_0004 = vtmpyacc_WhWubRb(vss5,VuuUB_0812,RtB_1620); + build EndPacket; +} + +# (hvx,1) vtmpy -- "Vxx.w+=vtmpy(Vuu.h,Rt.b)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 0 0 0 t t t t t P P 1 u u u u u 0 1 0 x x x x x + +define pcodeop vtmpyacc_WwWhRb; + +:vtmpy+= VddW_0004,VuuH_0812,RtB_1620 EndPacket is iclass=0x1 & op2127=0x48 & op13=0x1 & op0507=0x2 & vss5 & VddW_0004 & VuuH_0812 & RtB_1620 & $(END_PACKET) { + VddW_0004 = vtmpyacc_WwWhRb(vss5,VuuH_0812,RtB_1620); + build EndPacket; +} + +# (hvx,1) vtmpy -- "Vdd.w=vtmpy(Vuu.h,Rt.b)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 1 0 1 t t t t t P P 0 u u u u u 1 0 0 d d d d d + +define pcodeop vtmpy_WhRb; + +:vtmpy VddW_0004,VuuH_0812,RtB_1620 EndPacket is iclass=0x1 & op2127=0x4d & op13=0x0 & op0507=0x4 & VddW_0004 & VuuH_0812 & RtB_1620 & $(END_PACKET) { + VddW_0004 = vtmpy_WhRb(VuuH_0812,RtB_1620); + build EndPacket; +} + +# (hvx,1) vdsad -- "Vdd.uw=vdsad(Vuu.uh,Rt.uh)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 0 0 0 t t t t t P P 0 u u u u u 1 0 1 d d d d d + +define pcodeop vdsad_WuhRuh; + +:vdsad VddUW_0004,VuuUH_0812,RtUH_1620 EndPacket is iclass=0x1 & op2127=0x48 & op13=0x0 & op0507=0x5 & VddUW_0004 & VuuUH_0812 & RtUH_1620 & $(END_PACKET) { + VddUW_0004 = vdsad_WuhRuh(VuuUH_0812,RtUH_1620); + build EndPacket; +} + +# (hvx,1) vdsad -- "Vxx.uw+=vdsad(Vuu.uh,Rt.uh)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 0 1 1 t t t t t P P 1 u u u u u 0 0 0 x x x x x + +define pcodeop vdsadacc_WuwWuhRuh; + +:vdsad+= VddUW_0004,VuuUH_0812,RtUH_1620 EndPacket is iclass=0x1 & op2127=0x4b & op13=0x1 & op0507=0x0 & vss5 & VddUW_0004 & VuuUH_0812 & RtUH_1620 & $(END_PACKET) { + VddUW_0004 = vdsadacc_WuwWuhRuh(vss5,VuuUH_0812,RtUH_1620); + build EndPacket; +} + +# (hvx,1) vrsad -- "Vdd.uw=vrsad(Vuu.ub,Rt.ub,#u1)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 0 1 0 t t t t t P P 0 u u u u u 1 1 i d d d d d + +define pcodeop vrsad_WubRubI; + +:vrsad VddUW_0004,VuuUB_0812,RtUB_1620,Uimm1_05 EndPacket is iclass=0x1 & op2127=0x4a & op13=0x0 & op0607=0x3 & VddUW_0004 & VuuUB_0812 & RtUB_1620 & Uimm1_05 & $(END_PACKET) { + VddUW_0004 = vrsad_WubRubI(VuuUB_0812,RtUB_1620,Uimm1_05); + build EndPacket; +} + +# (hvx,1) vrsad -- "Vxx.uw+=vrsad(Vuu.ub,Rt.ub,#u1)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 0 1 0 t t t t t P P 1 u u u u u 1 1 i x x x x x + +define pcodeop vrsadacc_WuwWubRubI; + +:vrsad+= VddUW_0004,VuuUB_0812,RtUB_1620,Uimm1_05 EndPacket is iclass=0x1 & op2127=0x4a & op13=0x1 & op0607=0x3 & vss5 & VddUW_0004 & VuuUB_0812 & RtUB_1620 & Uimm1_05 & $(END_PACKET) { + VddUW_0004 = vrsadacc_WuwWubRubI(vss5,VuuUB_0812,RtUB_1620,Uimm1_05); + build EndPacket; +} + +# (hvx,1) vdmpy -- "Vd.w=vdmpy(Vu.h,Rt.b)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 0 0 0 t t t t t P P 0 u u u u u 0 1 0 d d d d d + +define pcodeop vdmpy_VhRb; + +:vdmpy VdW_0004,VuH_0812,RtB_1620 EndPacket is iclass=0x1 & op2127=0x48 & op13=0x0 & op0507=0x2 & VdW_0004 & VuH_0812 & RtB_1620 & $(END_PACKET) { + VdW_0004 = vdmpy_VhRb(VuH_0812,RtB_1620); + build EndPacket; +} + +# (hvx,1) vdmpy -- "Vd.h=vdmpy(Vu.ub,Rt.b)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 0 0 0 t t t t t P P 0 u u u u u 1 1 0 d d d d d + +define pcodeop vdmpy_VubRb; + +:vdmpy VdH_0004,VuUB_0812,RtB_1620 EndPacket is iclass=0x1 & op2127=0x48 & op13=0x0 & op0507=0x6 & VdH_0004 & VuUB_0812 & RtB_1620 & $(END_PACKET) { + VdH_0004 = vdmpy_VubRb(VuUB_0812,RtB_1620); + build EndPacket; +} + +# (hvx,1) vdmpy -- "Vx.w+=vdmpy(Vu.h,Rt.b)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 0 0 0 t t t t t P P 1 u u u u u 0 1 1 x x x x x + +define pcodeop vdmpyacc_VwVhRb; + +:vdmpy+= VdW_0004,VuH_0812,RtB_1620 EndPacket is iclass=0x1 & op2127=0x48 & op13=0x1 & op0507=0x3 & vs5 & VdW_0004 & VuH_0812 & RtB_1620 & $(END_PACKET) { + VdW_0004 = vdmpyacc_VwVhRb(vs5,VuH_0812,RtB_1620); + build EndPacket; +} + +# (hvx,1) vdmpy -- "Vx.h+=vdmpy(Vu.ub,Rt.b)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 0 0 0 t t t t t P P 1 u u u u u 1 1 0 x x x x x + +define pcodeop vdmpyacc_VhVubRb; + +:vdmpy+= VdH_0004,VuUB_0812,RtB_1620 EndPacket is iclass=0x1 & op2127=0x48 & op13=0x1 & op0507=0x6 & vs5 & VdH_0004 & VuUB_0812 & RtB_1620 & $(END_PACKET) { + VdH_0004 = vdmpyacc_VhVubRb(vs5,VuUB_0812,RtB_1620); + build EndPacket; +} + +# (hvx,1) vdmpy -- "Vd.w=vdmpy(Vu.h,Rt.uh):sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 0 0 1 t t t t t P P 0 u u u u u 0 0 0 d d d d d + +define pcodeop vdmpy_VhRuh_sat; + +:vdmpy^":sat" VdW_0004,VuH_0812,RtUH_1620 EndPacket is iclass=0x1 & op2127=0x49 & op13=0x0 & op0507=0x0 & VdW_0004 & VuH_0812 & RtUH_1620 & $(END_PACKET) { + VdW_0004 = vdmpy_VhRuh_sat(VuH_0812,RtUH_1620); + build EndPacket; +} + +# (hvx,1) vdmpy -- "Vd.w=vdmpy(Vu.h,Rt.h):sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 0 0 1 t t t t t P P 0 u u u u u 0 1 0 d d d d d + +define pcodeop vdmpy_VhRh_sat; + +:vdmpy^":sat" VdW_0004,VuH_0812,RtH_1620 EndPacket is iclass=0x1 & op2127=0x49 & op13=0x0 & op0507=0x2 & VdW_0004 & VuH_0812 & RtH_1620 & $(END_PACKET) { + VdW_0004 = vdmpy_VhRh_sat(VuH_0812,RtH_1620); + build EndPacket; +} + +# (hvx,1) vdmpy -- "Vx.w+=vdmpy(Vu.h,Rt.uh):sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 0 0 1 t t t t t P P 1 u u u u u 0 0 0 x x x x x + +define pcodeop vdmpyacc_VwVhRuh_sat; + +:vdmpy+=^":sat" VdW_0004,VuH_0812,RtUH_1620 EndPacket is iclass=0x1 & op2127=0x49 & op13=0x1 & op0507=0x0 & vs5 & VdW_0004 & VuH_0812 & RtUH_1620 & $(END_PACKET) { + VdW_0004 = vdmpyacc_VwVhRuh_sat(vs5,VuH_0812,RtUH_1620); + build EndPacket; +} + +# (hvx,1) vdmpy -- "Vx.w+=vdmpy(Vu.h,Rt.h):sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 0 0 1 t t t t t P P 1 u u u u u 0 1 1 x x x x x + +define pcodeop vdmpyacc_VwVhRh_sat; + +:vdmpy+=^":sat" VdW_0004,VuH_0812,RtH_1620 EndPacket is iclass=0x1 & op2127=0x49 & op13=0x1 & op0507=0x3 & vs5 & VdW_0004 & VuH_0812 & RtH_1620 & $(END_PACKET) { + VdW_0004 = vdmpyacc_VwVhRh_sat(vs5,VuH_0812,RtH_1620); + build EndPacket; +} + +# (hvx,1) vdmpy -- "Vd.w=vdmpy(Vu.h,Vv.h):sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 0 0 0 v v v v v P P 0 u u u u u 0 1 1 d d d d d + +define pcodeop vdmpy_VhVh_sat; + +:vdmpy^":sat" VdW_0004,VuH_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x60 & op13=0x0 & op0507=0x3 & VdW_0004 & VuH_0812 & VvH_1620 & $(END_PACKET) { + VdW_0004 = vdmpy_VhVh_sat(VuH_0812,VvH_1620); + build EndPacket; +} + +# (hvx,1) vmpy -- "Vd.h=vmpy(Vu.h,Rt.h):<<1:sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 0 1 0 t t t t t P P 0 u u u u u 0 0 1 d d d d d + +define pcodeop vmpy_VhRh_s1_sat; + +:vmpy^":<<1:sat" VdH_0004,VuH_0812,RtH_1620 EndPacket is iclass=0x1 & op2127=0x4a & op13=0x0 & op0507=0x1 & VdH_0004 & VuH_0812 & RtH_1620 & $(END_PACKET) { + VdH_0004 = vmpy_VhRh_s1_sat(VuH_0812,RtH_1620); + build EndPacket; +} + +# (hvx,1) vmpy -- "Vd.h=vmpy(Vu.h,Rt.h):<<1:rnd:sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 0 1 0 t t t t t P P 0 u u u u u 0 1 0 d d d d d + +define pcodeop vmpy_VhRh_s1_rnd_sat; + +:vmpy^":<<1:rnd:sat" VdH_0004,VuH_0812,RtH_1620 EndPacket is iclass=0x1 & op2127=0x4a & op13=0x0 & op0507=0x2 & VdH_0004 & VuH_0812 & RtH_1620 & $(END_PACKET) { + VdH_0004 = vmpy_VhRh_s1_rnd_sat(VuH_0812,RtH_1620); + build EndPacket; +} + +# (hvx,1) vmpy -- "Vd.uh=vmpy(Vu.uh,Vv.uh):>>16" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 1 1 0 v v v v v P P 1 u u u u u 1 1 1 d d d d d + +define pcodeop vmpy_VuhVuh_rs16; + +:vmpy^":>>16" VdUH_0004,VuUH_0812,VvUH_1620 EndPacket is iclass=0x1 & op2127=0x7e & op13=0x1 & op0507=0x7 & VdUH_0004 & VuUH_0812 & VvUH_1620 & $(END_PACKET) { + VdUH_0004 = vmpy_VuhVuh_rs16(VuUH_0812,VvUH_1620); + build EndPacket; +} + +# (hvx,1) vmpyieo -- "Vd.w=vmpyieo(Vu.h,Vv.h)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 0 1 1 v v v v v P P 0 u u u u u 0 0 0 d d d d d + +define pcodeop vmpyieo_VhVh; + +:vmpyieo VdW_0004,VuH_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x7b & op13=0x0 & op0507=0x0 & VdW_0004 & VuH_0812 & VvH_1620 & $(END_PACKET) { + VdW_0004 = vmpyieo_VhVh(VuH_0812,VvH_1620); + build EndPacket; +} + +# (hvx,1) vmpyi -- "Vx.w+=vmpyi(Vu.w,Rt.b)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 0 1 0 t t t t t P P 1 u u u u u 0 1 0 x x x x x + +define pcodeop vmpyiacc_VwVwRb; + +:vmpyi+= VdW_0004,VuW_0812,RtB_1620 EndPacket is iclass=0x1 & op2127=0x4a & op13=0x1 & op0507=0x2 & vs5 & VdW_0004 & VuW_0812 & RtB_1620 & $(END_PACKET) { + VdW_0004 = vmpyiacc_VwVwRb(vs5,VuW_0812,RtB_1620); + build EndPacket; +} + +# (hvx,1) vmpyi -- "Vd.h=vmpyi(Vu.h,Rt.b)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 0 1 1 t t t t t P P 0 u u u u u 0 0 0 d d d d d + +define pcodeop vmpyi_VhRb; + +:vmpyi VdH_0004,VuH_0812,RtB_1620 EndPacket is iclass=0x1 & op2127=0x4b & op13=0x0 & op0507=0x0 & VdH_0004 & VuH_0812 & RtB_1620 & $(END_PACKET) { + VdH_0004 = vmpyi_VhRb(VuH_0812,RtB_1620); + build EndPacket; +} + +# (hvx,1) vmpyi -- "Vx.h+=vmpyi(Vu.h,Rt.b)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 0 1 1 t t t t t P P 1 u u u u u 0 0 1 x x x x x + +define pcodeop vmpyiacc_VhVhRb; + +:vmpyi+= VdH_0004,VuH_0812,RtB_1620 EndPacket is iclass=0x1 & op2127=0x4b & op13=0x1 & op0507=0x1 & vs5 & VdH_0004 & VuH_0812 & RtB_1620 & $(END_PACKET) { + VdH_0004 = vmpyiacc_VhVhRb(vs5,VuH_0812,RtB_1620); + build EndPacket; +} + +# (hvx,1) vmpyi -- "Vd.w=vmpyi(Vu.w,Rt.ub)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 1 0 0 t t t t t P P 0 u u u u u 1 1 0 d d d d d + +define pcodeop vmpyi_VwRub; + +:vmpyi VdW_0004,VuW_0812,RtUB_1620 EndPacket is iclass=0x1 & op2127=0x4c & op13=0x0 & op0507=0x6 & VdW_0004 & VuW_0812 & RtUB_1620 & $(END_PACKET) { + VdW_0004 = vmpyi_VwRub(VuW_0812,RtUB_1620); + build EndPacket; +} + +# (hvx,1) vmpyi -- "Vx.w+=vmpyi(Vu.w,Rt.ub)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 1 0 0 t t t t t P P 1 u u u u u 0 0 1 x x x x x + +define pcodeop vmpyiacc_VwVwRub; + +:vmpyi+= VdW_0004,VuW_0812,RtUB_1620 EndPacket is iclass=0x1 & op2127=0x4c & op13=0x1 & op0507=0x1 & vs5 & VdW_0004 & VuW_0812 & RtUB_1620 & $(END_PACKET) { + VdW_0004 = vmpyiacc_VwVwRub(vs5,VuW_0812,RtUB_1620); + build EndPacket; +} + +# (hvx,1) vmpyi -- "Vd.w=vmpyi(Vu.w,Rt.b)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 1 0 1 t t t t t P P 0 u u u u u 0 0 0 d d d d d + +define pcodeop vmpyi_VwRb; + +:vmpyi VdW_0004,VuW_0812,RtB_1620 EndPacket is iclass=0x1 & op2127=0x4d & op13=0x0 & op0507=0x0 & VdW_0004 & VuW_0812 & RtB_1620 & $(END_PACKET) { + VdW_0004 = vmpyi_VwRb(VuW_0812,RtB_1620); + build EndPacket; +} + +# (hvx,1) vmpye -- "Vd.uw=vmpye(Vu.uh,Rt.uh)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 0 1 1 t t t t t P P 0 u u u u u 0 1 0 d d d d d + +define pcodeop vmpye_VuhRuh; + +:vmpye VdUW_0004,VuUH_0812,RtUH_1620 EndPacket is iclass=0x1 & op2127=0x4b & op13=0x0 & op0507=0x2 & VdUW_0004 & VuUH_0812 & RtUH_1620 & $(END_PACKET) { + VdUW_0004 = vmpye_VuhRuh(VuUH_0812,RtUH_1620); + build EndPacket; +} + +# (hvx,1) vmpye -- "Vx.uw+=vmpye(Vu.uh,Rt.uh)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 1 0 0 t t t t t P P 1 u u u u u 0 1 1 x x x x x + +define pcodeop vmpyeacc_VuwVuhRuh; + +:vmpye+= VdUW_0004,VuUH_0812,RtUH_1620 EndPacket is iclass=0x1 & op2127=0x4c & op13=0x1 & op0507=0x3 & vs5 & VdUW_0004 & VuUH_0812 & RtUH_1620 & $(END_PACKET) { + VdUW_0004 = vmpyeacc_VuwVuhRuh(vs5,VuUH_0812,RtUH_1620); + build EndPacket; +} + +# (hvx,1) vrmpy -- "Vd.uw=vrmpy(Vu.ub,Rt.ub)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 0 0 0 t t t t t P P 0 u u u u u 0 1 1 d d d d d + +define pcodeop vrmpy_VubRub; + +:vrmpy VdUW_0004,VuUB_0812,RtUB_1620 EndPacket is iclass=0x1 & op2127=0x48 & op13=0x0 & op0507=0x3 & VdUW_0004 & VuUB_0812 & RtUB_1620 & $(END_PACKET) { + VdUW_0004 = vrmpy_VubRub(VuUB_0812,RtUB_1620); + build EndPacket; +} + +# (hvx,1) vrmpy -- "Vd.w=vrmpy(Vu.ub,Rt.b)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 0 0 0 t t t t t P P 0 u u u u u 1 0 0 d d d d d + +define pcodeop Vw_vrmpy_VubRb; + +:vrmpy VdW_0004,VuUB_0812,RtB_1620 EndPacket is iclass=0x1 & op2127=0x48 & op13=0x0 & op0507=0x4 & VdW_0004 & VuUB_0812 & RtB_1620 & $(END_PACKET) { + VdW_0004 = Vw_vrmpy_VubRb(VuUB_0812,RtB_1620); + build EndPacket; +} + +# (hvx,1) vrmpy -- "Vx.uw+=vrmpy(Vu.ub,Rt.ub)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 0 0 0 t t t t t P P 1 u u u u u 1 0 0 x x x x x + +define pcodeop vrmpyacc_VuwVubRub; + +:vrmpy+= VdUW_0004,VuUB_0812,RtUB_1620 EndPacket is iclass=0x1 & op2127=0x48 & op13=0x1 & op0507=0x4 & vs5 & VdUW_0004 & VuUB_0812 & RtUB_1620 & $(END_PACKET) { + VdUW_0004 = vrmpyacc_VuwVubRub(vs5,VuUB_0812,RtUB_1620); + build EndPacket; +} + +# (hvx,1) vrmpy -- "Vx.w+=vrmpy(Vu.ub,Rt.b)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 0 0 0 t t t t t P P 1 u u u u u 1 0 1 x x x x x + +define pcodeop vrmpyacc_VwVubRb; + +:vrmpy+= VdW_0004,VuUB_0812,RtB_1620 EndPacket is iclass=0x1 & op2127=0x48 & op13=0x1 & op0507=0x5 & vs5 & VdW_0004 & VuUB_0812 & RtB_1620 & $(END_PACKET) { + VdW_0004 = vrmpyacc_VwVubRb(vs5,VuUB_0812,RtB_1620); + build EndPacket; +} + +# (hvx,1) vrmpy -- "Vd.uw=vrmpy(Vu.ub,Vv.ub)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 0 0 0 v v v v v P P 0 u u u u u 0 0 0 d d d d d + +define pcodeop Vuw_vrmpy_VubVub; + +:vrmpy VdUW_0004,VuUB_0812,VvUB_1620 EndPacket is iclass=0x1 & op2127=0x60 & op13=0x0 & op0507=0x0 & VdUW_0004 & VuUB_0812 & VvUB_1620 & $(END_PACKET) { + VdUW_0004 = Vuw_vrmpy_VubVub(VuUB_0812,VvUB_1620); + build EndPacket; +} + +# (hvx,1) vrmpy -- "Vd.w=vrmpy(Vu.b,Vv.b)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 0 0 0 v v v v v P P 0 u u u u u 0 0 1 d d d d d + +define pcodeop Vw_vrmpy_VbVb; + +:vrmpy VdW_0004,VuB_0812,VvB_1620 EndPacket is iclass=0x1 & op2127=0x60 & op13=0x0 & op0507=0x1 & VdW_0004 & VuB_0812 & VvB_1620 & $(END_PACKET) { + VdW_0004 = Vw_vrmpy_VbVb(VuB_0812,VvB_1620); + build EndPacket; +} + +# (hvx,1) vrmpy -- "Vd.w=vrmpy(Vu.ub,Vv.b)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 0 0 0 v v v v v P P 0 u u u u u 0 1 0 d d d d d + +define pcodeop Vw_vrmpy_VubVb; + +:vrmpy VdW_0004,VuUB_0812,VvB_1620 EndPacket is iclass=0x1 & op2127=0x60 & op13=0x0 & op0507=0x2 & VdW_0004 & VuUB_0812 & VvB_1620 & $(END_PACKET) { + VdW_0004 = Vw_vrmpy_VubVb(VuUB_0812,VvB_1620); + build EndPacket; +} + +# +# NOTE: The vsplat instruction from V60 was removed in later versions +# + +# (hvx,1) vsplat -- "Vd=vsplat(Rt)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 1 0 1 t t t t t P P 0 - - - - 0 0 0 1 d d d d d + +define pcodeop V_vsplat_R; + +:vsplat Vd5,rx5 EndPacket is iclass=0x1 & op2127=0x4d & op13=0x0 & op0508=0x1 & Vd5 & rx5 & $(END_PACKET) { + Vd5 = V_vsplat_R(rx5); + build EndPacket; +} + +# (hvx,1) vsplat -- "Vd.h=vsplat(Rt)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 1 1 0 t t t t t P P 0 - - - - - 0 0 1 d d d d d + +define pcodeop Vh_vsplat_R; + +:vsplat VdH_0004,rx5 EndPacket is iclass=0x1 & op2127=0x4e & op13=0x0 & op0507=0x1 & VdH_0004 & rx5 & $(END_PACKET) { + VdH_0004 = Vh_vsplat_R(rx5); + build EndPacket; +} + +# (hvx,1) vsplat -- "Vd.b=vsplat(Rt)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 1 1 0 t t t t t P P 0 - - - - - 0 1 0 d d d d d + +define pcodeop Vb_vsplat_R; + +:vsplat VdB_0004,rx5 EndPacket is iclass=0x1 & op2127=0x4e & op13=0x0 & op0507=0x2 & VdB_0004 & rx5 & $(END_PACKET) { + VdB_0004 = Vb_vsplat_R(rx5); + build EndPacket; +} + +# (hvx,1) vand -- "Qx4|=vand(Vu,Rt)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 0 1 1 t t t t t P P 1 u u u u u 1 0 0 - - - x x + +define pcodeop Q_vandor_QVR; + +:vand|= Qd2,Vu_0812,rx5 EndPacket is iclass=0x1 & op2127=0x4b & op13=0x1 & op0507=0x4 & Qd2 & Vu_0812 & rx5 & $(END_PACKET) { + Qd2 = Q_vandor_QVR(Qd2,Vu_0812,rx5); + build EndPacket; +} + +# (hvx,1) vand -- "Qd4=vand(Vu,Rt)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 1 0 1 t t t t t P P 0 u u u u u 0 1 0 - 1 0 d d + +define pcodeop Q_vand_VR; + +:vand Qd2,Vu_0812,rx5 EndPacket is iclass=0x1 & op2127=0x4d & op13=0x0 & op0507=0x2 & op3=0x1 & op2=0x0 & Qd2 & Vu_0812 & rx5 & $(END_PACKET) { + Qd2 = Q_vand_VR(Vu_0812,rx5); + build EndPacket; +} + +# (hvx,1) vand -- "Vx|=vand(Qu4,Rt)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 0 1 1 t t t t t P P 1 - - 0 u u 0 1 1 x x x x x + +define pcodeop V_vandor_VQR; + +:vand|= Vd5,qv0809,rx5 EndPacket is iclass=0x1 & op2127=0x4b & op13=0x1 & op10=0x0 & op0507=0x3 & Vd5 & vs5 & qv0809 & rx5 & $(END_PACKET) { + Vd5 = V_vandor_VQR(vs5,qv0809,rx5); + build EndPacket; +} + +# (hvx,1) vand -- "Vx|=vand(!Qu4,Rt)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 0 1 1 t t t t t P P 1 - - 1 u u 0 1 1 x x x x x + +:vand|= Vd5,qv0809,rx5 EndPacket is iclass=0x1 & op2127=0x4b & op13=0x1 & op10=0x1 & op0507=0x3 & Vd5 & vs5 & qv0809 & rx5 & $(END_PACKET) { + Vd5 = V_vandor_VQR(vs5,~qv0809,rx5); + build EndPacket; +} + +# (hvx,1) vand -- "Vd=vand(Qu4,Rt)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 1 0 1 t t t t t P P 0 - - 0 u u 1 0 1 d d d d d + +define pcodeop V_vand_QR; + +:vand Vd5,qv0809,rx5 EndPacket is iclass=0x1 & op2127=0x4d & op13=0x0 & op10=0x0 & op0507=0x5 & Vd5 & qv0809 & rx5 & $(END_PACKET) { + Vd5 = V_vand_QR(qv0809,rx5); + build EndPacket; +} + +# (hvx,1) vand -- "Vd=vand(!Qu4,Rt)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 1 0 1 t t t t t P P 0 - - 1 u u 1 0 1 d d d d d + +:vand Vd5,qv0809,rx5 EndPacket is iclass=0x1 & op2127=0x4d & op13=0x0 & op10=0x1 & op0507=0x5 & Vd5 & qv0809 & rx5 & $(END_PACKET) { + Vd5 = V_vand_QR(~qv0809,rx5); + build EndPacket; +} + +# (hvx,1) vabsdiff -- "Vd.ub=vabsdiff(Vu.ub,Vv.ub)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 1 0 v v v v v P P 0 u u u u u 0 0 0 d d d d d + +define pcodeop Vub_vabsdiff_VubVub; + +:vabsdiff VdUB_0004,VuUB_0812,VvUB_1620 EndPacket is iclass=0x1 & op2127=0x66 & op13=0x0 & op0507=0x0 & VdUB_0004 & VuUB_0812 & VvUB_1620 & $(END_PACKET) { + VdUB_0004 = Vub_vabsdiff_VubVub(VuUB_0812,VvUB_1620); + build EndPacket; +} + +# (hvx,1) vabsdiff -- "Vd.uh=vabsdiff(Vu.h,Vv.h)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 1 0 v v v v v P P 0 u u u u u 0 0 1 d d d d d + +define pcodeop Vuh_vabsdiff_VhVh; + +:vabsdiff VdUH_0004,VuH_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x66 & op13=0x0 & op0507=0x1 & VdUH_0004 & VuH_0812 & VvH_1620 & $(END_PACKET) { + VdUH_0004 = Vuh_vabsdiff_VhVh(VuH_0812,VvH_1620); + build EndPacket; +} + +# (hvx,1) vabsdiff -- "Vd.uh=vabsdiff(Vu.uh,Vv.uh)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 1 0 v v v v v P P 0 u u u u u 0 1 0 d d d d d + +define pcodeop Vuh_vabsdiff_VuhVuh; + +:vabsdiff VdUH_0004,VuUH_0812,VvUH_1620 EndPacket is iclass=0x1 & op2127=0x66 & op13=0x0 & op0507=0x2 & VdUH_0004 & VuUH_0812 & VvUH_1620 & $(END_PACKET) { + VdUH_0004 = Vuh_vabsdiff_VuhVuh(VuUH_0812,VvUH_1620); + build EndPacket; +} + +# (hvx,1) vabsdiff -- "Vd.uw=vabsdiff(Vu.w,Vv.w)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 1 0 v v v v v P P 0 u u u u u 0 1 1 d d d d d + +define pcodeop Vuw_vabsdiff_VwVw; + +:vabsdiff VdUW_0004,VuW_0812,VvW_1620 EndPacket is iclass=0x1 & op2127=0x66 & op13=0x0 & op0507=0x3 & VdUW_0004 & VuW_0812 & VvW_1620 & $(END_PACKET) { + VdUW_0004 = Vuw_vabsdiff_VwVw(VuW_0812,VvW_1620); + build EndPacket; +} + +# (hvx,1) vinsert -- "Vx.w=vinsert(Rt)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 1 0 1 t t t t t P P 1 - - - - - 0 0 1 x x x x x + +define pcodeop vinsert_VwR; + +:vinsert VdW_0004,rx5 EndPacket is iclass=0x1 & op2127=0x4d & op13=0x1 & op0507=0x1 & vs5 & VdW_0004 & rx5 & $(END_PACKET) { + VdW_0004 = vinsert_VwR(vs5,rx5); + build EndPacket; +} + +# (hvx,1) vror -- "Vd=vror(Vu,Rt)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 0 1 1 t t t t t P P 0 u u u u u 0 0 1 d d d d d + +define pcodeop vror_VR; + +:vror Vd5,Vu_0812,rx5 EndPacket is iclass=0x1 & op2127=0x4b & op13=0x0 & op0507=0x1 & Vd5 & Vu_0812 & rx5 & $(END_PACKET) { + Vd5 = vror_VR(Vu_0812,rx5); + build EndPacket; +} + +# (hvx,1) valign -- "Vd=valign(Vu,Vv,Rt)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 1 1 v v v v v t t t P P 0 u u u u u 0 0 0 d d d d d + +define pcodeop valign_VVR; + +:valign Vd5,Vu_0812,Vz_1923,rt1618 EndPacket is iclass=0x1 & op2427=0xb & op13=0x0 & op0507=0x0 & Vd5 & Vu_0812 & Vz_1923 & rt1618 & $(END_PACKET) { + Vd5 = valign_VVR(Vu_0812,Vz_1923,rt1618); + build EndPacket; +} + +# (hvx,1) vlalign -- "Vd=vlalign(Vu,Vv,Rt)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 1 1 v v v v v t t t P P 0 u u u u u 0 0 1 d d d d d + +define pcodeop vlalign_VVR; + +:vlalign Vd5,Vu_0812,Vz_1923,rt1618 EndPacket is iclass=0x1 & op2427=0xb & op13=0x0 & op0507=0x1 & Vd5 & Vu_0812 & Vz_1923 & rt1618 & $(END_PACKET) { + Vd5 = vlalign_VVR(Vu_0812,Vz_1923,rt1618); + build EndPacket; +} + +# (hvx,1) valign -- "Vd=valign(Vu,Vv,#u3)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 0 0 1 v v v v v P P 1 u u u u u i i i d d d d d + +define pcodeop V_valign_VVI; + +:valign Vd5,Vu_0812,Vv_1620,Uimm8_0507 EndPacket is iclass=0x1 & op2127=0x71 & op13=0x1 & Vd5 & Vu_0812 & Vv_1620 & Uimm8_0507 & $(END_PACKET) { + Vd5 = V_valign_VVI(Vu_0812,Vv_1620,Uimm8_0507); + build EndPacket; +} + +# (hvx,1) vlalign -- "Vd=vlalign(Vu,Vv,#u3)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 0 1 1 v v v v v P P 1 u u u u u i i i d d d d d + +define pcodeop V_vlalign_VVI; + +:vlalign Vd5,Vu_0812,Vv_1620,Uimm8_0507 EndPacket is iclass=0x1 & op2127=0x73 & op13=0x1 & Vd5 & Vu_0812 & Vv_1620 & Uimm8_0507 & $(END_PACKET) { + Vd5 = V_vlalign_VVI(Vu_0812,Vv_1620,Uimm8_0507); + build EndPacket; +} + +# (hvx,1) vdelta -- "Vd=vdelta(Vu,Vv)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 0 0 1 v v v v v P P 0 u u u u u 0 0 1 d d d d d + +define pcodeop vdelta_VV; + +:vdelta Vd5,Vu_0812,Vv_1620 EndPacket is iclass=0x1 & op2127=0x79 & op13=0x0 & op0507=0x1 & Vd5 & Vu_0812 & Vv_1620 & $(END_PACKET) { + Vd5 = vdelta_VV(Vu_0812,Vv_1620); + build EndPacket; +} + +# (hvx,1) vrdelta -- "Vd=vrdelta(Vu,Vv)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 0 0 1 v v v v v P P 0 u u u u u 0 1 1 d d d d d + +define pcodeop vrdelta_VV; + +:vrdelta Vd5,Vu_0812,Vv_1620 EndPacket is iclass=0x1 & op2127=0x79 & op13=0x0 & op0507=0x3 & Vd5 & Vu_0812 & Vv_1620 & $(END_PACKET) { + Vd5 = vrdelta_VV(Vu_0812,Vv_1620); + build EndPacket; +} + +# (hvx,1) vdeal -- "Vd.h=vdeal(Vu.h)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 - - 0 - - - 0 0 P P 0 u u u u u 1 1 0 d d d d d + +define pcodeop vdeal_Vh; + +:vdeal VdH_0004,VuH_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op1617=0x0 & op13=0x0 & op0507=0x6 & VdH_0004 & VuH_0812 & $(END_PACKET) { + VdH_0004 = vdeal_Vh(VuH_0812); + build EndPacket; +} + +# (hvx,1) vdeal -- "Vd.b=vdeal(Vu.b)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 - - 0 - - - 0 0 P P 0 u u u u u 1 1 1 d d d d d + +define pcodeop vdeal_Vb; + +:vdeal VdB_0004,VuB_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op1617=0x0 & op13=0x0 & op0507=0x7 & VdB_0004 & VuB_0812 & $(END_PACKET) { + VdB_0004 = vdeal_Vb(VuB_0812); + build EndPacket; +} + +# (hvx,1) vshuff -- "Vd.h=vshuff(Vu.h)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 - - 0 - - - 0 1 P P 0 u u u u u 1 1 1 d d d d d + +define pcodeop vshuff_Vh; + +:vshuff VdH_0004,VuH_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op1617=0x1 & op13=0x0 & op0507=0x7 & VdH_0004 & VuH_0812 & $(END_PACKET) { + VdH_0004 = vshuff_Vh(VuH_0812); + build EndPacket; +} + +# (hvx,1) vshuff -- "Vd.b=vshuff(Vu.b)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 - - 0 - - - 1 0 P P 0 u u u u u 0 0 0 d d d d d + +define pcodeop vshuff_Vb; + +:vshuff VdB_0004,VuB_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op1617=0x2 & op13=0x0 & op0507=0x0 & VdB_0004 & VuB_0812 & $(END_PACKET) { + VdB_0004 = vshuff_Vb(VuB_0812); + build EndPacket; +} + +# (hvx,1) vdeale -- "Vd.b=vdeale(Vu.b,Vv.b)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 0 0 1 v v v v v P P 0 u u u u u 1 1 1 d d d d d + +define pcodeop vdeale_VbVb; + +:vdeale VdB_0004,VuB_0812,VvB_1620 EndPacket is iclass=0x1 & op2127=0x79 & op13=0x0 & op0507=0x7 & VdB_0004 & VuB_0812 & VvB_1620 & $(END_PACKET) { + VdB_0004 = vdeale_VbVb(VuB_0812,VvB_1620); + build EndPacket; +} + +# (hvx,1) vpacke -- "Vd.b=vpacke(Vu.h,Vv.h)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 1 1 0 v v v v v P P 0 u u u u u 0 1 0 d d d d d + +define pcodeop Vb_vpacke_VhVh; + +:vpacke VdB_0004,VuH_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x7e & op13=0x0 & op0507=0x2 & VdB_0004 & VuH_0812 & VvH_1620 & $(END_PACKET) { + VdB_0004 = Vb_vpacke_VhVh(VuH_0812,VvH_1620); + build EndPacket; +} + +# (hvx,1) vpacke -- "Vd.h=vpacke(Vu.w,Vv.w)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 1 1 0 v v v v v P P 0 u u u u u 0 1 1 d d d d d + +define pcodeop Vh_vpacke_VwVw; + +:vpacke VdH_0004,VuW_0812,VvW_1620 EndPacket is iclass=0x1 & op2127=0x7e & op13=0x0 & op0507=0x3 & VdH_0004 & VuW_0812 & VvW_1620 & $(END_PACKET) { + VdH_0004 = Vh_vpacke_VwVw(VuW_0812,VvW_1620); + build EndPacket; +} + +# (hvx,1) vpack -- "Vd.ub=vpack(Vu.h,Vv.h):sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 1 1 0 v v v v v P P 0 u u u u u 1 0 1 d d d d d + +define pcodeop Vb_vpack_VhVh_sat; + +:vpack^":sat" VdUB_0004,VuH_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x7e & op13=0x0 & op0507=0x5 & VdUB_0004 & VuH_0812 & VvH_1620 & $(END_PACKET) { + VdUB_0004 = Vb_vpack_VhVh_sat(VuH_0812,VvH_1620); + build EndPacket; +} + +# (hvx,1) vpack -- "Vd.b=vpack(Vu.h,Vv.h):sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 1 1 0 v v v v v P P 0 u u u u u 1 1 0 d d d d d + +define pcodeop Vb_vpacko_VhVh_sat; + +:vpack^":sat" VdB_0004,VuH_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x7e & op13=0x0 & op0507=0x6 & VdB_0004 & VuH_0812 & VvH_1620 & $(END_PACKET) { + VdB_0004 = Vb_vpacko_VhVh_sat(VuH_0812,VvH_1620); + build EndPacket; +} + +# (hvx,1) vpack -- "Vd.uh=vpack(Vu.w,Vv.w):sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 1 1 0 v v v v v P P 0 u u u u u 1 1 1 d d d d d + +define pcodeop Vuh_vpack_VwVw_sat; + +:vpack^":sat" VdUH_0004,VuW_0812,VvW_1620 EndPacket is iclass=0x1 & op2127=0x7e & op13=0x0 & op0507=0x7 & VdUH_0004 & VuW_0812 & VvW_1620 & $(END_PACKET) { + VdUH_0004 = Vuh_vpack_VwVw_sat(VuW_0812,VvW_1620); + build EndPacket; +} + +# (hvx,1) vpack -- "Vd.h=vpack(Vu.w,Vv.w):sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 1 1 1 v v v v v P P 0 u u u u u 0 0 0 d d d d d + +define pcodeop Vh_vpack_VwVw_sat; + +:vpack^":sat" VdH_0004,VuW_0812,VvW_1620 EndPacket is iclass=0x1 & op2127=0x7f & op13=0x0 & op0507=0x0 & VdH_0004 & VuW_0812 & VvW_1620 & $(END_PACKET) { + VdH_0004 = Vh_vpack_VwVw_sat(VuW_0812,VvW_1620); + build EndPacket; +} + +# (hvx,1) vpacko -- "Vd.b=vpacko(Vu.h,Vv.h)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 1 1 1 v v v v v P P 0 u u u u u 0 0 1 d d d d d + +define pcodeop Vb_vpacko_VhVh; + +:vpacko VdB_0004,VuH_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x7f & op13=0x0 & op0507=0x1 & VdB_0004 & VuH_0812 & VvH_1620 & $(END_PACKET) { + VdB_0004 = Vb_vpacko_VhVh(VuH_0812,VvH_1620); + build EndPacket; +} + +# (hvx,1) vpacko -- "Vd.h=vpacko(Vu.w,Vv.w)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 1 1 1 v v v v v P P 0 u u u u u 0 1 0 d d d d d + +define pcodeop Vh_vpacko_VwVw; + +:vpacko VdH_0004,VuW_0812,VvW_1620 EndPacket is iclass=0x1 & op2127=0x7f & op13=0x0 & op0507=0x2 & VdH_0004 & VuW_0812 & VvW_1620 & $(END_PACKET) { + VdH_0004 = Vh_vpacko_VwVw(VuW_0812,VvW_1620); + build EndPacket; +} + +# (hvx,1) vsetq -- "Qd4=vsetq(Rt)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 1 0 1 t t t t t P P 0 - - - - - 0 1 0 - 0 1 d d + +define pcodeop Q_vsetq_R; + +:vsetq Qd2,rx5 EndPacket is iclass=0x1 & op2127=0x4d & op13=0x0 & op0507=0x2 & op3=0x0 & op2=0x1 & Qd2 & rx5 & $(END_PACKET) { + Qd2 = Q_vsetq_R(rx5); + build EndPacket; +} + +# (hvx,1) vsetq2 -- "Qd4=vsetq2(Rt)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 1 0 1 t t t t t P P 0 - - - - - 0 1 0 - 1 1 d d + +define pcodeop Q_vsetq2_R; + +:vsetq2 Qd2,rx5 EndPacket is iclass=0x1 & op2127=0x4d & op13=0x0 & op0507=0x2 & op3=0x1 & op2=0x1 & Qd2 & rx5 & $(END_PACKET) { + Qd2 = Q_vsetq2_R(rx5); + build EndPacket; +} + +# (hvx,1) vlut32 -- "Vd.b=vlut32(Vu.b,Vv.b,Rt):nomatch" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 0 v v v v v t t t P P 0 u u u u u 0 1 1 d d d d d + +define pcodeop Vb_vlut32_VbVbR_nomatch; + +:vlut32^":nomatch" VdB_0004,VuB_0812,VzB_1923,rt1618 EndPacket is iclass=0x1 & op2427=0x8 & op13=0x0 & op0507=0x3 & VdB_0004 & VuB_0812 & VzB_1923 & rt1618 & $(END_PACKET) { + VdB_0004 = Vb_vlut32_VbVbR_nomatch(VuB_0812,VzB_1923,rt1618); + build EndPacket; +} + +# (hvx,1) vlut32 -- "Vd.b=vlut32(Vu.b,Vv.b,Rt)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 1 1 v v v v v t t t P P 1 u u u u u 0 0 1 d d d d d + +define pcodeop Vb_vlut32_VbVbR; + +:vlut32 VdB_0004,VuB_0812,VzB_1923,rt1618 EndPacket is iclass=0x1 & op2427=0xb & op13=0x1 & op0507=0x1 & VdB_0004 & VuB_0812 & VzB_1923 & rt1618 & $(END_PACKET) { + VdB_0004 = Vb_vlut32_VbVbR(VuB_0812,VzB_1923,rt1618); + build EndPacket; +} + +# (hvx,1) vlut32 -- "Vd.b=vlut32(Vu.b,Vv.b,#u3)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 0 0 1 v v v v v P P 0 u u u u u i i i d d d d d + +define pcodeop Vb_vlut32_VbVbI; + +:vlut32 VdB_0004,VuB_0812,VvB_1620,Uimm8_0507 EndPacket is iclass=0x1 & op2127=0x71 & op13=0x0 & VdB_0004 & VuB_0812 & VvB_1620 & Uimm8_0507 & $(END_PACKET) { + VdB_0004 = Vb_vlut32_VbVbI(VuB_0812,VvB_1620,Uimm8_0507); + build EndPacket; +} + +# (hvx,1) vasrinto -- "Vxx.w=vasrinto(Vu.w,Vv.w)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 1 0 1 0 1 v v v v v P P 1 u u u u u 1 1 1 x x x x x + +define pcodeop vasrinto_WwVwVw; + +:vasrinto VddW_0004,VuW_0812,VvW_1620 EndPacket is iclass=0x1 & op2127=0x55 & op13=0x1 & op0507=0x7 & vss5 & VddW_0004 & VuW_0812 & VvW_1620 & $(END_PACKET) { + VddW_0004 = vasrinto_WwVwVw(vss5,VuW_0812,VvW_1620); + build EndPacket; +} + +# (hvx,1) vshuff -- "vshuff(Vy,Vx,Rt)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 1 1 1 t t t t t P P 1 y y y y y 0 0 1 x x x x x + +define pcodeop vshuff_VwVwR; + +:vshuff vu5,vs5,rx5 EndPacket is iclass=0x1 & op2127=0x4f & op13=0x1 & op0507=0x1 & vu5 & vs5 & rx5 & $(END_PACKET) { + # NOTE: Uncertain if this logic is correct or if .new value store should be updated in some way + pair:$(HVX_VECTOR_PAIR_SIZE) = vshuff_VwVwR(vu5,vs5,rx5); + build EndPacket; + <> + # Extract updated Vy and Vx vectors from 'pair' result from vshuff + vu5 = pair($(HVX_VECTOR_SIZE)); + vs5 = pair:$(HVX_VECTOR_SIZE); +} + +# (hvx,1) vdeal -- "vdeal(Vy,Vx,Rt)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 1 1 1 t t t t t P P 1 y y y y y 0 1 0 x x x x x + +define pcodeop vdeal_VwVwR; + +:vdeal vu5,vs5,rx5 EndPacket is iclass=0x1 & op2127=0x4f & op13=0x1 & op0507=0x2 & vu5 & vs5 & rx5 & $(END_PACKET) { + # NOTE: Uncertain if this logic is correct or if .new value store should be updated in some way + pair:$(HVX_VECTOR_PAIR_SIZE) = vdeal_VwVwR(vu5,vs5,rx5); + build EndPacket; + <> + # Extract updated Vy and Vx vectors from 'pair' result from vdeal + vu5 = pair($(HVX_VECTOR_SIZE)); + vs5 = pair:$(HVX_VECTOR_SIZE); +} + +# (hvx,1) vshuff -- "Vdd=vshuff(Vu,Vv,Rt)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 1 1 v v v v v t t t P P 1 u u u u u 0 1 1 d d d d d + +:vshuff Vdd5,Vu_0812,Vz_1923,rt1618 EndPacket is iclass=0x1 & op2427=0xb & op13=0x1 & op0507=0x3 & Vdd5 & Vu_0812 & Vz_1923 & rt1618 & $(END_PACKET) { + Vdd5 = vshuff_VwVwR(Vu_0812,Vz_1923,rt1618); + build EndPacket; +} + +# (hvx,1) vdeal -- "Vdd=vdeal(Vu,Vv,Rt)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 1 1 v v v v v t t t P P 1 u u u u u 1 0 0 d d d d d + +:vdeal Vdd5,Vu_0812,Vz_1923,rt1618 EndPacket is iclass=0x1 & op2427=0xb & op13=0x1 & op0507=0x4 & Vdd5 & Vu_0812 & Vz_1923 & rt1618 & $(END_PACKET) { + Vdd5 = vdeal_VwVwR(Vu_0812,Vz_1923,rt1618); + build EndPacket; +} + +# (hvx,1) vlut16 -- "Vdd.h=vlut16(Vu.b,Vv.h,Rt):nomatch" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 0 v v v v v t t t P P 0 u u u u u 1 0 0 d d d d d + +define pcodeop vlut16_VbVhR_nomatch; + +:vlut16^":nomatch" VddH_0004,VuB_0812,VzH_1923,rt1618 EndPacket is iclass=0x1 & op2427=0x8 & op13=0x0 & op0507=0x4 & vss5 & VddH_0004 & VuB_0812 & VzH_1923 & rt1618 & $(END_PACKET) { + VddH_0004 = vlut16_VbVhR_nomatch(vss5,VuB_0812,VzH_1923,rt1618); + build EndPacket; +} + +# (hvx,1) vlut32 -- "Vx.b|=vlut32(Vu.b,Vv.b,Rt)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 1 1 v v v v v t t t P P 1 u u u u u 1 0 1 x x x x x + +define pcodeop vlut32or_VbVbVbR; + +:vlut32|= VdB_0004,VuB_0812,VzB_1923,rt1618 EndPacket is iclass=0x1 & op2427=0xb & op13=0x1 & op0507=0x5 & vs5 & VdB_0004 & VuB_0812 & VzB_1923 & rt1618 & $(END_PACKET) { + VdB_0004 = vlut32or_VbVbVbR(vs5,VuB_0812,VzB_1923,rt1618); + build EndPacket; +} + +# (hvx,1) vlut16 -- "Vdd.h=vlut16(Vu.b,Vv.h,Rt)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 1 1 v v v v v t t t P P 1 u u u u u 1 1 0 d d d d d + +define pcodeop vlut16_VbVhR; + +:vlut16 VddH_0004,VuB_0812,VzH_1923,rt1618 EndPacket is iclass=0x1 & op2427=0xb & op13=0x1 & op0507=0x6 & VddH_0004 & VuB_0812 & VzH_1923 & rt1618 & $(END_PACKET) { + VddH_0004 = vlut16_VbVhR(VuB_0812,VzH_1923,rt1618); + build EndPacket; +} + +# (hvx,1) vlut16 -- "Vxx.h|=vlut16(Vu.b,Vv.h,Rt)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 1 1 v v v v v t t t P P 1 u u u u u 1 1 1 x x x x x + +define pcodeop vlut16or_WhVbVhR; + +:vlut16|= VddH_0004,VuB_0812,VzH_1923,rt1618 EndPacket is iclass=0x1 & op2427=0xb & op13=0x1 & op0507=0x7 & vss5 & VddH_0004 & VuB_0812 & VzH_1923 & rt1618 & $(END_PACKET) { + VddH_0004 = vlut16or_WhVbVhR(vss5,VuB_0812,VzH_1923,rt1618); + build EndPacket; +} + +# (hvx,1) vlut32 -- "Vx.b|=vlut32(Vu.b,Vv.b,#u3)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 1 0 v v v v v P P 1 u u u u u i i i x x x x x + +define pcodeop vlut32or_VbVbVbI; + +:vlut32|= VdB_0004,VuB_0812,VvB_1620,Uimm8_0507 EndPacket is iclass=0x1 & op2127=0x66 & op13=0x1 & vs5 & VdB_0004 & VuB_0812 & VvB_1620 & Uimm8_0507 & $(END_PACKET) { + VdB_0004 = vlut32or_VbVbVbI(vs5,VuB_0812,VvB_1620,Uimm8_0507); + build EndPacket; +} + +# (hvx,1) vlut16 -- "Vxx.h|=vlut16(Vu.b,Vv.h,#u3)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 0 1 1 1 v v v v v P P 1 u u u u u i i i x x x x x + +define pcodeop vlut16or_WhVbVhI; + +:vlut16|= VddH_0004,VuB_0812,VvH_1620,Uimm8_0507 EndPacket is iclass=0x1 & op2127=0x67 & op13=0x1 & vss5 & VddH_0004 & VuB_0812 & VvH_1620 & Uimm8_0507 & $(END_PACKET) { + VddH_0004 = vlut16or_WhVbVhI(vss5,VuB_0812,VvH_1620,Uimm8_0507); + build EndPacket; +} + +# (hvx,1) vlut16 -- "Vdd.h=vlut16(Vu.b,Vv.h,#u3)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 0 1 1 v v v v v P P 0 u u u u u i i i d d d d d + +define pcodeop vlut16_VbVhI; + +:vlut16 VddH_0004,VuB_0812,VvH_1620,Uimm8_0507 EndPacket is iclass=0x1 & op2127=0x73 & op13=0x0 & vss5 & VddH_0004 & VuB_0812 & VvH_1620 & Uimm8_0507 & $(END_PACKET) { + VddH_0004 = vlut16_VbVhI(vss5,VuB_0812,VvH_1620,Uimm8_0507); + build EndPacket; +} + +# (hvx,1) vunpack -- "Vdd.uh=vunpack(Vu.ub)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 - - 0 - - - 0 1 P P 0 u u u u u 0 0 0 d d d d d + +define pcodeop Wuh_vunpack_Vub; + +:vunpack VddUH_0004,VuUB_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op1617=0x1 & op13=0x0 & op0507=0x0 & VddUH_0004 & VuUB_0812 & $(END_PACKET) { + VddUH_0004 = Wuh_vunpack_Vub(VuUB_0812); + build EndPacket; +} + +# (hvx,1) vunpack -- "Vdd.uw=vunpack(Vu.uh)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 - - 0 - - - 0 1 P P 0 u u u u u 0 0 1 d d d d d + +define pcodeop Wuw_vunpack_Vuh; + +:vunpack VddUW_0004,VuUH_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op1617=0x1 & op13=0x0 & op0507=0x1 & VddUW_0004 & VuUH_0812 & $(END_PACKET) { + VddUW_0004 = Wuw_vunpack_Vuh(VuUH_0812); + build EndPacket; +} + +# (hvx,1) vunpack -- "Vdd.h=vunpack(Vu.b)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 - - 0 - - - 0 1 P P 0 u u u u u 0 1 0 d d d d d + +define pcodeop Wh_vunpack_Vb; + +:vunpack VddH_0004,VuB_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op1617=0x1 & op13=0x0 & op0507=0x2 & VddH_0004 & VuB_0812 & $(END_PACKET) { + VddH_0004 = Wh_vunpack_Vb(VuB_0812); + build EndPacket; +} + +# (hvx,1) vunpack -- "Vdd.w=vunpack(Vu.h)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 - - 0 - - - 0 1 P P 0 u u u u u 0 1 1 d d d d d + +define pcodeop Ww_vunpack_Vh; + +:vunpack VddW_0004,VuH_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op1617=0x1 & op13=0x0 & op0507=0x3 & VddW_0004 & VuH_0812 & $(END_PACKET) { + VddW_0004 = Ww_vunpack_Vh(VuH_0812); + build EndPacket; +} + +# (hvx,1) vunpacko -- "Vxx.h|=vunpacko(Vu.b)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 - - 0 - - 0 0 0 P P 1 u u u u u 0 0 0 x x x x x + +define pcodeop vunpackoor_WhVb; + +:vunpacko|= VddH_0004,VuB_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x0 & op1617=0x0 & op13=0x1 & op0507=0x0 & vss5 & VddH_0004 & VuB_0812 & $(END_PACKET) { + VddH_0004 = vunpackoor_WhVb(vss5,VuB_0812); + build EndPacket; +} + +# (hvx,1) vunpacko -- "Vxx.w|=vunpacko(Vu.h)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 - - 0 - - 0 0 0 P P 1 u u u u u 0 0 1 x x x x x + +define pcodeop vunpackoor_WwVh; + +:vunpacko|= VddW_0004,VuH_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x0 & op1617=0x0 & op13=0x1 & op0507=0x1 & vss5 & VddW_0004 & VuH_0812 & $(END_PACKET) { + VddW_0004 = vunpackoor_WwVh(vss5,VuH_0812); + build EndPacket; +} + +# (hvx,2) "vscatter(Rt,Mu,Vvv.w).h=Vw32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 1 1 1 0 0 1 t t t t t P P u v v v v v 0 1 0 w w w w w + +define pcodeop vscatter_RMWwV; + +:vscatter.h rt5,mu,VuuW_0812,Vs_0004 EndPacket is iclass=0x2 & op2127=0x79 & op0507=0x2 & rt5 & mu & VuuW_0812 & Vs_0004 & $(END_PACKET) { + # May need to splt-up to convey delayed memory commit vs register reads + vscatter_RMWwV(rt5,mu,VuuW_0812,Vs_0004); + build EndPacket; +} + +# (hvx,2) "vscatter(Rt,Mu,Vvv.w).h+=Vw32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 1 1 1 0 0 1 t t t t t P P u v v v v v 1 1 0 w w w w w + +define pcodeop vscatteracc_RMWwV; + +:vscatter.h+= rt5,mu,VuuW_0812,Vs_0004 EndPacket is iclass=0x2 & op2127=0x79 & op0507=0x6 & rt5 & mu & VuuW_0812 & Vs_0004 & $(END_PACKET) { + # May need to splt-up to convey delayed memory commit vs register reads + vscatteracc_RMWwV(rt5,mu,VuuW_0812,Vs_0004); + build EndPacket; +} + +# (hvx,2) "if (Qs4) vscatter(Rt,Mu,Vvv.w).h=Vw32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 1 1 1 1 0 1 t t t t t P P u v v v v v 0 s s w w w w w + +define pcodeop vscatter_QRMWwV; + +:vscatter.h^".if("^qv0506^")" rt5,mu,VuuW_0812,Vs_0004 EndPacket is iclass=0x2 & op2127=0x7d & op7=0x0 & qv0506 & rt5 & mu & VuuW_0812 & Vs_0004 & $(END_PACKET) { + # May need to splt-up to convey delayed memory commit vs register reads + vscatter_QRMWwV(qv0506,rt5,mu,VuuW_0812,Vs_0004); + build EndPacket; +} + +# (hvx,2) "vscatter(Rt,Mu,Vv.w).w=Vw32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 1 1 1 0 0 1 t t t t t P P u v v v v v 0 0 0 w w w w w + +define pcodeop vscatter_RMVwV; + +:vscatter.w rt5,mu,VuW_0812,Vs_0004 EndPacket is iclass=0x2 & op2127=0x79 & op0507=0x0 & rt5 & mu & VuW_0812 & Vs_0004 & $(END_PACKET) { + # May need to splt-up to convey delayed memory commit vs register reads + vscatter_RMVwV(rt5,mu,VuW_0812,Vs_0004); + build EndPacket; +} + +# (hvx,2) "vscatter(Rt,Mu,Vv.h).h=Vw32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 1 1 1 0 0 1 t t t t t P P u v v v v v 0 0 1 w w w w w + +define pcodeop vscatter_RMVhV; + +:vscatter.h rt5,mu,VuH_0812,Vs_0004 EndPacket is iclass=0x2 & op2127=0x79 & op0507=0x1 & rt5 & mu & VuH_0812 & Vs_0004 & $(END_PACKET) { + # May need to splt-up to convey delayed memory commit vs register reads + vscatter_RMVhV(rt5,mu,VuH_0812,Vs_0004); + build EndPacket; +} + +# (hvx,2) "vscatter(Rt,Mu,Vv.w).w+=Vw32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 1 1 1 0 0 1 t t t t t P P u v v v v v 1 0 0 w w w w w + +define pcodeop vscatteracc_RMVwV; + +:vscatter.w+= rt5,mu,VuW_0812,Vs_0004 EndPacket is iclass=0x2 & op2127=0x79 & op0507=0x4 & rt5 & mu & VuW_0812 & Vs_0004 & $(END_PACKET) { + # May need to splt-up to convey delayed memory commit vs register reads + vscatteracc_RMVwV(rt5,mu,VuW_0812,Vs_0004); + build EndPacket; +} + +# (hvx,2) "vscatter(Rt,Mu,Vv.h).h+=Vw32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 1 1 1 0 0 1 t t t t t P P u v v v v v 1 0 1 w w w w w + +define pcodeop vscatteracc_RMVhV; + +:vscatter.h+= rt5,mu,VuH_0812,Vs_0004 EndPacket is iclass=0x2 & op2127=0x79 & op0507=0x5 & rt5 & mu & VuH_0812 & Vs_0004 & $(END_PACKET) { + # May need to splt-up to convey delayed memory commit vs register reads + vscatteracc_RMVhV(rt5,mu,VuH_0812,Vs_0004); + build EndPacket; +} + +# (hvx,2) "if (Qs4) vscatter(Rt,Mu,Vv.w).w=Vw32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 1 1 1 1 0 0 t t t t t P P u v v v v v 0 s s w w w w w + +define pcodeop vscatter_QRMVwV; + +:vscatter.w^".if("^qv0506^")" rt5,mu,VuW_0812,Vs_0004 EndPacket is iclass=0x2 & op2127=0x7c & op7=0x0 & qv0506 & rt5 & mu & VuW_0812 & Vs_0004 & $(END_PACKET) { + # May need to splt-up to convey delayed memory commit vs register reads + vscatter_QRMVwV(qv0506,rt5,mu,VuW_0812,Vs_0004); + build EndPacket; +} + +# (hvx,2) "if (Qs4) vscatter(Rt,Mu,Vv.h).h=Vw32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 1 1 1 1 0 0 t t t t t P P u v v v v v 1 s s w w w w w + +define pcodeop vscatter_QRMVhV; + +:vscatter.h^".if("^qv0506^")" rt5,mu,VuH_0812,Vs_0004 EndPacket is iclass=0x2 & op2127=0x7c & op7=0x1 & qv0506 & rt5 & mu & VuH_0812 & Vs_0004 & $(END_PACKET) { + # May need to splt-up to convey delayed memory commit vs register reads + vscatter_QRMVhV(qv0506,rt5,mu,VuH_0812,Vs_0004); + build EndPacket; +} + +# (hvx,1) vasr -- "Vd.b=vasr(Vu.h,Vv.h,Rt):sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 0 v v v v v t t t P P 0 u u u u u 0 0 0 d d d d d + +define pcodeop Vb_vasr_VhVhR_sat; + +:vasr^":sat" VdB_0004,VuH_0812,VzH_1923,rt1618 EndPacket is iclass=0x1 & op2427=0x8 & op13=0x0 & op0507=0x0 & VdB_0004 & VuH_0812 & VzH_1923 & rt1618 & $(END_PACKET) { + VdB_0004 = Vb_vasr_VhVhR_sat(VuH_0812,VzH_1923,rt1618); + build EndPacket; +} + +# (hvx,1) vasr -- "Vd.uh=vasr(Vu.uw,Vv.uw,Rt):rnd:sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 0 v v v v v t t t P P 0 u u u u u 0 0 1 d d d d d + +define pcodeop vasr_VhVhR_rnd_sat; + +:vasr^":rnd:sat" VdUH_0004,VuUW_0812,VzUW_1923,rt1618 EndPacket is iclass=0x1 & op2427=0x8 & op13=0x0 & op0507=0x1 & VdUH_0004 & VuUW_0812 & VzUW_1923 & rt1618 & $(END_PACKET) { + VdUH_0004 = vasr_VhVhR_rnd_sat(VuUW_0812,VzUW_1923,rt1618); + build EndPacket; +} + +# (hvx,1) vasr -- "Vd.uh=vasr(Vu.w,Vv.w,Rt):rnd:sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 0 v v v v v t t t P P 0 u u u u u 0 1 0 d d d d d + +define pcodeop Vuh_vasr_VwVwR_rnd_sat; + +:vasr^":rnd:sat" VdUH_0004,VuW_0812,VzW_1923,rt1618 EndPacket is iclass=0x1 & op2427=0x8 & op13=0x0 & op0507=0x2 & VdUH_0004 & VuW_0812 & VzW_1923 & rt1618 & $(END_PACKET) { + VdUH_0004 = Vuh_vasr_VwVwR_rnd_sat(VuW_0812,VzW_1923,rt1618); + build EndPacket; +} + +# (hvx,1) vasr -- "Vd.ub=vasr(Vu.uh,Vv.uh,Rt):rnd:sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 0 v v v v v t t t P P 0 u u u u u 1 1 1 d d d d d + +define pcodeop Vub_vasr_VuhVuhR_rnd_sat; + +:vasr^":rnd:sat" VdUB_0004,VuUH_0812,VzUH_1923,rt1618 EndPacket is iclass=0x1 & op2427=0x8 & op13=0x0 & op0507=0x7 & VdUB_0004 & VuUH_0812 & VzUH_1923 & rt1618 & $(END_PACKET) { + VdUB_0004 = Vub_vasr_VuhVuhR_rnd_sat(VuUH_0812,VzUH_1923,rt1618); + build EndPacket; +} + +# (hvx,1) vasr -- "Vd.uh=vasr(Vu.uw,Vv.uw,Rt):sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 0 v v v v v t t t P P 1 u u u u u 1 0 0 d d d d d + +define pcodeop Vuh_vasr_VuwVuwR_sat; + +:vasr^":sat" VdUH_0004,VuUW_0812,VzUW_1923,rt1618 EndPacket is iclass=0x1 & op2427=0x8 & op13=0x1 & op0507=0x4 & VdUH_0004 & VuUW_0812 & VzUW_1923 & rt1618 & $(END_PACKET) { + VdUH_0004 = Vuh_vasr_VuwVuwR_sat(VuUW_0812,VzUW_1923,rt1618); + build EndPacket; +} + +# (hvx,1) vasr -- "Vd.ub=vasr(Vu.uh,Vv.uh,Rt):sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 0 v v v v v t t t P P 1 u u u u u 1 0 1 d d d d d + +define pcodeop Vub_vasr_VuhVuhR_sat; + +:vasr^":sat" VdUB_0004,VuUH_0812,VzUH_1923,rt1618 EndPacket is iclass=0x1 & op2427=0x8 & op13=0x1 & op0507=0x5 & VdUB_0004 & VuUH_0812 & VzUH_1923 & rt1618 & $(END_PACKET) { + VdUB_0004 = Vub_vasr_VuhVuhR_sat(VuUH_0812,VzUH_1923,rt1618); + build EndPacket; +} + +# (hvx,1) vasr -- "Vd.h=vasr(Vu.w,Vv.w,Rt)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 1 1 v v v v v t t t P P 0 u u u u u 0 1 0 d d d d d + +define pcodeop Vh_vasr_VwVwR; + +:vasr VdH_0004,VuW_0812,VzW_1923,rt1618 EndPacket is iclass=0x1 & op2427=0xb & op13=0x0 & op0507=0x2 & VdH_0004 & VuW_0812 & VzW_1923 & rt1618 & $(END_PACKET) { + VdH_0004 = Vh_vasr_VwVwR(VuW_0812,VzW_1923,rt1618); + build EndPacket; +} + +# (hvx,1) vasr -- "Vd.h=vasr(Vu.w,Vv.w,Rt):sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 1 1 v v v v v t t t P P 0 u u u u u 0 1 1 d d d d d + +define pcodeop Vh_vasr_VwVwR_sat; + +:vasr^":sat" VdH_0004,VuW_0812,VzW_1923,rt1618 EndPacket is iclass=0x1 & op2427=0xb & op13=0x0 & op0507=0x3 & VdH_0004 & VuW_0812 & VzW_1923 & rt1618 & $(END_PACKET) { + VdH_0004 = Vh_vasr_VwVwR_sat(VuW_0812,VzW_1923,rt1618); + build EndPacket; +} + +# (hvx,1) vasr -- "Vd.h=vasr(Vu.w,Vv.w,Rt):rnd:sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 1 1 v v v v v t t t P P 0 u u u u u 1 0 0 d d d d d + +define pcodeop Vh_vasr_VwVwR_rnd_sat; + +:vasr^":rnd:sat" VdH_0004,VuW_0812,VzW_1923,rt1618 EndPacket is iclass=0x1 & op2427=0xb & op13=0x0 & op0507=0x4 & VdH_0004 & VuW_0812 & VzW_1923 & rt1618 & $(END_PACKET) { + VdH_0004 = Vh_vasr_VwVwR_rnd_sat(VuW_0812,VzW_1923,rt1618); + build EndPacket; +} + +# (hvx,1) vasr -- "Vd.uh=vasr(Vu.w,Vv.w,Rt):sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 1 1 v v v v v t t t P P 0 u u u u u 1 0 1 d d d d d + +define pcodeop Vuh_vasr_VwVwR_sat; + +:vasr^":sat" VdUH_0004,VuW_0812,VzW_1923,rt1618 EndPacket is iclass=0x1 & op2427=0xb & op13=0x0 & op0507=0x5 & VdUH_0004 & VuW_0812 & VzW_1923 & rt1618 & $(END_PACKET) { + VdUH_0004 = Vuh_vasr_VwVwR_sat(VuW_0812,VzW_1923,rt1618); + build EndPacket; +} + +# (hvx,1) vasr -- "Vd.ub=vasr(Vu.h,Vv.h,Rt):sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 1 1 v v v v v t t t P P 0 u u u u u 1 1 0 d d d d d + +define pcodeop Vub_vasr_VhVhR_sat; + +:vasr^":sat" VdUB_0004,VuH_0812,VzH_1923,rt1618 EndPacket is iclass=0x1 & op2427=0xb & op13=0x0 & op0507=0x6 & VdUB_0004 & VuH_0812 & VzH_1923 & rt1618 & $(END_PACKET) { + VdUB_0004 = Vub_vasr_VhVhR_sat(VuH_0812,VzH_1923,rt1618); + build EndPacket; +} + +# (hvx,1) vasr -- "Vd.ub=vasr(Vu.h,Vv.h,Rt):rnd:sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 1 1 v v v v v t t t P P 0 u u u u u 1 1 1 d d d d d + +define pcodeop Vub_vasr_VhVhR_rnd_sat; + +:vasr^":rnd:sat" VdUB_0004,VuH_0812,VzH_1923,rt1618 EndPacket is iclass=0x1 & op2427=0xb & op13=0x0 & op0507=0x7 & VdUB_0004 & VuH_0812 & VzH_1923 & rt1618 & $(END_PACKET) { + VdUB_0004 = Vub_vasr_VhVhR_rnd_sat(VuH_0812,VzH_1923,rt1618); + build EndPacket; +} + +# (hvx,1) vasr -- "Vd.b=vasr(Vu.h,Vv.h,Rt):rnd:sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 1 1 v v v v v t t t P P 1 u u u u u 0 0 0 d d d d d + +define pcodeop Vb_vasr_VhVhR_rnd_sat; + +:vasr^":rnd:sat" VdB_0004,VuH_0812,VzH_1923,rt1618 EndPacket is iclass=0x1 & op2427=0xb & op13=0x1 & op0507=0x0 & VdB_0004 & VuH_0812 & VzH_1923 & rt1618 & $(END_PACKET) { + VdB_0004 = Vb_vasr_VhVhR_rnd_sat(VuH_0812,VzH_1923,rt1618); + build EndPacket; +} + +# (hvx,1) prefixsum -- "Vd.b=prefixsum(Qv4)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 v v 0 - - 0 1 1 P P 1 - - 0 0 0 0 1 0 d d d d d + +define pcodeop Vb_prefixsum_Q; + +:prefixsum VdB_0004,qv2223 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x0 & op1617=0x3 & op13=0x1 & op0810=0x0 & op0507=0x2 & VdB_0004 & qv2223 & $(END_PACKET) { + VdB_0004 = Vb_prefixsum_Q(qv2223); + build EndPacket; +} + +# (hvx,1) prefixsum -- "Vd.h=prefixsum(Qv4)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 v v 0 - - 0 1 1 P P 1 - - 0 0 1 0 1 0 d d d d d + +define pcodeop Vh_prefixsum_Q; + +:prefixsum VdH_0004,qv2223 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x0 & op1617=0x3 & op13=0x1 & op0810=0x1 & op0507=0x2 & VdH_0004 & qv2223 & $(END_PACKET) { + VdH_0004 = Vh_prefixsum_Q(qv2223); + build EndPacket; +} + +# (hvx,1) prefixsum -- "Vd.w=prefixsum(Qv4)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 v v 0 - - 0 1 1 P P 1 - - 0 1 0 0 1 0 d d d d d + +define pcodeop Vw_prefixsum_Q; + +:prefixsum VdW_0004,qv2223 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x0 & op1617=0x3 & op13=0x1 & op0810=0x2 & op0507=0x2 & VdW_0004 & qv2223 & $(END_PACKET) { + VdW_0004 = Vw_prefixsum_Q(qv2223); + build EndPacket; +} + +# (hvx,1) vadd -- "Vd.qf16=vadd(Vu.qf16,Vv.qf16)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 0 1 1 v v v v v P P 1 u u u u u 0 1 0 d d d d d + +define pcodeop Vqf16_vadd_Vqf16Vqf16; + +:vadd VdQF16_0004,VuQF16_0812,VvQF16_1620 EndPacket is iclass=0x1 & op2127=0x7b & op13=0x1 & op0507=0x2 & VdQF16_0004 & VuQF16_0812 & VvQF16_1620 & $(END_PACKET) { + VdQF16_0004 = Vqf16_vadd_Vqf16Vqf16(VuQF16_0812,VvQF16_1620); + build EndPacket; +} + +# (hvx,1) vadd -- "Vd.qf16=vadd(Vu.hf,Vv.hf)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 0 1 1 v v v v v P P 1 u u u u u 0 1 1 d d d d d + +define pcodeop Vqf16_vadd_VhfVhf; + +:vadd VdQF16_0004,VuHF_0812,VvHF_1620 EndPacket is iclass=0x1 & op2127=0x7b & op13=0x1 & op0507=0x3 & VdQF16_0004 & VuHF_0812 & VvHF_1620 & $(END_PACKET) { + VdQF16_0004 = Vqf16_vadd_VhfVhf(VuHF_0812,VvHF_1620); + build EndPacket; +} + +# (hvx,1) vadd -- "Vd.qf16=vadd(Vu.qf16,Vv.hf)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 0 1 1 v v v v v P P 1 u u u u u 1 0 0 d d d d d + +define pcodeop Vqf16_vadd_Vqf16Vhf; + +:vadd VdQF16_0004,VuQF16_0812,VvHF_1620 EndPacket is iclass=0x1 & op2127=0x7b & op13=0x1 & op0507=0x4 & VdQF16_0004 & VuQF16_0812 & VvHF_1620 & $(END_PACKET) { + VdQF16_0004 = Vqf16_vadd_Vqf16Vhf(VuQF16_0812,VvHF_1620); + build EndPacket; +} + +# (hvx,1) vadd -- "Vd.qf32=vadd(Vu.qf32,Vv.qf32)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 1 0 1 v v v v v P P 1 u u u u u 0 0 0 d d d d d + +define pcodeop Vqf32_vadd_Vqf32Vqf32; + +:vadd VdQF32_0004,VuQF32_0812,VvQF32_1620 EndPacket is iclass=0x1 & op2127=0x7d & op13=0x1 & op0507=0x0 & VdQF32_0004 & VuQF32_0812 & VvQF32_1620 & $(END_PACKET) { + VdQF32_0004 = Vqf32_vadd_Vqf32Vqf32(VuQF32_0812,VvQF32_1620); + build EndPacket; +} + +# (hvx,1) vadd -- "Vd.qf32=vadd(Vu.sf,Vv.sf)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 1 0 1 v v v v v P P 1 u u u u u 0 0 1 d d d d d + +define pcodeop Vqf32_vadd_VsfVsf; + +:vadd VdQF32_0004,VuSF_0812,VvSF_1620 EndPacket is iclass=0x1 & op2127=0x7d & op13=0x1 & op0507=0x1 & VdQF32_0004 & VuSF_0812 & VvSF_1620 & $(END_PACKET) { + VdQF32_0004 = Vqf32_vadd_VsfVsf(VuSF_0812,VvSF_1620); + build EndPacket; +} + +# (hvx,1) vadd -- "Vd.qf32=vadd(Vu.qf32,Vv.sf)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 1 0 1 v v v v v P P 1 u u u u u 0 1 0 d d d d d + +define pcodeop Vqf32_vadd_Vqf32Vsf; + +:vadd VdQF32_0004,VuQF32_0812,VvSF_1620 EndPacket is iclass=0x1 & op2127=0x7d & op13=0x1 & op0507=0x2 & VdQF32_0004 & VuQF32_0812 & VvSF_1620 & $(END_PACKET) { + VdQF32_0004 = Vqf32_vadd_Vqf32Vsf(VuQF32_0812,VvSF_1620); + build EndPacket; +} + +# (hvx,1) vasl -- "Vx.w+=vasl(Vu.w,Rt)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 0 1 1 t t t t t P P 1 u u u u u 0 1 0 x x x x x + +define pcodeop vaslacc_VwVwR; + +:vasl+= VdW_0004,VuW_0812,rx5 EndPacket is iclass=0x1 & op2127=0x4b & op13=0x1 & op0507=0x2 & vs5 & VdW_0004 & VuW_0812 & rx5 & $(END_PACKET) { + VdW_0004 = vaslacc_VwVwR(vs5,VuW_0812,rx5); + build EndPacket; +} + +# (hvx,1) vasr -- "Vx.w+=vasr(Vu.w,Rt)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 0 1 1 t t t t t P P 1 u u u u u 1 0 1 x x x x x + +define pcodeop vasracc_VwVwR; + +:vasr+= VdW_0004,VuW_0812,rx5 EndPacket is iclass=0x1 & op2127=0x4b & op13=0x1 & op0507=0x5 & vs5 & VdW_0004 & VuW_0812 & rx5 & $(END_PACKET) { + VdW_0004 = vasracc_VwVwR(vs5,VuW_0812,rx5); + build EndPacket; +} + +# (hvx,1) vasr -- "Vx.h+=vasr(Vu.h,Rt)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 1 0 0 t t t t t P P 1 u u u u u 1 1 1 x x x x x + +define pcodeop vasracc_VhVhR; + +:vasr+= VdH_0004,VuH_0812,rx5 EndPacket is iclass=0x1 & op2127=0x4c & op13=0x1 & op0507=0x7 & vs5 & VdH_0004 & VuH_0812 & rx5 & $(END_PACKET) { + VdH_0004 = vasracc_VhVhR(vs5,VuH_0812,rx5); + build EndPacket; +} + +# (hvx,1) vasl -- "Vx.h+=vasl(Vu.h,Rt)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 1 0 1 t t t t t P P 1 u u u u u 1 0 1 x x x x x + +define pcodeop vaslacc_VhVhR; + +:vasl+= VdH_0004,VuH_0812,rx5 EndPacket is iclass=0x1 & op2127=0x4d & op13=0x1 & op0507=0x5 & vs5 & VdH_0004 & VuH_0812 & rx5 & $(END_PACKET) { + VdH_0004 = vaslacc_VhVhR(vs5,VuH_0812,rx5); + build EndPacket; +} + +# (hvx,1) vasr -- "Vd.w=vasr(Vu.w,Rt)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 0 1 1 t t t t t P P 0 u u u u u 1 0 1 d d d d d + +define pcodeop vasr_VwR; + +:vasr VdW_0004,VuW_0812,rx5 EndPacket is iclass=0x1 & op2127=0x4b & op13=0x0 & op0507=0x5 & VdW_0004 & VuW_0812 & rx5 & $(END_PACKET) { + VdW_0004 = vasr_VwR(VuW_0812,rx5); + build EndPacket; +} + +# (hvx,1) vasr -- "Vd.h=vasr(Vu.h,Rt)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 0 1 1 t t t t t P P 0 u u u u u 1 1 0 d d d d d + +define pcodeop vasr_VhR; + +:vasr VdH_0004,VuH_0812,rx5 EndPacket is iclass=0x1 & op2127=0x4b & op13=0x0 & op0507=0x6 & VdH_0004 & VuH_0812 & rx5 & $(END_PACKET) { + VdH_0004 = vasr_VhR(VuH_0812,rx5); + build EndPacket; +} + +# (hvx,1) vasl -- "Vd.w=vasl(Vu.w,Rt)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 0 1 1 t t t t t P P 0 u u u u u 1 1 1 d d d d d + +define pcodeop vasl_VwR; + +:vasl VdW_0004,VuW_0812,rx5 EndPacket is iclass=0x1 & op2127=0x4b & op13=0x0 & op0507=0x7 & VdW_0004 & VuW_0812 & rx5 & $(END_PACKET) { + VdW_0004 = vasl_VwR(VuW_0812,rx5); + build EndPacket; +} + +# (hvx,1) vasl -- "Vd.h=vasl(Vu.h,Rt)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 1 0 0 t t t t t P P 0 u u u u u 0 0 0 d d d d d + +define pcodeop vasl_VhR; + +:vasl VdH_0004,VuH_0812,rx5 EndPacket is iclass=0x1 & op2127=0x4c & op13=0x0 & op0507=0x0 & VdH_0004 & VuH_0812 & rx5 & $(END_PACKET) { + VdH_0004 = vasl_VhR(VuH_0812,rx5); + build EndPacket; +} + +# (hvx,1) vlsr -- "Vd.uw=vlsr(Vu.uw,Rt)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 1 0 0 t t t t t P P 0 u u u u u 0 0 1 d d d d d + +define pcodeop vlsr_VuwR; + +:vlsr VdUW_0004,VuUW_0812,rx5 EndPacket is iclass=0x1 & op2127=0x4c & op13=0x0 & op0507=0x1 & VdUW_0004 & VuUW_0812 & rx5 & $(END_PACKET) { + VdUW_0004 = vlsr_VuwR(VuUW_0812,rx5); + build EndPacket; +} + +# (hvx,1) vlsr -- "Vd.uh=vlsr(Vu.uh,Rt)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 1 0 0 t t t t t P P 0 u u u u u 0 1 0 d d d d d + +define pcodeop vlsr_VuhR; + +:vlsr VdUH_0004,VuUH_0812,rx5 EndPacket is iclass=0x1 & op2127=0x4c & op13=0x0 & op0507=0x2 & VdUH_0004 & VuUH_0812 & rx5 & $(END_PACKET) { + VdUH_0004 = vlsr_VuhR(VuUH_0812,rx5); + build EndPacket; +} + +# (hvx,1) vlsr -- "Vd.ub=vlsr(Vu.ub,Rt)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 0 1 1 0 0 t t t t t P P 0 u u u u u 0 1 1 d d d d d + +define pcodeop vlsr_VubR; + +:vlsr VdUB_0004,VuUB_0812,rx5 EndPacket is iclass=0x1 & op2127=0x4c & op13=0x0 & op0507=0x3 & VdUB_0004 & VuUB_0812 & rx5 & $(END_PACKET) { + VdUB_0004 = vlsr_VubR(VuUB_0812,rx5); + build EndPacket; +} + +# (hvx,1) vasr -- "Vd.w=vasr(Vu.w,Vv.w)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 1 0 1 v v v v v P P 0 u u u u u 0 0 0 d d d d d + +define pcodeop vasr_VwVw; + +:vasr VdW_0004,VuW_0812,VvW_1620 EndPacket is iclass=0x1 & op2127=0x7d & op13=0x0 & op0507=0x0 & VdW_0004 & VuW_0812 & VvW_1620 & $(END_PACKET) { + VdW_0004 = vasr_VwVw(VuW_0812,VvW_1620); + build EndPacket; +} + +# (hvx,1) vlsr -- "Vd.w=vlsr(Vu.w,Vv.w)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 1 0 1 v v v v v P P 0 u u u u u 0 0 1 d d d d d + +define pcodeop vlsr_VwVw; + +:vlsr VdW_0004,VuW_0812,VvW_1620 EndPacket is iclass=0x1 & op2127=0x7d & op13=0x0 & op0507=0x1 & VdW_0004 & VuW_0812 & VvW_1620 & $(END_PACKET) { + VdW_0004 = vlsr_VwVw(VuW_0812,VvW_1620); + build EndPacket; +} + +# (hvx,1) vlsr -- "Vd.h=vlsr(Vu.h,Vv.h)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 1 0 1 v v v v v P P 0 u u u u u 0 1 0 d d d d d + +define pcodeop vlsr_VhVh; + +:vlsr VdH_0004,VuH_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x7d & op13=0x0 & op0507=0x2 & VdH_0004 & VuH_0812 & VvH_1620 & $(END_PACKET) { + VdH_0004 = vlsr_VhVh(VuH_0812,VvH_1620); + build EndPacket; +} + +# (hvx,1) vasr -- "Vd.h=vasr(Vu.h,Vv.h)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 1 0 1 v v v v v P P 0 u u u u u 0 1 1 d d d d d + +define pcodeop vasr_VhVh; + +:vasr VdH_0004,VuH_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x7d & op13=0x0 & op0507=0x3 & VdH_0004 & VuH_0812 & VvH_1620 & $(END_PACKET) { + VdH_0004 = vasr_VhVh(VuH_0812,VvH_1620); + build EndPacket; +} + +# (hvx,1) vasl -- "Vd.w=vasl(Vu.w,Vv.w)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 1 0 1 v v v v v P P 0 u u u u u 1 0 0 d d d d d + +define pcodeop vasl_VwVw; + +:vasl VdW_0004,VuW_0812,VvW_1620 EndPacket is iclass=0x1 & op2127=0x7d & op13=0x0 & op0507=0x4 & VdW_0004 & VuW_0812 & VvW_1620 & $(END_PACKET) { + VdW_0004 = vasl_VwVw(VuW_0812,VvW_1620); + build EndPacket; +} + +# (hvx,1) vasl -- "Vd.h=vasl(Vu.h,Vv.h)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 1 0 1 v v v v v P P 0 u u u u u 1 0 1 d d d d d + +define pcodeop vasl_VhVh; + +:vasl VdH_0004,VuH_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x7d & op13=0x0 & op0507=0x5 & VdH_0004 & VuH_0812 & VvH_1620 & $(END_PACKET) { + VdH_0004 = vasl_VhVh(VuH_0812,VvH_1620); + build EndPacket; +} + +# (hvx,1) vasr -- "Vd.uh=vasr(Vuu.w,Vv.uh):sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 1 0 0 0 v v v v v P P 0 u u u u u 0 0 0 d d d d d + +define pcodeop Vuh_vasr_WwVuh_sat; + +:vasr^":sat" VdUH_0004,VuuW_0812,VvUH_1620 EndPacket is iclass=0x1 & op2127=0x68 & op13=0x0 & op0507=0x0 & VdUH_0004 & VuuW_0812 & VvUH_1620 & $(END_PACKET) { + VdUH_0004 = Vuh_vasr_WwVuh_sat(VuuW_0812,VvUH_1620); + build EndPacket; +} + +# (hvx,1) vasr -- "Vd.uh=vasr(Vuu.w,Vv.uh):rnd:sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 1 0 0 0 v v v v v P P 0 u u u u u 0 0 1 d d d d d + +define pcodeop Vuh_vasr_WwVuh_rnd_sat; + +:vasr^":rnd:sat" VdUH_0004,VuuW_0812,VvUH_1620 EndPacket is iclass=0x1 & op2127=0x68 & op13=0x0 & op0507=0x1 & VdUH_0004 & VuuW_0812 & VvUH_1620 & $(END_PACKET) { + VdUH_0004 = Vuh_vasr_WwVuh_rnd_sat(VuuW_0812,VvUH_1620); + build EndPacket; +} + +# (hvx,1) vasr -- "Vd.ub=vasr(Vuu.uh,Vv.ub):sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 1 0 0 0 v v v v v P P 0 u u u u u 0 1 0 d d d d d + +define pcodeop Vub_vasr_WuhVub_sat; + +:vasr^":sat" VdUB_0004,VuuUH_0812,VvUB_1620 EndPacket is iclass=0x1 & op2127=0x68 & op13=0x0 & op0507=0x2 & VdUB_0004 & VuuUH_0812 & VvUB_1620 & $(END_PACKET) { + VdUB_0004 = Vub_vasr_WuhVub_sat(VuuUH_0812,VvUB_1620); + build EndPacket; +} + +# (hvx,1) vasr -- "Vd.ub=vasr(Vuu.uh,Vv.ub):rnd:sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 0 1 0 0 0 v v v v v P P 0 u u u u u 0 1 1 d d d d d + +define pcodeop Vub_vasr_WuhVub_rnd_sat; + +:vasr^":rnd:sat" VdUB_0004,VuuUH_0812,VvUB_1620 EndPacket is iclass=0x1 & op2127=0x68 & op13=0x0 & op0507=0x3 & VdUB_0004 & VuuUH_0812 & VvUB_1620 & $(END_PACKET) { + VdUB_0004 = Vub_vasr_WuhVub_rnd_sat(VuuUH_0812,VvUB_1620); + build EndPacket; +} + +# (hvx,1) "Vd.sf=Vu.qf32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 - - 0 - - 1 0 0 P P 1 u u u u u 0 0 0 d d d d d + +define pcodeop Vsf_equals_Vqf32; + +:assign VdSF_0004,VuQF32_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x1 & op1617=0x0 & op13=0x1 & op0507=0x0 & VdSF_0004 & VuQF32_0812 & $(END_PACKET) { + VdSF_0004 = Vsf_equals_Vqf32(VuQF32_0812); + build EndPacket; +} + +# (hvx,1) "Vd.hf=Vu.qf16" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 - - 0 - - 1 0 0 P P 1 u u u u u 0 1 1 d d d d d + +define pcodeop Vhf_equals_Vqf16; + +:assign VdHF_0004,VuQF16_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x1 & op1617=0x0 & op13=0x1 & op0507=0x3 & VdHF_0004 & VuQF16_0812 & $(END_PACKET) { + VdHF_0004 = Vhf_equals_Vqf16(VuQF16_0812); + build EndPacket; +} + +# (hvx,1) "Vd.hf=Vuu.qf32" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 - - 0 - - 1 0 0 P P 1 u u u u u 1 1 0 d d d d d + +define pcodeop Vhf_equals_Wqf32; + +:assign VdHF_0004,VuuQF32_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op18=0x1 & op1617=0x0 & op13=0x1 & op0507=0x6 & VdHF_0004 & VuuQF32_0812 & $(END_PACKET) { + VdHF_0004 = Vhf_equals_Wqf32(VuuQF32_0812); + build EndPacket; +} + +# (hvx,1) vround -- "Vd.h=vround(Vu.w,Vv.w):sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 0 1 1 v v v v v P P 0 u u u u u 1 0 0 d d d d d + +define pcodeop Vh_vround_VwVw_sat; + +:vround^":sat" VdH_0004,VuW_0812,VvW_1620 EndPacket is iclass=0x1 & op2127=0x7b & op13=0x0 & op0507=0x4 & VdH_0004 & VuW_0812 & VvW_1620 & $(END_PACKET) { + VdH_0004 = Vh_vround_VwVw_sat(VuW_0812,VvW_1620); + build EndPacket; +} + +# (hvx,1) vround -- "Vd.uh=vround(Vu.w,Vv.w):sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 0 1 1 v v v v v P P 0 u u u u u 1 0 1 d d d d d + +define pcodeop Vuh_vround_VwVw_sat; + +:vround^":sat" VdUH_0004,VuW_0812,VvW_1620 EndPacket is iclass=0x1 & op2127=0x7b & op13=0x0 & op0507=0x5 & VdUH_0004 & VuW_0812 & VvW_1620 & $(END_PACKET) { + VdUH_0004 = Vuh_vround_VwVw_sat(VuW_0812,VvW_1620); + build EndPacket; +} + +# (hvx,1) vround -- "Vd.b=vround(Vu.h,Vv.h):sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 0 1 1 v v v v v P P 0 u u u u u 1 1 0 d d d d d + +define pcodeop Vb_vround_VhVh_sat; + +:vround^":sat" VdB_0004,VuH_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x7b & op13=0x0 & op0507=0x6 & VdB_0004 & VuH_0812 & VvH_1620 & $(END_PACKET) { + VdB_0004 = Vb_vround_VhVh_sat(VuH_0812,VvH_1620); + build EndPacket; +} + +# (hvx,1) vround -- "Vd.ub=vround(Vu.h,Vv.h):sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 0 1 1 v v v v v P P 0 u u u u u 1 1 1 d d d d d + +define pcodeop Vub_vround_VhVh_sat; + +:vround^":sat" VdUB_0004,VuH_0812,VvH_1620 EndPacket is iclass=0x1 & op2127=0x7b & op13=0x0 & op0507=0x7 & VdUB_0004 & VuH_0812 & VvH_1620 & $(END_PACKET) { + VdUB_0004 = Vub_vround_VhVh_sat(VuH_0812,VvH_1620); + build EndPacket; +} + +# (hvx,1) vround -- "Vd.ub=vround(Vu.uh,Vv.uh):sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 1 1 1 v v v v v P P 0 u u u u u 0 1 1 d d d d d + +define pcodeop Vub_vround_VuhVuh_sat; + +:vround^":sat" VdUB_0004,VuUH_0812,VvUH_1620 EndPacket is iclass=0x1 & op2127=0x7f & op13=0x0 & op0507=0x3 & VdUB_0004 & VuUH_0812 & VvUH_1620 & $(END_PACKET) { + VdUB_0004 = Vub_vround_VuhVuh_sat(VuUH_0812,VvUH_1620); + build EndPacket; +} + +# (hvx,1) vround -- "Vd.uh=vround(Vu.uw,Vv.uw):sat" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 1 1 1 v v v v v P P 0 u u u u u 1 0 0 d d d d d + +define pcodeop Vuh_vround_VuwVuw_sat; + +:vround^":sat" VdUH_0004,VuUW_0812,VvUW_1620 EndPacket is iclass=0x1 & op2127=0x7f & op13=0x0 & op0507=0x4 & VdUH_0004 & VuUW_0812 & VvUW_1620 & $(END_PACKET) { + VdUH_0004 = Vuh_vround_VuwVuw_sat(VuUW_0812,VvUW_1620); + build EndPacket; +} + +# (hvx,1) vrotr -- "Vd.uw=vrotr(Vu.uw,Vv.uw)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 0 1 0 1 0 0 v v v v v P P 1 u u u u u 1 1 1 d d d d d + +define pcodeop Vuw_vrotr_VuwVuw; + +:vrotr VdUW_0004,VuUW_0812,VvUW_1620 EndPacket is iclass=0x1 & op2127=0x54 & op13=0x1 & op0507=0x7 & VdUW_0004 & VuUW_0812 & VvUW_1620 & $(END_PACKET) { + VdUW_0004 = Vuw_vrotr_VuwVuw(VuUW_0812,VvUW_1620); + build EndPacket; +} + +# (hvx,1) vsub -- "Vd.qf16=vsub(Vu.qf16,Vv.qf16)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 0 1 1 v v v v v P P 1 u u u u u 1 0 1 d d d d d + +define pcodeop Vqf16_vsub_Vqf16Vqf16; + +:vsub VdQF16_0004,VuQF16_0812,VvQF16_1620 EndPacket is iclass=0x1 & op2127=0x7b & op13=0x1 & op0507=0x5 & VdQF16_0004 & VuQF16_0812 & VvQF16_1620 & $(END_PACKET) { + VdQF16_0004 = Vqf16_vsub_Vqf16Vqf16(VuQF16_0812,VvQF16_1620); + build EndPacket; +} + +# (hvx,1) vsub -- "Vd.qf16=vsub(Vu.hf,Vv.hf)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 0 1 1 v v v v v P P 1 u u u u u 1 1 0 d d d d d + +define pcodeop Vqf16_vsub_VhfVhf; + +:vsub VdQF16_0004,VuHF_0812,VvHF_1620 EndPacket is iclass=0x1 & op2127=0x7b & op13=0x1 & op0507=0x6 & VdQF16_0004 & VuHF_0812 & VvHF_1620 & $(END_PACKET) { + VdQF16_0004 = Vqf16_vsub_VhfVhf(VuHF_0812,VvHF_1620); + build EndPacket; +} + +# (hvx,1) vsub -- "Vd.qf16=vsub(Vu.qf16,Vv.hf)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 0 1 1 v v v v v P P 1 u u u u u 1 1 1 d d d d d + +define pcodeop Vqf16_vsub_Vqf16Vhf; + +:vsub VdQF16_0004,VuQF16_0812,VvHF_1620 EndPacket is iclass=0x1 & op2127=0x7b & op13=0x1 & op0507=0x7 & VdQF16_0004 & VuQF16_0812 & VvHF_1620 & $(END_PACKET) { + VdQF16_0004 = Vqf16_vsub_Vqf16Vhf(VuQF16_0812,VvHF_1620); + build EndPacket; +} + +# (hvx,1) vsub -- "Vd.qf32=vsub(Vu.qf32,Vv.qf32)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 1 0 1 v v v v v P P 1 u u u u u 0 1 1 d d d d d + +define pcodeop Vqf32_vsub_Vqf32Vqf32; + +:vsub VdQF32_0004,VuQF32_0812,VvQF32_1620 EndPacket is iclass=0x1 & op2127=0x7d & op13=0x1 & op0507=0x3 & VdQF32_0004 & VuQF32_0812 & VvQF32_1620 & $(END_PACKET) { + VdQF32_0004 = Vqf32_vsub_Vqf32Vqf32(VuQF32_0812,VvQF32_1620); + build EndPacket; +} + +# (hvx,1) vsub -- "Vd.qf32=vsub(Vu.sf,Vv.sf)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 1 0 1 v v v v v P P 1 u u u u u 1 0 0 d d d d d + +define pcodeop Vqf32_vsub_VsfVsf; + +:vsub VdQF32_0004,VuSF_0812,VvSF_1620 EndPacket is iclass=0x1 & op2127=0x7d & op13=0x1 & op0507=0x4 & VdQF32_0004 & VuSF_0812 & VvSF_1620 & $(END_PACKET) { + VdQF32_0004 = Vqf32_vsub_VsfVsf(VuSF_0812,VvSF_1620); + build EndPacket; +} + +# (hvx,1) vsub -- "Vd.qf32=vsub(Vu.qf32,Vv.sf)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 1 0 1 v v v v v P P 1 u u u u u 1 0 1 d d d d d + +define pcodeop Vqf32_vsub_Vqf32Vsf; + +:vsub VdQF32_0004,VuQF32_0812,VvSF_1620 EndPacket is iclass=0x1 & op2127=0x7d & op13=0x1 & op0507=0x5 & VdQF32_0004 & VuQF32_0812 & VvSF_1620 & $(END_PACKET) { + VdQF32_0004 = Vqf32_vsub_Vqf32Vsf(VuQF32_0812,VvSF_1620); + build EndPacket; +} + +# (hvx,1) vcl0 -- "Vd.uw=vcl0(Vu.uw)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 - - 0 - - - 1 0 P P 0 u u u u u 1 0 1 d d d d d + +define pcodeop Vuw_vcl0_Vuw; + +:vcl0 VdUW_0004,VuUW_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op1617=0x2 & op13=0x0 & op0507=0x5 & VdUW_0004 & VuUW_0812 & $(END_PACKET) { + VdUW_0004 = Vuw_vcl0_Vuw(VuUW_0812); + build EndPacket; +} + +# (hvx,1) vpopcount -- "Vd.h=vpopcount(Vu.h)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 - - 0 - - - 1 0 P P 0 u u u u u 1 1 0 d d d d d + +define pcodeop Vh_vpopcount_Vh; + +:vpopcount VdH_0004,VuH_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op1617=0x2 & op13=0x0 & op0507=0x6 & VdH_0004 & VuH_0812 & $(END_PACKET) { + VdH_0004 = Vh_vpopcount_Vh(VuH_0812); + build EndPacket; +} + +# (hvx,1) vcl0 -- "Vd.uh=vcl0(Vu.uh)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 - - 0 - - - 1 0 P P 0 u u u u u 1 1 1 d d d d d + +define pcodeop Vuh_vcl0_Vuh; + +:vcl0 VdUH_0004,VuUH_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op1617=0x2 & op13=0x0 & op0507=0x7 & VdUH_0004 & VuUH_0812 & $(END_PACKET) { + VdUH_0004 = Vuh_vcl0_Vuh(VuUH_0812); + build EndPacket; +} + +# (hvx,1) vnormamt -- "Vd.w=vnormamt(Vu.w)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 - - 0 - - - 1 1 P P 0 u u u u u 1 0 0 d d d d d + +define pcodeop Vw_vnormamt_Vw; + +:vnormamt VdW_0004,VuW_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op1617=0x3 & op13=0x0 & op0507=0x4 & VdW_0004 & VuW_0812 & $(END_PACKET) { + VdW_0004 = Vw_vnormamt_Vw(VuW_0812); + build EndPacket; +} + +# (hvx,1) vnormamt -- "Vd.h=vnormamt(Vu.h)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 0 - - 0 - - - 1 1 P P 0 u u u u u 1 0 1 d d d d d + +define pcodeop Vh_vnormamt_Vh; + +:vnormamt VdH_0004,VuH_0812 EndPacket is iclass=0x1 & op2427=0xe & op21=0x0 & op1617=0x3 & op13=0x0 & op0507=0x5 & VdH_0004 & VuH_0812 & $(END_PACKET) { + VdH_0004 = Vh_vnormamt_Vh(VuH_0812); + build EndPacket; +} + +# (hvx,1) vadd -- "Vd.h=vadd(vclb(Vu.h),Vv.h)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 0 0 0 v v v v v P P 1 u u u u u 0 0 0 d d d d d + +define pcodeop vadd_vclb_VhVh; + +:vadd VdH_0004,"vclb("^VuH_0812^")",VvH_1620 EndPacket is iclass=0x1 & op2127=0x78 & op13=0x1 & op0507=0x0 & VdH_0004 & VuH_0812 & VvH_1620 & $(END_PACKET) { + build EndPacket; + <> + VdH_0004 = vadd_vclb_VhVh(VuH_0812,VvH_1620); +} + +# (hvx,1) vadd -- "Vd.w=vadd(vclb(Vu.w),Vv.w)" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 1 1 1 1 0 0 0 v v v v v P P 1 u u u u u 0 0 1 d d d d d + +define pcodeop vadd_vclb_VwVw; + +:vadd VdW_0004,"vclb("^VuW_0812^")",VvW_1620 EndPacket is iclass=0x1 & op2127=0x78 & op13=0x1 & op0507=0x1 & VdW_0004 & VuW_0812 & VvW_1620 & $(END_PACKET) { + build EndPacket; + <> + VdW_0004 = vadd_vclb_VwVw(VuW_0812,VvW_1620); +} + +# (hvx,2) "if (Qv4) vmem(Rt+#s4)=Vs" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 0 1 0 0 t t t t t P P i v v i i i 0 0 0 s s s s s +# +# (hvx,2) "if (Qv4) vmem(Rt+#s4):nt=Vs" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 0 1 1 0 t t t t t P P i v v i i i 0 0 0 s s s s s +# +# (hvx,2) "if (!Qv4) vmem(Rt+#s4)=Vs" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 0 1 0 0 t t t t t P P i v v i i i 0 0 1 s s s s s +# +# (hvx,2) "if (!Qv4) vmem(Rt+#s4):nt=Vs" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 0 1 1 0 t t t t t P P i v v i i i 0 0 1 s s s s s + +define pcodeop vmemStoreIf; # aligned store of vector bytes where corresponding predicate bit is set + +:vmem^".if("^Qv_1112_S05^")"^ntHint22 VAlignMemAddrRxS4,Vs_0004 EndPacket is iclass=0x2 & op2127=0x44 & op0607=0x0 & ntHint22 & Qv_1112_S05 & VAlignMemAddrRxS4 & Vs_0004 & $(END_PACKET) { + build EndPacket; + <> + vmemStoreIf(Qv_1112_S05, VAlignMemAddrRxS4, Vs_0004); +} + +# (hvx,2) "if (Qv4) vmem(Rx++#s3)=Vs" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 1 1 0 0 x x x x x P P - v v i i i 0 0 0 s s s s s +# +# (hvx,2) "if (Qv4) vmem(Rx++#s3):nt=Vs" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 1 1 1 0 x x x x x P P - v v i i i 0 0 0 s s s s s +# +# (hvx,2) "if (!Qv4) vmem(Rx++#s3)=Vs" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 1 1 0 0 x x x x x P P - v v i i i 0 0 1 s s s s s +# +# (hvx,2) "if (!Qv4) vmem(Rx++#s3):nt=Vs" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 1 1 1 0 x x x x x P P - v v i i i 0 0 1 s s s s s + +:vmem^".if("^Qv_1112_S05^")"^ntHint22 VAlignMemAddrRxAIS3,Vs_0004 EndPacket is iclass=0x2 & op2127=0x4c & op0607=0x0 & ntHint22 & Qv_1112_S05 & VAlignMemAddrRxAIS3 & Vs_0004 & $(END_PACKET) { + build EndPacket; + <> + vmemStoreIf(Qv_1112_S05, VAlignMemAddrRxAIS3, Vs_0004); +} + +# (hvx,2) "if (Qv4) vmem(Rx++Mu)=Vs" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 1 1 1 0 0 x x x x x P P u v v - - - 0 0 0 s s s s s +# +# (hvx,2) "if (Qv4) vmem(Rx++Mu):nt=Vs" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 1 1 1 1 0 x x x x x P P u v v - - - 0 0 0 s s s s s +# +# (hvx,2) "if (!Qv4) vmem(Rx++Mu)=Vs" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 1 1 1 0 0 x x x x x P P u v v - - - 0 0 1 s s s s s +# +# (hvx,2) "if (!Qv4) vmem(Rx++Mu):nt=Vs" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 1 1 1 1 0 x x x x x P P u v v - - - 0 0 1 s s s s s + +:vmem^".if("^Qv_1112_S05^")"^ntHint22 VAlignMemAddrRxAIMu,Vs_0004 EndPacket is iclass=0x2 & op2127=0x5c & op0607=0x0 & ntHint22 & Qv_1112_S05 & VAlignMemAddrRxAIMu & Vs_0004 & $(END_PACKET) { + build EndPacket; + <> + vmemStoreIf(Qv_1112_S05, VAlignMemAddrRxAIMu, Vs_0004); +} + +# (hvx,2) "vmem(Rt+#s4)=Os8.new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 0 0 0 1 t t t t t P P i - - i i i 0 0 1 - 0 s s s +# +# (hvx,2) "vmem(Rt+#s4):nt=Os8.new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 0 0 1 1 t t t t t P P i - - i i i 0 0 1 - - s s s + +:vmem^ntHint22 VAlignMemAddrRxS4,VNreg0002 EndPacket is iclass=0x2 & op2127=0x41 & op0507=0x1 & op3=0x0 & ntHint22 & VAlignMemAddrRxS4 & VNreg0002 & $(END_PACKET) { + build EndPacket; + <> + VAlignMemAddrRxS4 = VNreg0002; +} + +# (hvx,2) "if (Pv) vmem(Rt+#s4)=Os8.new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 0 1 0 1 t t t t t P P i v v i i i 0 1 0 0 0 s s s +# +# (hvx,2) "if (!Pv) vmem(Rt+#s4)=Os8.new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 0 1 0 1 t t t t t P P i v v i i i 0 1 1 0 1 s s s +# +# (hvx,2) "if (Pv) vmem(Rt+#s4):nt=Os8.new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 0 1 1 1 t t t t t P P i v v i i i 0 1 0 1 0 s s s +# +# (hvx,2) "if (!Pv) vmem(Rt+#s4):nt=Os8.new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 0 1 1 1 t t t t t P P i v v i i i 0 1 1 1 1 s s s +# +# NOTE: We tie op4=op22 & op3=op5 to reduce the number of constructors + +:vmem^VPuCond1112_S05^ntHint22 VAlignMemAddrRxS4,VNreg0002 EndPacket is iclass=0x2 & op21=1 & op2327=0x11 & op0607=0x1 & op4=op22 & op3=op5 & VPuCond1112_S05 & ntHint22 & VAlignMemAddrRxS4 & VNreg0002 & $(END_PACKET) { + build VPuCond1112_S05; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + VAlignMemAddrRxS4 = VNreg0002; + +} + +# (hvx,2) "vmem(Rx++#s3)=Os8.new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 1 0 0 1 x x x x x P P - - - i i i 0 0 1 - 0 s s s +# +# (hvx,2) "vmem(Rx++#s3):nt=Os8.new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 1 0 1 1 x x x x x P P - - - i i i 0 0 1 - - s s s + +:vmem^ntHint22 VAlignMemAddrRxAIS3,VNreg0002 EndPacket is iclass=0x2 & op2127=0x49 & op0507=0x1 & op3=0x0 & ntHint22 & VAlignMemAddrRxAIS3 & VNreg0002 & $(END_PACKET) [ cond=0; ] { + build EndPacket; + <> + VAlignMemAddrRxAIS3 = VNreg0002; +} + +# (hvx,2) "if (Pv) vmem(Rx++#s3)=Os8.new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 1 1 0 1 x x x x x P P - v v i i i 0 1 0 0 0 s s s +# +# (hvx,2) "if (!Pv) vmem(Rx++#s3)=Os8.new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 1 1 0 1 x x x x x P P - v v i i i 0 1 1 0 1 s s s +# +# (hvx,2) "if (Pv) vmem(Rx++#s3):nt=Os8.new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 1 1 1 1 x x x x x P P - v v i i i 0 1 0 1 0 s s s +# +# (hvx,2) "if (!Pv) vmem(Rx++#s3):nt=Os8.new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 1 1 1 1 x x x x x P P - v v i i i 0 1 1 1 1 s s s +# +# NOTE: We tie op4=op22 & op3=op5 to reduce the number of constructors + +:vmem^VPuCond1112_S05^ntHint22 VAlignMemAddrRxAIS3,VNreg0002 EndPacket is iclass=0x2 & op21=1 & op2327=0x13 & op0607=0x1 & op4=op22 & op3=op5 & VPuCond1112_S05 & ntHint22 & VAlignMemAddrRxAIS3 & VNreg0002 & $(END_PACKET) [ cond=1; ] { + build VPuCond1112_S05; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + VAlignMemAddrRxAIS3 = VNreg0002; + +} + +# (hvx,2) "vmem(Rx++Mu)=Os8.new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 1 1 0 0 1 x x x x x P P u - - - - - 0 0 1 - 0 s s s +# +# (hvx,2) "vmem(Rx++Mu):nt=Os8.new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 1 1 0 1 1 x x x x x P P u - - - - - 0 0 1 - - s s s + +:vmem^ntHint22 VAlignMemAddrRxAIMu,VNreg0002 EndPacket is iclass=0x2 & op2127=0x59 & op0507=0x1 & op3=0x0 & ntHint22 & VAlignMemAddrRxAIMu & VNreg0002 & $(END_PACKET) [ cond=0; ] { + build EndPacket; + <> + VAlignMemAddrRxAIMu = VNreg0002; +} + +# (hvx,2) "if (Pv) vmem(Rx++Mu)=Os8.new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 1 1 1 0 1 x x x x x P P u v v - - - 0 1 0 0 0 s s s +# +# (hvx,2) "if (!Pv) vmem(Rx++Mu)=Os8.new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 1 1 1 0 1 x x x x x P P u v v - - - 0 1 1 0 1 s s s +# +# (hvx,2) "if (Pv) vmem(Rx++Mu):nt=Os8.new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 1 1 1 1 1 x x x x x P P u v v - - - 0 1 0 1 0 s s s +# +# (hvx,2) "if (!Pv) vmem(Rx++Mu):nt=Os8.new" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 1 1 1 1 1 x x x x x P P u v v - - - 0 1 1 1 1 s s s +# +# NOTE: We tie op4=op22 & op3=op5 to reduce the number of constructors + +:vmem^VPuCond1112_S05^ntHint22 VAlignMemAddrRxAIMu,VNreg0002 EndPacket is iclass=0x2 & op21=1 & op2327=0x17 & op0607=0x1 & op4=op22 & op3=op5 & VPuCond1112_S05 & ntHint22 & VAlignMemAddrRxAIMu & VNreg0002 & $(END_PACKET) [ cond=1; ] { + build VPuCond1112_S05; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + VAlignMemAddrRxAIMu = VNreg0002; + +} + +# (hvx,2) "vmem(Rt+#s4)=Vs" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 0 0 0 1 t t t t t P P i - - i i i 0 0 0 s s s s s +# +# (hvx,2) "vmem(Rt+#s4):nt=Vs" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 0 0 1 1 t t t t t P P i - - i i i 0 0 0 s s s s s + +:vmem^ntHint22 VAlignMemAddrRxS4,Vs_0004 EndPacket is iclass=0x2 & op21=1 & op2327=0x10 & op0507=0x0 & ntHint22 & VAlignMemAddrRxS4 & Vs_0004 & $(END_PACKET) { + build EndPacket; + <> + VAlignMemAddrRxS4 = Vs_0004; +} + +# (hvx,2) "if (Pv) vmem(Rt+#s4)=Vs" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 0 1 0 1 t t t t t P P i v v i i i 0 0 0 s s s s s +# +# (hvx,2) "if (!Pv) vmem(Rt+#s4)=Vs" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 0 1 0 1 t t t t t P P i v v i i i 0 0 1 s s s s s +# +# (hvx,2) "if (Pv) vmem(Rt+#s4):nt=Vs" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 0 1 1 1 t t t t t P P i v v i i i 0 0 0 s s s s s +# +# (hvx,2) "if (!Pv) vmem(Rt+#s4):nt=Vs" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 0 1 1 1 t t t t t P P i v v i i i 0 0 1 s s s s s + +:vmem^VPuCond1112_S05^ntHint22 VAlignMemAddrRxS4,Vs_0004 EndPacket is iclass=0x2 & op21=1 & op2327=0x11 & op0607=0x0 & VPuCond1112_S05 & ntHint22 & VAlignMemAddrRxS4 & Vs_0004 & $(END_PACKET) { + build VPuCond1112_S05; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + VAlignMemAddrRxS4 = Vs_0004; + +} + +# (hvx,2) "vmem(Rx++#s3)=Vs" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 1 0 0 1 x x x x x P P - - - i i i 0 0 0 s s s s s +# +# (hvx,2) "vmem(Rx++#s3):nt=Vs" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 1 0 1 1 x x x x x P P - - - i i i 0 0 0 s s s s s + +:vmem^ntHint22 VAlignMemAddrRxAIS3,Vs_0004 EndPacket is iclass=0x2 & op21=1 & op2327=0x12 & op0607=0x0 & ntHint22 & VAlignMemAddrRxAIS3 & Vs_0004 & $(END_PACKET) [ cond=0; ] { + build EndPacket; + <> + VAlignMemAddrRxAIS3 = Vs_0004; +} + +# (hvx,2) "if (Pv) vmem(Rx++#s3)=Vs" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 1 1 0 1 x x x x x P P - v v i i i 0 0 0 s s s s s +# +# (hvx,2) "if (!Pv) vmem(Rx++#s3)=Vs" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 1 1 0 1 x x x x x P P - v v i i i 0 0 1 s s s s s +# +# (hvx,2) "if (Pv) vmem(Rx++#s3):nt=Vs" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 1 1 1 1 x x x x x P P - v v i i i 0 0 0 s s s s s +# +# (hvx,2) "if (!Pv) vmem(Rx++#s3):nt=Vs" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 1 1 1 1 x x x x x P P - v v i i i 0 0 1 s s s s s + +:vmem^VPuCond1112_S05^ntHint22 VAlignMemAddrRxAIS3,Vs_0004 EndPacket is iclass=0x2 & op21=1 & op2327=0x13 & op0607=0x0 & VPuCond1112_S05 & ntHint22 & VAlignMemAddrRxAIS3 & Vs_0004 & $(END_PACKET) [ cond=1; ] { + build VPuCond1112_S05; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + VAlignMemAddrRxAIS3 = Vs_0004; + +} + +# (hvx,2) "vmem(Rx++Mu)=Vs" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 1 1 0 0 1 x x x x x P P u - - - - - 0 0 0 s s s s s +# +# (hvx,2) "vmem(Rx++Mu):nt=Vs" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 1 1 0 1 1 x x x x x P P u - - - - - 0 0 0 s s s s s + +:vmem^ntHint22 VAlignMemAddrRxAIMu,Vs_0004 EndPacket is iclass=0x2 & op21=1 & op2327=0x16 & op0507=0x0 & ntHint22 & VAlignMemAddrRxAIMu & Vs_0004 & $(END_PACKET) [ cond=0; ] { + build EndPacket; + <> + VAlignMemAddrRxAIMu = Vs_0004; +} + +# (hvx,2) "if (Pv) vmem(Rx++Mu)=Vs" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 1 1 1 0 1 x x x x x P P u v v - - - 0 0 0 s s s s s +# +# (hvx,2) "if (!Pv) vmem(Rx++Mu)=Vs" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 1 1 1 0 1 x x x x x P P u v v - - - 0 0 1 s s s s s +# +# (hvx,2) "if (Pv) vmem(Rx++Mu):nt=Vs" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 1 1 1 1 1 x x x x x P P u v v - - - 0 0 0 s s s s s +# +# (hvx,2) "if (!Pv) vmem(Rx++Mu):nt=Vs" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 1 1 1 1 1 x x x x x P P u v v - - - 0 0 1 s s s s s + +:vmem^VPuCond1112_S05^ntHint22 VAlignMemAddrRxAIMu,Vs_0004 EndPacket is iclass=0x2 & op21=1 & op2327=0x17 & op0607=0x0 & VPuCond1112_S05 & ntHint22 & VAlignMemAddrRxAIMu & Vs_0004 & $(END_PACKET) [ cond=1; ] { + build VPuCond1112_S05; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + VAlignMemAddrRxAIMu = Vs_0004; + +} + +# (hvx,2) "vmemu(Rt+#s4)=Vs" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 0 0 0 1 t t t t t P P i - - i i i 1 1 1 s s s s s + +:vmemu VMemAddrRxS4,Vs_0004 EndPacket is iclass=0x2 & op2127=0x41 & op0507=0x7 & VMemAddrRxS4 & Vs_0004 & $(END_PACKET) { + build EndPacket; + <> + VMemAddrRxS4 = Vs_0004; +} + +# (hvx,2) "if (Pv) vmemu(Rt+#s4)=Vs" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 0 1 0 1 t t t t t P P i v v i i i 1 1 0 s s s s s +# +# (hvx,2) "if (!Pv) vmemu(Rt+#s4)=Vs" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 0 1 0 1 t t t t t P P i v v i i i 1 1 1 s s s s s +# + +:vmemu^VPuCond1112_S05 VMemAddrRxS4,Vs_0004 EndPacket is iclass=0x2 & op2127=0x45 & op0607=0x3 & VPuCond1112_S05 & VMemAddrRxS4 & Vs_0004 & $(END_PACKET) { + build VPuCond1112_S05; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + VMemAddrRxS4 = Vs_0004; + +} + +# (hvx,2) "vmemu(Rx++#s3)=Vs" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 1 0 0 1 x x x x x P P - - - i i i 1 1 1 s s s s s + +:vmemu VMemAddrRxAIS3,Vs_0004 EndPacket is iclass=0x2 & op2127=0x49 & op0507=0x7 & VMemAddrRxAIS3 & Vs_0004 & $(END_PACKET) [ cond=0; ] { + build EndPacket; + <> + VMemAddrRxAIS3 = Vs_0004; +} + +# +# (hvx,2) "if (Pv) vmemu(Rx++#s3)=Vs" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 1 1 0 1 x x x x x P P - v v i i i 1 1 0 s s s s s +# +# (hvx,2) "if (!Pv) vmemu(Rx++#s3)=Vs" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 1 1 0 1 x x x x x P P - v v i i i 1 1 1 s s s s s + +:vmemu^VPuCond1112_S05 VMemAddrRxAIS3,Vs_0004 EndPacket is iclass=0x2 & op2127=0x4d & op0607=0x3 & VPuCond1112_S05 & VMemAddrRxAIS3 & Vs_0004 & $(END_PACKET) [ cond=1; ] { + build VPuCond1112_S05; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + VMemAddrRxAIS3 = Vs_0004; + +} + +# (hvx,2) "vmemu(Rx++Mu)=Vs" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 1 1 0 0 1 x x x x x P P u - - - - - 1 1 1 s s s s s + +:vmemu VMemAddrRxAIMu,Vs_0004 EndPacket is iclass=0x2 & op2127=0x59 & op0507=0x7 & VMemAddrRxAIMu & Vs_0004 & $(END_PACKET) [ cond=0; ] { + build EndPacket; + <> + VMemAddrRxAIMu = Vs_0004; +} + +# (hvx,2) "if (Pv) vmemu(Rx++Mu)=Vs" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 1 1 1 0 1 x x x x x P P u v v - - - 1 1 0 s s s s s +# +# (hvx,2) "if (!Pv) vmemu(Rx++Mu)=Vs" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 1 1 1 0 1 x x x x x P P u v v - - - 1 1 1 s s s s s + +:vmemu^VPuCond1112_S05 VMemAddrRxAIMu,Vs_0004 EndPacket is iclass=0x2 & op2127=0x5d & op0607=0x3 & VPuCond1112_S05 & VMemAddrRxAIMu & Vs_0004 & $(END_PACKET) [ cond=1; ] { + build VPuCond1112_S05; + build EndPacket; + <> + if (ConditionReg == 0) goto ; + VMemAddrRxAIMu = Vs_0004; + +} + +# +# NOTE: vmem scatter_release is specific to the V66 to address a V60/V61 pipeline issue where an +# explicit release was required to avoid a scatter storage hazard. These vmem instructions were +# a microarchitectural workaround that existed only for V60‑class cores and was never part of the +# stable, forward‑compatible HVX ISA. +# + +define pcodeop scatter_release; + +# (hvx,2) vmem -- "vmem(Rt+#s4):scatter_release" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 0 0 0 1 t t t t t P P i - - i i i 0 0 1 - 1 - - - + +:vmem^":scatter_release" VAlignMemAddrRxS4 EndPacket is iclass=0x2 & op2127=0x41 & op0507=0x1 & op3=0x1 & VAlignMemAddrRxS4 & $(END_PACKET) { + build EndPacket; + <> + scatter_release(VAlignMemAddrRxS4); +} + +# (hvx,2) vmem -- "vmem(Rx++#s3):scatter_release" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 0 1 0 0 1 x x x x x P P - - - i i i 0 0 1 - 1 - - - + +:vmem^":scatter_release" VAlignMemAddrRxAIS3 EndPacket is iclass=0x2 & op2127=0x49 & op0507=0x1 & op3=0x1 & VAlignMemAddrRxAIS3 & $(END_PACKET) { + build EndPacket; + <> + scatter_release(VAlignMemAddrRxAIS3); +} + +# (hvx,2) vmem -- "vmem(Rx++Mu):scatter_release" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 1 1 0 0 1 x x x x x P P u - - - - - 0 0 1 - 1 - - - + +:vmem^":scatter_release" VAlignMemAddrRxAIMu EndPacket is iclass=0x2 & op2127=0x59 & op0507=0x1 & op3=0x1 & VAlignMemAddrRxAIMu & $(END_PACKET) { + build EndPacket; + <> + scatter_release(VAlignMemAddrRxAIMu); +} + + diff --git a/Ghidra/Processors/Hexagon/data/languages/hexagon_hvx.txt b/Ghidra/Processors/Hexagon/data/languages/hexagon_hvx.txt new file mode 100644 index 0000000000..6a8dc21415 --- /dev/null +++ b/Ghidra/Processors/Hexagon/data/languages/hexagon_hvx.txt @@ -0,0 +1,618 @@ +Hexagon V69 HVX instruction patterns + +0 0 0 1 1 1 1 0 - - 0 - - 0 0 0 P P 1 - 0 0 1 0 1 0 0 - - - - - vwhist256 +0 0 0 1 1 1 1 0 - - 0 - - 0 0 0 P P 1 - 0 0 1 1 1 0 0 - - - - - vwhist256:sat +0 0 0 1 1 1 1 0 - - 0 - - 0 0 0 P P 1 - 0 1 0 - 1 0 0 - - - - - vwhist128 +0 0 0 1 1 1 1 0 - - 0 - - 0 0 0 P P 1 - 0 1 1 i 1 0 0 - - - - - vwhist128(#u1) +0 0 0 1 1 1 1 0 v v 0 - - 0 1 0 P P 1 - - 0 1 0 1 0 0 - - - - - vwhist256(Qv4) +0 0 0 1 1 1 1 0 v v 0 - - 0 1 0 P P 1 - - 0 1 1 1 0 0 - - - - - vwhist256(Qv4):sat +0 0 0 1 1 1 1 0 v v 0 - - 0 1 0 P P 1 - - 1 0 - 1 0 0 - - - - - vwhist128(Qv4) +0 0 0 1 1 1 1 0 v v 0 - - 0 1 0 P P 1 - - 1 1 i 1 0 0 - - - - - vwhist128(Qv4,#u1) +0 0 0 1 1 1 1 0 t t 0 - - - 1 1 P P 0 - - - s s 0 0 0 0 0 0 d d Qd4=and(Qs4,Qt4) +0 0 0 1 1 1 1 0 t t 0 - - - 1 1 P P 0 - - - s s 0 0 0 0 0 1 d d Qd4=or(Qs4,Qt4) +0 0 0 1 1 1 1 0 t t 0 - - - 1 1 P P 0 - - - s s 0 0 0 0 1 1 d d Qd4=xor(Qs4,Qt4) +0 0 0 1 1 1 1 0 t t 0 - - - 1 1 P P 0 - - - s s 0 0 0 1 0 0 d d Qd4=or(Qs4,!Qt4) +0 0 0 1 1 1 1 0 t t 0 - - - 1 1 P P 0 - - - s s 0 0 0 1 0 1 d d Qd4=and(Qs4,!Qt4) +0 0 0 1 1 1 1 0 t t 0 - - - 1 1 P P 0 - - - s s 0 0 0 1 1 0 d d Qd4.b=vshuffe(Qs4.h,Qt4.h) +0 0 0 1 1 1 1 0 t t 0 - - - 1 1 P P 0 - - - s s 0 0 0 1 1 1 d d Qd4.h=vshuffe(Qs4.w,Qt4. +0 0 0 1 1 0 1 0 0 1 0 v v v v v P P - u u u u u - s s d d d d d if (!Ps) Vdd=vcombine(Vu,Vv) +0 0 0 1 1 0 1 0 0 1 1 v v v v v P P - u u u u u - s s d d d d d if (Ps) Vdd=vcombine(Vu,Vv) +0 0 0 1 1 1 1 1 0 1 0 v v v v v P P 0 u u u u u 1 1 1 d d d d d Vdd=vcombine(Vu,Vv) +0 0 0 1 1 1 1 1 0 1 0 v v v v v P P 0 u u u u u 1 0 1 d d d d d Vdd.h=vshuffoe(Vu.h,Vv.h) +0 0 0 1 1 1 1 1 0 1 0 v v v v v P P 0 u u u u u 1 1 0 d d d d d Vdd.b=vshuffoe(Vu.b,Vv.b) +0 0 0 1 1 1 1 0 1 0 1 v v v v v P P 1 u u u u u - t t d d d d d Vdd=vswap(Qt4,Vu,Vv) +0 0 0 1 1 1 1 0 - - 0 - - - 1 0 P P 0 u u u u u 0 0 1 d d d d d Vdd.uh=vzxt(Vu.ub) +0 0 0 1 1 1 1 0 - - 0 - - - 1 0 P P 0 u u u u u 0 1 0 d d d d d Vdd.uw=vzxt(Vu.uh) +0 0 0 1 1 1 1 0 - - 0 - - - 1 0 P P 0 u u u u u 0 1 1 d d d d d Vdd.h=vsxt(Vu.b) +0 0 0 1 1 1 1 0 - - 0 - - - 1 0 P P 0 u u u u u 1 0 0 d d d d d Vdd.w=vsxt(Vu.h) +0 0 0 1 1 1 0 0 0 1 1 v v v v v P P 0 u u u u u 1 0 0 d d d d d Vdd.b=vadd(Vuu.b,Vvv.b) +0 0 0 1 1 1 0 0 0 1 1 v v v v v P P 0 u u u u u 1 0 1 d d d d d Vdd.h=vadd(Vuu.h,Vvv.h) +0 0 0 1 1 1 0 0 0 1 1 v v v v v P P 0 u u u u u 1 1 0 d d d d d Vdd.w=vadd(Vuu.w,Vvv.w) +0 0 0 1 1 1 0 0 0 1 1 v v v v v P P 0 u u u u u 1 1 1 d d d d d Vdd.ub=vadd(Vuu.ub,Vvv.ub):sat +0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 0 u u u u u 0 0 0 d d d d d Vdd.uh=vadd(Vuu.uh,Vvv.uh):sat +0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 0 u u u u u 0 0 1 d d d d d Vdd.h=vadd(Vuu.h,Vvv.h):sat +0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 0 u u u u u 0 1 0 d d d d d Vdd.w=vadd(Vuu.w,Vvv.w):sat +0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 0 u u u u u 0 1 1 d d d d d Vdd.b=vsub(Vuu.b,Vvv.b) +0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 0 u u u u u 1 0 0 d d d d d Vdd.h=vsub(Vuu.h,Vvv.h) +0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 0 u u u u u 1 0 1 d d d d d Vdd.w=vsub(Vuu.w,Vvv.w) +0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 0 u u u u u 1 1 0 d d d d d Vdd.ub=vsub(Vuu.ub,Vvv.ub):sat +0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 0 u u u u u 1 1 1 d d d d d Vdd.uh=vsub(Vuu.uh,Vvv.uh):sat +0 0 0 1 1 1 0 0 1 0 1 v v v v v P P 0 u u u u u 0 0 0 d d d d d Vdd.h=vsub(Vuu.h,Vvv.h):sat +0 0 0 1 1 1 0 0 1 0 1 v v v v v P P 0 u u u u u 0 0 1 d d d d d Vdd.w=vsub(Vuu.w,Vvv.w):sat +0 0 0 1 1 1 1 0 1 0 1 v v v v v P P 0 u u u u u 0 0 0 d d d d d Vdd.b=vadd(Vuu.b,Vvv.b):sat +0 0 0 1 1 1 1 0 1 0 1 v v v v v P P 0 u u u u u 0 0 1 d d d d d Vdd.b=vsub(Vuu.b,Vvv.b):sat +0 0 0 1 1 1 1 0 1 0 1 v v v v v P P 0 u u u u u 0 1 0 d d d d d Vdd.uw=vadd(Vuu.uw,Vvv.uw):sat +0 0 0 1 1 1 1 0 1 0 1 v v v v v P P 0 u u u u u 0 1 1 d d d d d Vdd.uw=vsub(Vuu.uw,Vvv.uw):sat +0 0 0 1 1 1 1 0 - - 0 - - - 1 1 P P 0 - - - s s 0 0 0 0 1 0 d d Qd4=not(Qs4) +0 0 0 1 1 1 1 0 v v 0 - - 0 1 1 P P 1 u u u u u 0 0 0 d d d d d Vd=vand(Qv4,Vu) +0 0 0 1 1 1 1 0 v v 0 - - 0 1 1 P P 1 u u u u u 0 0 1 d d d d d Vd=vand(!Qv4,Vu) +0 0 0 1 1 1 1 1 0 0 0 v v v v v P P 0 u u u u u 0 0 1 d d d d d Vd.ub=vmin(Vu.ub,Vv.ub) +0 0 0 1 1 1 1 1 0 0 0 v v v v v P P 0 u u u u u 0 1 0 d d d d d Vd.uh=vmin(Vu.uh,Vv.uh) +0 0 0 1 1 1 1 1 0 0 0 v v v v v P P 0 u u u u u 0 1 1 d d d d d Vd.h=vmin(Vu.h,Vv.h) +0 0 0 1 1 1 1 1 0 0 0 v v v v v P P 0 u u u u u 1 0 0 d d d d d Vd.w=vmin(Vu.w,Vv.w) +0 0 0 1 1 1 1 1 0 0 0 v v v v v P P 0 u u u u u 1 0 1 d d d d d Vd.ub=vmax(Vu.ub,Vv.ub) +0 0 0 1 1 1 1 1 0 0 0 v v v v v P P 0 u u u u u 1 1 0 d d d d d Vd.uh=vmax(Vu.uh,Vv.uh) +0 0 0 1 1 1 1 1 0 0 0 v v v v v P P 0 u u u u u 1 1 1 d d d d d Vd.h=vmax(Vu.h,Vv.h) +0 0 0 1 1 1 1 1 0 0 1 v v v v v P P 0 u u u u u 0 0 0 d d d d d Vd.w=vmax(Vu.w,Vv.w) +0 0 0 1 1 1 1 1 0 0 1 v v v v v P P 0 u u u u u 1 0 0 d d d d d Vd.b=vmin(Vu.b,Vv.b) +0 0 0 1 1 1 1 1 0 0 1 v v v v v P P 0 u u u u u 1 0 1 d d d d d Vd.b=vmax(Vu.b,Vv.b) +0 0 0 1 1 1 1 1 1 1 0 v v v v v P P 1 u u u u u 0 0 1 d d d d d Vd.sf=vmax(Vu.sf,Vv.sf) +0 0 0 1 1 1 1 1 1 1 0 v v v v v P P 1 u u u u u 0 1 0 d d d d d Vd.sf=vmin(Vu.sf,Vv.sf) +0 0 0 1 1 1 1 1 1 1 0 v v v v v P P 1 u u u u u 0 1 1 d d d d d Vd.hf=vmax(Vu.hf,Vv.hf) +0 0 0 1 1 1 1 1 1 1 0 v v v v v P P 1 u u u u u 1 0 0 d d d d d Vd.hf=vmin(Vu.hf,Vv.hf) +0 0 0 1 1 1 1 0 - - 0 - - - 0 0 P P 0 u u u u u 0 0 0 d d d d d Vd.h=vabs(Vu.h) +0 0 0 1 1 1 1 0 - - 0 - - - 0 0 P P 0 u u u u u 0 0 1 d d d d d Vd.h=vabs(Vu.h):sat +0 0 0 1 1 1 1 0 - - 0 - - - 0 0 P P 0 u u u u u 0 1 0 d d d d d Vd.w=vabs(Vu.w) +0 0 0 1 1 1 1 0 - - 0 - - - 0 0 P P 0 u u u u u 0 1 1 d d d d d Vd.w=vabs(Vu.w):sat +0 0 0 1 1 1 1 0 - - 0 - - - 0 1 P P 0 u u u u u 1 0 0 d d d d d Vd.b=vabs(Vu.b) +0 0 0 1 1 1 1 0 - - 0 - - - 0 1 P P 0 u u u u u 1 0 1 d d d d d Vd.b=vabs(Vu.b):sat +0 0 0 1 1 1 0 0 0 1 0 v v v v v P P 0 u u u u u 0 0 0 d d d d d Vd.w=vadd(Vu.w,Vv.w) +0 0 0 1 1 1 0 0 0 1 0 v v v v v P P 0 u u u u u 0 0 1 d d d d d Vd.ub=vadd(Vu.ub,Vv.ub):sat +0 0 0 1 1 1 0 0 0 1 0 v v v v v P P 0 u u u u u 0 1 0 d d d d d Vd.uh=vadd(Vu.uh,Vv.uh):sat +0 0 0 1 1 1 0 0 0 1 0 v v v v v P P 0 u u u u u 0 1 1 d d d d d Vd.h=vadd(Vu.h,Vv.h):sat +0 0 0 1 1 1 0 0 0 1 0 v v v v v P P 0 u u u u u 1 0 0 d d d d d Vd.w=vadd(Vu.w,Vv.w):sat +0 0 0 1 1 1 0 0 0 1 0 v v v v v P P 0 u u u u u 1 0 1 d d d d d Vd.b=vsub(Vu.b,Vv.b) +0 0 0 1 1 1 0 0 0 1 0 v v v v v P P 0 u u u u u 1 1 0 d d d d d Vd.h=vsub(Vu.h,Vv.h) +0 0 0 1 1 1 0 0 0 1 0 v v v v v P P 0 u u u u u 1 1 1 d d d d d Vd.w=vsub(Vu.w,Vv.w) +0 0 0 1 1 1 0 0 0 1 1 v v v v v P P 0 u u u u u 0 0 0 d d d d d Vd.ub=vsub(Vu.ub,Vv.ub):sat +0 0 0 1 1 1 0 0 0 1 1 v v v v v P P 0 u u u u u 0 0 1 d d d d d Vd.uh=vsub(Vu.uh,Vv.uh):sat +0 0 0 1 1 1 0 0 0 1 1 v v v v v P P 0 u u u u u 0 1 0 d d d d d Vd.h=vsub(Vu.h,Vv.h):sat +0 0 0 1 1 1 0 0 0 1 1 v v v v v P P 0 u u u u u 0 1 1 d d d d d Vd.w=vsub(Vu.w,Vv.w):sat +0 0 0 1 1 1 1 0 1 0 1 v v v v v P P 0 u u u u u 1 0 0 d d d d d Vd.ub=vadd(Vu.ub,Vv.b):sat +0 0 0 1 1 1 1 0 1 0 1 v v v v v P P 0 u u u u u 1 0 1 d d d d d Vd.ub=vsub(Vu.ub,Vv.b):sat +0 0 0 1 1 1 1 1 0 0 0 v v v v v P P 0 u u u u u 0 0 0 d d d d d Vd.b=vadd(Vu.b,Vv.b):sat +0 0 0 1 1 1 1 1 0 0 1 v v v v v P P 0 u u u u u 0 1 0 d d d d d Vd.b=vsub(Vu.b,Vv.b):sat +0 0 0 1 1 1 1 1 0 1 1 v v v v v P P 0 u u u u u 0 0 1 d d d d d Vd.uw=vadd(Vu.uw,Vv.uw):sat +0 0 0 1 1 1 1 1 1 0 1 v v v v v P P 0 u u u u u 1 1 0 d d d d d Vd.b=vadd(Vu.b,Vv.b) +0 0 0 1 1 1 1 1 1 0 1 v v v v v P P 0 u u u u u 1 1 1 d d d d d Vd.h=vadd(Vu.h,Vv.h) +0 0 0 1 1 1 1 1 1 1 0 v v v v v P P 0 u u u u u 1 0 0 d d d d d Vd.uw=vsub(Vu.uw,Vv.uw):sat +0 0 0 1 1 1 0 0 1 0 1 v v v v v P P 1 u u u u u 0 x x d d d d d Vd.w=vadd(Vu.w,Vv.w,Qx4):carry +0 0 0 1 1 1 0 0 1 0 1 v v v v v P P 1 u u u u u 1 x x d d d d d Vd.w=vsub(Vu.w,Vv.w,Qx4):carry +0 0 0 1 1 1 0 1 1 0 0 v v v v v P P 1 u u u u u 0 s s d d d d d Vd.w=vadd(Vu.w,Vv.w,Qs4):carry:sat +0 0 0 1 1 1 0 1 1 0 1 v v v v v P P 1 u u u u u 0 e e d d d d d Vd.w,Qe4=vadd(Vu.w,Vv.w):carry +0 0 0 1 1 1 0 1 1 0 1 v v v v v P P 1 u u u u u 1 e e d d d d d Vd.w,Qe4=vsub(Vu.w,Vv.w):carry +1 1 0 0 0 0 1 0 1 1 0 s s s s s P P - t t t t t - x x d d d d d Rdd=add(Rss,Rtt,Px):carry +1 1 0 0 0 0 1 0 1 1 1 s s s s s P P - t t t t t - x x d d d d d Rdd=sub(Rss,Rtt,Px):carry +0 0 0 1 1 1 0 0 0 0 1 v v v v v P P 0 u u u u u 1 0 1 d d d d d Vd=vand(Vu,Vv) +0 0 0 1 1 1 0 0 0 0 1 v v v v v P P 0 u u u u u 1 1 0 d d d d d Vd=vor(Vu,Vv) +0 0 0 1 1 1 0 0 0 0 1 v v v v v P P 0 u u u u u 1 1 1 d d d d d Vd=vxor(Vu,Vv) +0 0 0 1 1 1 1 0 - - 0 - - - 0 0 P P 0 u u u u u 1 0 0 d d d d d Vd=vnot(Vu) +0 0 0 1 1 0 1 0 0 0 0 - - - - - P P - u u u u u - s s d d d d d if (Ps) Vd=Vu +0 0 0 1 1 0 1 0 0 0 1 - - - - - P P - u u u u u - s s d d d d d if (!Ps) Vd=Vu +0 0 0 1 1 1 1 0 - - 0 - - 0 1 1 P P 1 u u u u u 1 1 1 d d d d d Vd=Vu +0 0 0 1 1 1 1 0 - - 0 - - - 0 1 P P 0 u u u u u 1 1 0 d d d d d Vd.tmp=Vu +0 0 0 1 1 1 1 0 1 0 1 v v v v v P P 0 u u u u u 1 1 1 d d d d d Vdd.tmp=vcombine(Vu,Vv) +0 0 0 1 1 1 0 0 1 1 0 v v v v v P P 0 u u u u u 1 0 0 d d d d d Vd.ub=vavg(Vu.ub,Vv.ub) +0 0 0 1 1 1 0 0 1 1 0 v v v v v P P 0 u u u u u 1 0 1 d d d d d Vd.uh=vavg(Vu.uh,Vv.uh) +0 0 0 1 1 1 0 0 1 1 0 v v v v v P P 0 u u u u u 1 1 0 d d d d d Vd.h=vavg(Vu.h,Vv.h) +0 0 0 1 1 1 0 0 1 1 0 v v v v v P P 0 u u u u u 1 1 1 d d d d d Vd.w=vavg(Vu.w,Vv.w) +0 0 0 1 1 1 0 0 1 1 1 v v v v v P P 0 u u u u u 0 0 0 d d d d d Vd.b=vnavg(Vu.ub,Vv.ub) +0 0 0 1 1 1 0 0 1 1 1 v v v v v P P 0 u u u u u 0 0 1 d d d d d Vd.h=vnavg(Vu.h,Vv.h) +0 0 0 1 1 1 0 0 1 1 1 v v v v v P P 0 u u u u u 0 1 0 d d d d d Vd.w=vnavg(Vu.w,Vv.w) +0 0 0 1 1 1 0 0 1 1 1 v v v v v P P 0 u u u u u 0 1 1 d d d d d Vd.ub=vavg(Vu.ub,Vv.ub):rnd +0 0 0 1 1 1 0 0 1 1 1 v v v v v P P 0 u u u u u 1 0 0 d d d d d Vd.uh=vavg(Vu.uh,Vv.uh):rnd +0 0 0 1 1 1 0 0 1 1 1 v v v v v P P 0 u u u u u 1 0 1 d d d d d Vd.h=vavg(Vu.h,Vv.h):rnd +0 0 0 1 1 1 0 0 1 1 1 v v v v v P P 0 u u u u u 1 1 0 d d d d d Vd.w=vavg(Vu.w,Vv.w):rnd +0 0 0 1 1 1 1 1 0 0 0 v v v v v P P 1 u u u u u 0 1 0 d d d d d Vd.uw=vavg(Vu.uw,Vv.uw) +0 0 0 1 1 1 1 1 0 0 0 v v v v v P P 1 u u u u u 0 1 1 d d d d d Vd.uw=vavg(Vu.uw,Vv.uw):rnd +0 0 0 1 1 1 1 1 0 0 0 v v v v v P P 1 u u u u u 1 0 0 d d d d d Vd.b=vavg(Vu.b,Vv.b) +0 0 0 1 1 1 1 1 0 0 0 v v v v v P P 1 u u u u u 1 0 1 d d d d d Vd.b=vavg(Vu.b,Vv.b):rnd +0 0 0 1 1 1 1 1 0 0 0 v v v v v P P 1 u u u u u 1 1 0 d d d d d Vd.b=vnavg(Vu.b,Vv.b) +0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 0 0 0 0 0 x x Qx4&=vcmp.eq(Vu.b,Vv.b) +0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 0 0 0 0 1 x x Qx4&=vcmp.eq(Vu.h,Vv.h) +0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 0 0 0 1 0 x x Qx4&=vcmp.eq(Vu.w,Vv.w) +0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 0 0 1 0 0 x x Qx4&=vcmp.gt(Vu.b,Vv.b) +0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 0 0 1 0 1 x x Qx4&=vcmp.gt(Vu.h,Vv.h) +0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 0 0 1 1 0 x x Qx4&=vcmp.gt(Vu.w,Vv.w) +0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 0 1 0 0 0 x x Qx4&=vcmp.gt(Vu.ub,Vv.ub) +0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 0 1 0 0 1 x x Qx4&=vcmp.gt(Vu.uh,Vv.uh) +0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 0 1 0 1 0 x x Qx4&=vcmp.gt(Vu.uw,Vv.uw) +0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 0 1 1 0 0 x x Qx4|=vcmp.gt(Vu.sf,Vv.sf) +0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 0 1 1 0 1 x x Qx4|=vcmp.gt(Vu.hf,Vv.hf) +0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 1 0 0 0 0 x x Qx4|=vcmp.eq(Vu.b,Vv.b) +0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 1 0 0 0 1 x x Qx4|=vcmp.eq(Vu.h,Vv.h) +0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 1 0 0 1 0 x x Qx4|=vcmp.eq(Vu.w,Vv.w) +0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 1 0 1 0 0 x x Qx4|=vcmp.gt(Vu.b,Vv.b) +0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 1 0 1 0 1 x x Qx4|=vcmp.gt(Vu.h,Vv.h) +0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 1 0 1 1 0 x x Qx4|=vcmp.gt(Vu.w,Vv.w) +0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 1 1 0 0 0 x x Qx4|=vcmp.gt(Vu.ub,Vv.ub) +0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 1 1 0 0 1 x x Qx4|=vcmp.gt(Vu.uh,Vv.uh) +0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 1 1 0 1 0 x x Qx4|=vcmp.gt(Vu.uw,Vv.uw) +0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 1 1 1 0 0 d d Qd4=vcmp.gt(Vu.sf,Vv.sf) +0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 0 1 1 1 0 1 d d Qd4=vcmp.gt(Vu.hf,Vv.hf) +0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 1 0 0 0 0 0 x x Qx4^=vcmp.eq(Vu.b,Vv.b) +0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 1 0 0 0 0 1 x x Qx4^=vcmp.eq(Vu.h,Vv.h) +0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 1 0 0 0 1 0 x x Qx4^=vcmp.eq(Vu.w,Vv.w) +0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 1 0 0 1 0 0 x x Qx4^=vcmp.gt(Vu.b,Vv.b) +0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 1 0 0 1 0 1 x x Qx4^=vcmp.gt(Vu.h,Vv.h) +0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 1 0 0 1 1 0 x x Qx4^=vcmp.gt(Vu.w,Vv.w) +0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 1 0 1 0 0 0 x x Qx4^=vcmp.gt(Vu.ub,Vv.ub) +0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 1 0 1 0 0 1 x x Qx4^=vcmp.gt(Vu.uh,Vv.uh) +0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 1 0 1 0 1 0 x x Qx4^=vcmp.gt(Vu.uw,Vv.uw) +0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 1 1 0 0 1 0 x x Qx4&=vcmp.gt(Vu.sf,Vv.sf) +0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 1 1 0 0 1 1 x x Qx4&=vcmp.gt(Vu.hf,Vv.hf) +0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 1 1 1 0 1 0 x x Qx4^=vcmp.gt(Vu.sf,Vv.sf) +0 0 0 1 1 1 0 0 1 0 0 v v v v v P P 1 u u u u u 1 1 1 0 1 1 x x Qx4^=vcmp.gt(Vu.hf,Vv.hf) +0 0 0 1 1 1 1 1 1 0 0 v v v v v P P 0 u u u u u 0 0 0 0 0 0 d d Qd4=vcmp.eq(Vu.b,Vv.b) +0 0 0 1 1 1 1 1 1 0 0 v v v v v P P 0 u u u u u 0 0 0 0 0 1 d d Qd4=vcmp.eq(Vu.h,Vv.h) +0 0 0 1 1 1 1 1 1 0 0 v v v v v P P 0 u u u u u 0 0 0 0 1 0 d d Qd4=vcmp.eq(Vu.w,Vv.w) +0 0 0 1 1 1 1 1 1 0 0 v v v v v P P 0 u u u u u 0 0 0 1 0 0 d d Qd4=vcmp.gt(Vu.b,Vv.b) +0 0 0 1 1 1 1 1 1 0 0 v v v v v P P 0 u u u u u 0 0 0 1 0 1 d d Qd4=vcmp.gt(Vu.h,Vv.h) +0 0 0 1 1 1 1 1 1 0 0 v v v v v P P 0 u u u u u 0 0 0 1 1 0 d d Qd4=vcmp.gt(Vu.w,Vv.w) +0 0 0 1 1 1 1 1 1 0 0 v v v v v P P 0 u u u u u 0 0 1 0 0 0 d d Qd4=vcmp.gt(Vu.ub,Vv.ub) +0 0 0 1 1 1 1 1 1 0 0 v v v v v P P 0 u u u u u 0 0 1 0 0 1 d d Qd4=vcmp.gt(Vu.uh,Vv.uh) +0 0 0 1 1 1 1 1 1 0 0 v v v v v P P 0 u u u u u 0 0 1 0 1 0 d d Qd4=vcmp.gt(Vu.uw,Vv.uw) +0 0 0 1 1 1 1 0 v v 0 - - 0 0 1 P P 1 u u u u u 0 0 0 x x x x x if (Qv4) Vx.b+=Vu.b +0 0 0 1 1 1 1 0 v v 0 - - 0 0 1 P P 1 u u u u u 0 0 1 x x x x x if (Qv4) Vx.h+=Vu.h +0 0 0 1 1 1 1 0 v v 0 - - 0 0 1 P P 1 u u u u u 0 1 0 x x x x x if (Qv4) Vx.w+=Vu.w +0 0 0 1 1 1 1 0 v v 0 - - 0 0 1 P P 1 u u u u u 0 1 1 x x x x x if (!Qv4) Vx.b+=Vu.b +0 0 0 1 1 1 1 0 v v 0 - - 0 0 1 P P 1 u u u u u 1 0 0 x x x x x if (!Qv4) Vx.h+=Vu.h +0 0 0 1 1 1 1 0 v v 0 - - 0 0 1 P P 1 u u u u u 1 0 1 x x x x x if (!Qv4) Vx.w+=Vu.w +0 0 0 1 1 1 1 0 v v 0 - - 0 0 1 P P 1 u u u u u 1 1 0 x x x x x if (Qv4) Vx.b-=Vu.b +0 0 0 1 1 1 1 0 v v 0 - - 0 0 1 P P 1 u u u u u 1 1 1 x x x x x if (Qv4) Vx.h-=Vu.h +0 0 0 1 1 1 1 0 v v 0 - - 0 1 0 P P 1 u u u u u 0 0 0 x x x x x if (Qv4) Vx.w-=Vu.w +0 0 0 1 1 1 1 0 v v 0 - - 0 1 0 P P 1 u u u u u 0 0 1 x x x x x if (!Qv4) Vx.b-=Vu.b +0 0 0 1 1 1 1 0 v v 0 - - 0 1 0 P P 1 u u u u u 0 1 0 x x x x x if (!Qv4) Vx.h-=Vu.h +0 0 0 1 1 1 1 0 v v 0 - - 0 1 0 P P 1 u u u u u 0 1 1 x x x x x if (!Qv4) Vx.w-=Vu.w +0 0 0 1 1 1 1 0 1 1 1 v v v v v P P 1 u u u u u - t t d d d d d Vd=vmux(Qt4,Vu,Vv) +0 0 0 1 1 1 0 1 1 0 0 v v v v v P P 1 u u u u u 1 1 1 d d d d d Vd.w=vsatdw(Vu.w,Vv.w) +0 0 0 1 1 1 1 1 0 0 1 v v v v v P P 0 u u u u u 1 1 0 d d d d d Vd.uh=vsat(Vu.uw,Vv.uw) +0 0 0 1 1 1 1 1 0 1 1 v v v v v P P 0 u u u u u 0 1 0 d d d d d Vd.ub=vsat(Vu.h,Vv.h) +0 0 0 1 1 1 1 1 0 1 1 v v v v v P P 0 u u u u u 0 1 1 d d d d d Vd.h=vsat(Vu.w,Vv.w) +0 0 0 1 1 1 1 1 0 1 0 v v v v v P P 0 u u u u u 0 0 1 d d d d d Vd.b=vshuffe(Vu.b,Vv.b) +0 0 0 1 1 1 1 1 0 1 0 v v v v v P P 0 u u u u u 0 1 0 d d d d d Vd.b=vshuffo(Vu.b,Vv.b) +0 0 0 1 1 1 1 1 0 1 0 v v v v v P P 0 u u u u u 0 1 1 d d d d d Vd.h=vshuffe(Vu.h,Vv.h) +0 0 0 1 1 1 1 1 0 1 0 v v v v v P P 0 u u u u u 1 0 0 d d d d d Vd.h=vshuffo(Vu.h,Vv.h) +1 0 0 1 0 0 1 0 0 0 0 s s s s s P P 0 u u u u u 0 0 1 d d d d d Rd=vextract(Vu,Rs) +0 0 1 0 1 1 1 1 0 0 0 t t t t t P P u - - 0 1 0 - - - v v v v v vtmp.h=vgather(Rt,Mu,Vvv.w).h +0 0 1 0 1 1 1 1 0 0 0 t t t t t P P u - - 1 1 0 - s s v v v v v if (Qs4) vtmp.h=vgather(Rt,Mu,Vvv.w).h +0 0 1 0 1 1 1 1 0 0 0 t t t t t P P u - - 0 0 0 - - - v v v v v vtmp.w=vgather(Rt,Mu,Vv.w).w +0 0 1 0 1 1 1 1 0 0 0 t t t t t P P u - - 0 0 1 - - - v v v v v vtmp.h=vgather(Rt,Mu,Vv.h).h +0 0 1 0 1 1 1 1 0 0 0 t t t t t P P u - - 1 0 0 - s s v v v v v if (Qs4) vtmp.w=vgather(Rt,Mu,Vv.w).w +0 0 1 0 1 1 1 1 0 0 0 t t t t t P P u - - 1 0 1 - s s v v v v v if (Qs4) vtmp.h=vgather(Rt,Mu,Vv.h).h +0 0 1 0 1 0 0 0 0 0 0 t t t t t P P i 0 0 i i i 0 0 0 d d d d d Vd=vmem(Rt+#s4) +0 0 1 0 1 0 0 0 0 1 0 t t t t t P P i 0 0 i i i 0 0 0 d d d d d Vd=vmem(Rt+#s4):nt +0 0 1 0 1 0 0 0 1 0 0 t t t t t P P i v v i i i 0 1 0 d d d d d if (Pv) Vd=vmem(Rt+#s4) +0 0 1 0 1 0 0 0 1 0 0 t t t t t P P i v v i i i 0 1 1 d d d d d if (!Pv) Vd=vmem(Rt+#s4) +0 0 1 0 1 0 0 0 1 1 0 t t t t t P P i v v i i i 0 1 0 d d d d d if (Pv) Vd=vmem(Rt+#s4):nt +0 0 1 0 1 0 0 0 1 1 0 t t t t t P P i v v i i i 0 1 1 d d d d d if (!Pv) Vd=vmem(Rt+#s4):nt +0 0 1 0 1 0 0 1 0 0 0 x x x x x P P - 0 0 i i i 0 0 0 d d d d d Vd=vmem(Rx++#s3) +0 0 1 0 1 0 0 1 0 1 0 x x x x x P P - 0 0 i i i 0 0 0 d d d d d Vd=vmem(Rx++#s3):nt +0 0 1 0 1 0 0 1 1 0 0 x x x x x P P - v v i i i 0 1 0 d d d d d if (Pv) Vd=vmem(Rx++#s3) +0 0 1 0 1 0 0 1 1 0 0 x x x x x P P - v v i i i 0 1 1 d d d d d if (!Pv) Vd=vmem(Rx++#s3) +0 0 1 0 1 0 0 1 1 1 0 x x x x x P P - v v i i i 0 1 0 d d d d d if (Pv) Vd=vmem(Rx++#s3):nt +0 0 1 0 1 0 0 1 1 1 0 x x x x x P P - v v i i i 0 1 1 d d d d d if (!Pv) Vd=vmem(Rx++#s3):nt +0 0 1 0 1 0 1 1 0 0 0 x x x x x P P u 0 0 - - - 0 0 0 d d d d d Vd=vmem(Rx++Mu) +0 0 1 0 1 0 1 1 0 1 0 x x x x x P P u 0 0 - - - 0 0 0 d d d d d Vd=vmem(Rx++Mu):nt +0 0 1 0 1 0 1 1 1 0 0 x x x x x P P u v v - - - 0 1 0 d d d d d if (Pv) Vd=vmem(Rx++Mu) +0 0 1 0 1 0 1 1 1 0 0 x x x x x P P u v v - - - 0 1 1 d d d d d if (!Pv) Vd=vmem(Rx++Mu) +0 0 1 0 1 0 1 1 1 1 0 x x x x x P P u v v - - - 0 1 0 d d d d d if (Pv) Vd=vmem(Rx++Mu):nt +0 0 1 0 1 0 1 1 1 1 0 x x x x x P P u v v - - - 0 1 1 d d d d d if (!Pv) Vd=vmem(Rx++Mu):nt +0 0 1 0 1 0 0 0 0 0 0 t t t t t P P i 0 0 i i i 0 0 1 d d d d d Vd.cur=vmem(Rt+#s4) +0 0 1 0 1 0 0 0 0 1 0 t t t t t P P i 0 0 i i i 0 0 1 d d d d d Vd.cur=vmem(Rt+#s4):nt +0 0 1 0 1 0 0 0 1 0 0 t t t t t P P i v v i i i 1 0 0 d d d d d if (Pv) Vd.cur=vmem(Rt+#s4) +0 0 1 0 1 0 0 0 1 0 0 t t t t t P P i v v i i i 1 0 1 d d d d d if (!Pv) Vd.cur=vmem(Rt+#s4) +0 0 1 0 1 0 0 0 1 1 0 t t t t t P P i v v i i i 1 0 0 d d d d d if (Pv) Vd.cur=vmem(Rt+#s4):nt +0 0 1 0 1 0 0 0 1 1 0 t t t t t P P i v v i i i 1 0 1 d d d d d if (!Pv) Vd.cur=vmem(Rt+#s4):nt +0 0 1 0 1 0 0 1 0 0 0 x x x x x P P - 0 0 i i i 0 0 1 d d d d d Vd.cur=vmem(Rx++#s3) +0 0 1 0 1 0 0 1 0 1 0 x x x x x P P - 0 0 i i i 0 0 1 d d d d d Vd.cur=vmem(Rx++#s3):nt +0 0 1 0 1 0 0 1 1 0 0 x x x x x P P - v v i i i 1 0 0 d d d d d if (Pv) Vd.cur=vmem(Rx++#s3) +0 0 1 0 1 0 0 1 1 0 0 x x x x x P P - v v i i i 1 0 1 d d d d d if (!Pv) Vd.cur=vmem(Rx++#s3) +0 0 1 0 1 0 0 1 1 1 0 x x x x x P P - v v i i i 1 0 0 d d d d d if (Pv) Vd.cur=vmem(Rx++#s3):nt +0 0 1 0 1 0 0 1 1 1 0 x x x x x P P - v v i i i 1 0 1 d d d d d if (!Pv) Vd.cur=vmem(Rx++#s3):nt +0 0 1 0 1 0 1 1 0 0 0 x x x x x P P u 0 0 - - - 0 0 1 d d d d d Vd.cur=vmem(Rx++Mu) +0 0 1 0 1 0 1 1 0 1 0 x x x x x P P u 0 0 - - - 0 0 1 d d d d d Vd.cur=vmem(Rx++Mu):nt +0 0 1 0 1 0 1 1 1 0 0 x x x x x P P u v v - - - 1 0 0 d d d d d if (Pv) Vd.cur=vmem(Rx++Mu) +0 0 1 0 1 0 1 1 1 0 0 x x x x x P P u v v - - - 1 0 1 d d d d d if (!Pv) Vd.cur=vmem(Rx++Mu) +0 0 1 0 1 0 1 1 1 1 0 x x x x x P P u v v - - - 1 0 0 d d d d d if (Pv) Vd.cur=vmem(Rx++Mu):nt +0 0 1 0 1 0 1 1 1 1 0 x x x x x P P u v v - - - 1 0 1 d d d d d if (!Pv) Vd.cur=vmem(Rx++Mu):nt +0 0 1 0 1 0 0 0 0 0 0 t t t t t P P i 0 0 i i i 0 1 0 d d d d d Vd.tmp=vmem(Rt+#s4) +0 0 1 0 1 0 0 0 0 1 0 t t t t t P P i 0 0 i i i 0 1 0 d d d d d Vd.tmp=vmem(Rt+#s4):nt +0 0 1 0 1 0 0 0 1 0 0 t t t t t P P i v v i i i 1 1 0 d d d d d if (Pv) Vd.tmp=vmem(Rt+#s4) +0 0 1 0 1 0 0 0 1 0 0 t t t t t P P i v v i i i 1 1 1 d d d d d if (!Pv) Vd.tmp=vmem(Rt+#s4) +0 0 1 0 1 0 0 0 1 1 0 t t t t t P P i v v i i i 1 1 0 d d d d d if (Pv) Vd.tmp=vmem(Rt+#s4):nt +0 0 1 0 1 0 0 0 1 1 0 t t t t t P P i v v i i i 1 1 1 d d d d d if (!Pv) Vd.tmp=vmem(Rt+#s4):nt +0 0 1 0 1 0 0 1 0 0 0 x x x x x P P - 0 0 i i i 0 1 0 d d d d d Vd.tmp=vmem(Rx++#s3) +0 0 1 0 1 0 0 1 0 1 0 x x x x x P P - 0 0 i i i 0 1 0 d d d d d Vd.tmp=vmem(Rx++#s3):nt +0 0 1 0 1 0 0 1 1 0 0 x x x x x P P - v v i i i 1 1 0 d d d d d if (Pv) Vd.tmp=vmem(Rx++#s3) +0 0 1 0 1 0 0 1 1 0 0 x x x x x P P - v v i i i 1 1 1 d d d d d if (!Pv) Vd.tmp=vmem(Rx++#s3) +0 0 1 0 1 0 0 1 1 1 0 x x x x x P P - v v i i i 1 1 0 d d d d d if (Pv) Vd.tmp=vmem(Rx++#s3):nt +0 0 1 0 1 0 0 1 1 1 0 x x x x x P P - v v i i i 1 1 1 d d d d d if (!Pv) Vd.tmp=vmem(Rx++#s3):nt +0 0 1 0 1 0 1 1 0 0 0 x x x x x P P u 0 0 - - - 0 1 0 d d d d d Vd.tmp=vmem(Rx++Mu) +0 0 1 0 1 0 1 1 0 1 0 x x x x x P P u 0 0 - - - 0 1 0 d d d d d Vd.tmp=vmem(Rx++Mu):nt +0 0 1 0 1 0 1 1 1 0 0 x x x x x P P u v v - - - 1 1 0 d d d d d if (Pv) Vd.tmp=vmem(Rx++Mu) +0 0 1 0 1 0 1 1 1 0 0 x x x x x P P u v v - - - 1 1 1 d d d d d if (!Pv) Vd.tmp=vmem(Rx++Mu) +0 0 1 0 1 0 1 1 1 1 0 x x x x x P P u v v - - - 1 1 0 d d d d d if (Pv) Vd.tmp=vmem(Rx++Mu):nt +0 0 1 0 1 0 1 1 1 1 0 x x x x x P P u v v - - - 1 1 1 d d d d d if (!Pv) Vd.tmp=vmem(Rx++Mu):nt +0 0 1 0 1 0 0 0 0 0 0 t t t t t P P i 0 0 i i i 1 1 1 d d d d d Vd=vmemu(Rt+#s4) +0 0 1 0 1 0 0 1 0 0 0 x x x x x P P - 0 0 i i i 1 1 1 d d d d d Vd=vmemu(Rx++#s3) +0 0 1 0 1 0 1 1 0 0 0 x x x x x P P u 0 0 - - - 1 1 1 d d d d d Vd=vmemu(Rx++Mu) +0 0 0 1 1 1 1 1 0 0 1 v v v v v P P 1 u u u u u 0 i i x x x x x Vxx.w+=v6mpy(Vuu.ub,Vvv.b,#u2):v +0 0 0 1 1 1 1 1 0 0 1 v v v v v P P 1 u u u u u 1 i i x x x x x Vxx.w+=v6mpy(Vuu.ub,Vvv.b,#u2):h +0 0 0 1 1 1 1 1 0 1 0 v v v v v P P 1 u u u u u 0 i i d d d d d Vdd.w=v6mpy(Vuu.ub,Vvv.b,#u2):v +0 0 0 1 1 1 1 1 0 1 0 v v v v v P P 1 u u u u u 1 i i d d d d d Vdd.w=v6mpy(Vuu.ub,Vvv.b,#u2):h +0 0 0 1 1 1 0 0 0 0 1 v v v v v P P 1 u u u u u 0 1 0 x x x x x Vxx.w+=vadd(Vu.h,Vv.h) +0 0 0 1 1 1 0 0 0 1 0 v v v v v P P 1 u u u u u 1 0 0 x x x x x Vxx.w+=vadd(Vu.uh,Vv.uh) +0 0 0 1 1 1 0 0 0 1 0 v v v v v P P 1 u u u u u 1 0 1 x x x x x Vxx.h+=vadd(Vu.ub,Vv.ub) +0 0 0 1 1 1 0 0 1 0 1 v v v v v P P 0 u u u u u 0 1 0 d d d d d Vdd.h=vadd(Vu.ub,Vv.ub) +0 0 0 1 1 1 0 0 1 0 1 v v v v v P P 0 u u u u u 0 1 1 d d d d d Vdd.w=vadd(Vu.uh,Vv.uh) +0 0 0 1 1 1 0 0 1 0 1 v v v v v P P 0 u u u u u 1 0 0 d d d d d Vdd.w=vadd(Vu.h,Vv.h) +0 0 0 1 1 1 0 0 1 0 1 v v v v v P P 0 u u u u u 1 0 1 d d d d d Vdd.h=vsub(Vu.ub,Vv.ub) +0 0 0 1 1 1 0 0 1 0 1 v v v v v P P 0 u u u u u 1 1 0 d d d d d Vdd.w=vsub(Vu.uh,Vv.uh) +0 0 0 1 1 1 0 0 1 0 1 v v v v v P P 0 u u u u u 1 1 1 d d d d d Vdd.w=vsub(Vu.h,Vv.h) +0 0 0 1 1 0 0 1 0 0 0 t t t t t P P 0 u u u u u 1 1 1 d d d d d Vdd.h=vdmpy(Vuu.ub,Rt.b) +0 0 0 1 1 0 0 1 0 0 0 t t t t t P P 1 u u u u u 1 1 1 x x x x x Vxx.h+=vdmpy(Vuu.ub,Rt.b) +0 0 0 1 1 0 0 1 0 0 1 t t t t t P P 0 u u u u u 0 0 1 d d d d d Vd.w=vdmpy(Vuu.h,Rt.uh,#1):sat +0 0 0 1 1 0 0 1 0 0 1 t t t t t P P 0 u u u u u 0 1 1 d d d d d Vd.w=vdmpy(Vuu.h,Rt.h):sat +0 0 0 1 1 0 0 1 0 0 1 t t t t t P P 0 u u u u u 1 0 0 d d d d d Vdd.w=vdmpy(Vuu.h,Rt.b) +0 0 0 1 1 0 0 1 0 0 1 t t t t t P P 1 u u u u u 0 0 1 x x x x x Vx.w+=vdmpy(Vuu.h,Rt.uh,#1):sat +0 0 0 1 1 0 0 1 0 0 1 t t t t t P P 1 u u u u u 0 1 0 x x x x x Vx.w+=vdmpy(Vuu.h,Rt.h):sat +0 0 0 1 1 0 0 1 0 0 1 t t t t t P P 1 u u u u u 1 0 0 x x x x x Vxx.w+=vdmpy(Vuu.h,Rt.b) +0 0 0 1 1 1 0 0 0 0 0 v v v v v P P 1 u u u u u 0 1 1 x x x x x Vx.w+=vdmpy(Vu.h,Vv.h):sat +0 0 0 1 1 0 0 1 0 1 1 t t t t t P P 0 u u u u u 1 0 0 d d d d d Vd.h=vlut4(Vu.uh,Rtt.h) +0 0 0 1 1 0 0 1 1 0 0 t t t t t P P 1 u u u u u 1 0 0 x x x x x Vx.h=vmpa(Vx.h,Vu.h,Rtt.h):sat +0 0 0 1 1 0 0 1 1 0 0 t t t t t P P 1 u u u u u 1 0 1 x x x x x Vx.h=vmpa(Vx.h,Vu.uh,Rtt.uh):sat +0 0 0 1 1 0 0 1 1 0 0 t t t t t P P 1 u u u u u 1 1 0 x x x x x Vx.h=vmps(Vx.h,Vu.uh,Rtt.uh):sat +0 0 0 1 1 0 0 1 0 0 1 t t t t t P P 0 u u u u u 1 1 0 d d d d d Vdd.h=vmpa(Vuu.ub,Rt.b) +0 0 0 1 1 0 0 1 0 0 1 t t t t t P P 0 u u u u u 1 1 1 d d d d d Vdd.w=vmpa(Vuu.h,Rt.b) +0 0 0 1 1 0 0 1 0 0 1 t t t t t P P 1 u u u u u 1 1 0 x x x x x Vxx.h+=vmpa(Vuu.ub,Rt.b) +0 0 0 1 1 0 0 1 0 0 1 t t t t t P P 1 u u u u u 1 1 1 x x x x x Vxx.w+=vmpa(Vuu.h,Rt.b) +0 0 0 1 1 0 0 1 0 1 1 t t t t t P P 0 u u u u u 0 1 1 d d d d d Vdd.h=vmpa(Vuu.ub,Rt.ub) +0 0 0 1 1 0 0 1 1 0 0 t t t t t P P 0 u u u u u 1 0 1 d d d d d Vdd.w=vmpa(Vuu.uh,Rt.b) +0 0 0 1 1 0 0 1 1 0 0 t t t t t P P 1 u u u u u 0 1 0 x x x x x Vxx.w+=vmpa(Vuu.uh,Rt.b) +0 0 0 1 1 0 0 1 1 0 1 t t t t t P P 1 u u u u u 1 0 0 x x x x x Vxx.h+=vmpa(Vuu.ub,Rt.ub) +0 0 0 1 1 1 0 0 0 0 1 v v v v v P P 0 u u u u u 0 1 1 d d d d d Vdd.h=vmpa(Vuu.ub,Vvv.b) +0 0 0 1 1 1 0 0 1 1 1 v v v v v P P 0 u u u u u 1 1 1 d d d d d Vdd.h=vmpa(Vuu.ub,Vvv.ub) +0 0 0 1 1 0 0 1 0 0 1 t t t t t P P 0 u u u u u 1 0 1 d d d d d Vdd.h=vmpy(Vu.ub,Rt.b) +0 0 0 1 1 0 0 1 0 0 1 t t t t t P P 1 u u u u u 1 0 1 x x x x x Vxx.h+=vmpy(Vu.ub,Rt.b) +0 0 0 1 1 0 0 1 0 1 0 t t t t t P P 0 u u u u u 0 0 0 d d d d d Vdd.w=vmpy(Vu.h,Rt.h) +0 0 0 1 1 0 0 1 0 1 0 t t t t t P P 0 u u u u u 0 1 1 d d d d d Vdd.uw=vmpy(Vu.uh,Rt.uh) +0 0 0 1 1 0 0 1 0 1 0 t t t t t P P 1 u u u u u 0 0 0 x x x x x Vxx.w+=vmpy(Vu.h,Rt.h):sat +0 0 0 1 1 0 0 1 0 1 0 t t t t t P P 1 u u u u u 0 0 1 x x x x x Vxx.uw+=vmpy(Vu.uh,Rt.uh) +0 0 0 1 1 0 0 1 1 0 0 t t t t t P P 1 u u u u u 0 0 0 x x x x x Vxx.uh+=vmpy(Vu.ub,Rt.ub) +0 0 0 1 1 0 0 1 1 0 1 t t t t t P P 1 u u u u u 1 1 0 x x x x x Vxx.w+=vmpy(Vu.h,Rt.h) +0 0 0 1 1 0 0 1 1 1 0 t t t t t P P 0 u u u u u 0 0 0 d d d d d Vdd.uh=vmpy(Vu.ub,Rt.ub) +0 0 0 1 1 1 0 0 0 0 0 v v v v v P P 0 u u u u u 1 0 0 d d d d d Vdd.h=vmpy(Vu.b,Vv.b) +0 0 0 1 1 1 0 0 0 0 0 v v v v v P P 0 u u u u u 1 0 1 d d d d d Vdd.uh=vmpy(Vu.ub,Vv.ub) +0 0 0 1 1 1 0 0 0 0 0 v v v v v P P 0 u u u u u 1 1 0 d d d d d Vdd.h=vmpy(Vu.ub,Vv.b) +0 0 0 1 1 1 0 0 0 0 0 v v v v v P P 1 u u u u u 1 0 0 x x x x x Vxx.h+=vmpy(Vu.b,Vv.b) +0 0 0 1 1 1 0 0 0 0 0 v v v v v P P 1 u u u u u 1 0 1 x x x x x Vxx.uh+=vmpy(Vu.ub,Vv.ub) +0 0 0 1 1 1 0 0 0 0 0 v v v v v P P 1 u u u u u 1 1 0 x x x x x Vxx.h+=vmpy(Vu.ub,Vv.b) +0 0 0 1 1 1 0 0 0 0 1 v v v v v P P 0 u u u u u 0 0 0 d d d d d Vdd.uw=vmpy(Vu.uh,Vv.uh) +0 0 0 1 1 1 0 0 0 0 1 v v v v v P P 1 u u u u u 0 0 0 x x x x x Vxx.uw+=vmpy(Vu.uh,Vv.uh) +0 0 0 1 1 1 1 1 1 0 0 v v v v v P P 1 u u u u u 0 0 0 d d d d d Vdd.qf32=vmpy(Vu.qf16,Vv.hf) +0 0 0 1 1 1 1 1 1 1 1 v v v v v P P 1 u u u u u 0 1 1 d d d d d Vd.qf16=vmpy(Vu.qf16,Vv.qf16) +0 0 0 1 1 1 1 1 1 1 1 v v v v v P P 1 u u u u u 1 0 0 d d d d d Vd.qf16=vmpy(Vu.hf,Vv.hf) +0 0 0 1 1 1 1 1 1 1 1 v v v v v P P 1 u u u u u 1 0 1 d d d d d Vd.qf16=vmpy(Vu.qf16,Vv.hf) +0 0 0 1 1 1 1 1 1 1 1 v v v v v P P 1 u u u u u 1 1 0 d d d d d Vdd.qf32=vmpy(Vu.qf16,Vv.qf16) +0 0 0 1 1 1 1 1 1 1 1 v v v v v P P 1 u u u u u 1 1 1 d d d d d Vdd.qf32=vmpy(Vu.hf,Vv.hf) +0 0 0 1 1 1 0 0 0 0 1 v v v v v P P 0 u u u u u 1 0 0 d d d d d Vd.h=vmpyi(Vu.h,Vv.h) +0 0 0 1 1 1 0 0 0 0 1 v v v v v P P 1 u u u u u 1 0 0 x x x x x Vx.h+=vmpyi(Vu.h,Vv.h) +0 0 0 1 1 1 0 0 0 0 1 v v v v v P P 1 u u u u u 1 0 1 x x x x x Vx.w+=vmpyie(Vu.w,Vv.uh) +0 0 0 1 1 1 0 0 0 1 0 v v v v v P P 1 u u u u u 0 0 0 x x x x x Vx.w+=vmpyie(Vu.w,Vv.h) +0 0 0 1 1 1 1 1 1 1 0 v v v v v P P 0 u u u u u 0 0 0 d d d d d Vd.w=vmpyie(Vu.w,Vv.uh) +0 0 0 1 1 1 1 1 1 1 0 v v v v v P P 0 u u u u u 0 0 1 d d d d d Vd.w=vmpyio(Vu.w,Vv.h) +0 0 0 1 1 0 0 1 0 1 0 t t t t t P P 1 u u u u u 0 1 1 x x x x x Vx.w+=vmpyi(Vu.w,Rt.h) +0 0 0 1 1 0 0 1 1 0 0 t t t t t P P 0 u u u u u 1 1 1 d d d d d Vd.w=vmpyi(Vu.w,Rt.h) +0 0 0 1 1 1 1 1 1 1 1 v v v v v P P 1 u u u u u 0 0 0 d d d d d Vd.qf32=vmpy(Vu.qf32,Vv.qf32) +0 0 0 1 1 1 1 1 1 1 1 v v v v v P P 1 u u u u u 0 0 1 d d d d d Vd.qf32=vmpy(Vu.sf,Vv.sf) +0 0 0 1 1 1 0 0 0 0 1 v v v v v P P 1 u u u u u 0 1 1 x x x x x Vxx+=vmpyo(Vu.w,Vv.h) +0 0 0 1 1 1 0 0 0 0 1 v v v v v P P 1 u u u u u 1 1 0 x x x x x Vx.w+=vmpyo(Vu.w,Vv.h):<<1:sat:shift +0 0 0 1 1 1 0 0 0 0 1 v v v v v P P 1 u u u u u 1 1 1 x x x x x Vx.w+=vmpyo(Vu.w,Vv.h):<<1:rnd:sat:shift +0 0 0 1 1 1 1 0 1 0 1 v v v v v P P 0 u u u u u 1 1 0 d d d d d Vdd=vmpye(Vu.w,Vv.uh) +0 0 0 1 1 1 1 1 0 1 0 v v v v v P P 0 u u u u u 0 0 0 d d d d d Vd.w=vmpyo(Vu.w,Vv.h):<<1:rnd:sat +0 0 0 1 1 1 1 1 1 1 1 v v v v v P P 0 u u u u u 1 0 1 d d d d d Vd.w=vmpye(Vu.w,Vv.uh) +0 0 0 1 1 1 1 1 1 1 1 v v v v v P P 0 u u u u u 1 1 1 d d d d d Vd.w=vmpyo(Vu.w,Vv.h):<<1:sat +0 0 0 1 1 0 0 1 0 1 0 t t t t t P P 0 u u u u u 1 0 i d d d d d Vdd.w=vrmpy(Vuu.ub,Rt.b,#u1) +0 0 0 1 1 0 0 1 0 1 0 t t t t t P P 1 u u u u u 1 0 i x x x x x Vxx.w+=vrmpy(Vuu.ub,Rt.b,#u1) +0 0 0 1 1 0 0 1 0 1 1 t t t t t P P 1 u u u u u 1 1 i x x x x x Vxx.uw+=vrmpy(Vuu.ub,Rt.ub,#u1) +0 0 0 1 1 0 0 1 1 0 1 t t t t t P P 0 u u u u u 1 1 i d d d d d Vdd.uw=vrmpy(Vuu.ub,Rt.ub,#u1) +0 0 0 1 1 1 0 0 0 0 0 v v v v v P P 1 u u u u u 0 0 0 x x x x x Vx.uw+=vrmpy(Vu.ub,Vv.ub) +0 0 0 1 1 1 0 0 0 0 0 v v v v v P P 1 u u u u u 0 0 1 x x x x x Vx.w+=vrmpy(Vu.b,Vv.b) +0 0 0 1 1 1 0 0 0 0 0 v v v v v P P 1 u u u u u 0 1 0 x x x x x Vx.w+=vrmpy(Vu.ub,Vv.b) +0 0 0 1 1 0 0 1 0 0 0 t t t t t P P 0 u u u u u 0 0 0 d d d d d Vdd.h=vtmpy(Vuu.b,Rt.b) +0 0 0 1 1 0 0 1 0 0 0 t t t t t P P 0 u u u u u 0 0 1 d d d d d Vdd.h=vtmpy(Vuu.ub,Rt.b) +0 0 0 1 1 0 0 1 0 0 0 t t t t t P P 1 u u u u u 0 0 0 x x x x x Vxx.h+=vtmpy(Vuu.b,Rt.b) +0 0 0 1 1 0 0 1 0 0 0 t t t t t P P 1 u u u u u 0 0 1 x x x x x Vxx.h+=vtmpy(Vuu.ub,Rt.b) +0 0 0 1 1 0 0 1 0 0 0 t t t t t P P 1 u u u u u 0 1 0 x x x x x Vxx.w+=vtmpy(Vuu.h,Rt.b) +0 0 0 1 1 0 0 1 1 0 1 t t t t t P P 0 u u u u u 1 0 0 d d d d d Vdd.w=vtmpy(Vuu.h,Rt.b) +0 0 0 1 1 0 0 1 0 0 0 t t t t t P P 0 u u u u u 1 0 1 d d d d d Vdd.uw=vdsad(Vuu.uh,Rt.uh) +0 0 0 1 1 0 0 1 0 1 1 t t t t t P P 1 u u u u u 0 0 0 x x x x x Vxx.uw+=vdsad(Vuu.uh,Rt.uh) +0 0 0 1 1 0 0 1 0 1 0 t t t t t P P 0 u u u u u 1 1 i d d d d d Vdd.uw=vrsad(Vuu.ub,Rt.ub,#u1) +0 0 0 1 1 0 0 1 0 1 0 t t t t t P P 1 u u u u u 1 1 i x x x x x Vxx.uw+=vrsad(Vuu.ub,Rt.ub,#u1) +0 0 0 1 1 0 0 1 0 0 0 t t t t t P P 0 u u u u u 0 1 0 d d d d d Vd.w=vdmpy(Vu.h,Rt.b) +0 0 0 1 1 0 0 1 0 0 0 t t t t t P P 0 u u u u u 1 1 0 d d d d d Vd.h=vdmpy(Vu.ub,Rt.b) +0 0 0 1 1 0 0 1 0 0 0 t t t t t P P 1 u u u u u 0 1 1 x x x x x Vx.w+=vdmpy(Vu.h,Rt.b) +0 0 0 1 1 0 0 1 0 0 0 t t t t t P P 1 u u u u u 1 1 0 x x x x x Vx.h+=vdmpy(Vu.ub,Rt.b) +0 0 0 1 1 0 0 1 0 0 1 t t t t t P P 0 u u u u u 0 0 0 d d d d d Vd.w=vdmpy(Vu.h,Rt.uh):sat +0 0 0 1 1 0 0 1 0 0 1 t t t t t P P 0 u u u u u 0 1 0 d d d d d Vd.w=vdmpy(Vu.h,Rt.h):sat +0 0 0 1 1 0 0 1 0 0 1 t t t t t P P 1 u u u u u 0 0 0 x x x x x Vx.w+=vdmpy(Vu.h,Rt.uh):sat +0 0 0 1 1 0 0 1 0 0 1 t t t t t P P 1 u u u u u 0 1 1 x x x x x Vx.w+=vdmpy(Vu.h,Rt.h):sat +0 0 0 1 1 1 0 0 0 0 0 v v v v v P P 0 u u u u u 0 1 1 d d d d d Vd.w=vdmpy(Vu.h,Vv.h):sat +0 0 0 1 1 0 0 1 0 1 0 t t t t t P P 0 u u u u u 0 0 1 d d d d d Vd.h=vmpy(Vu.h,Rt.h):<<1:sat +0 0 0 1 1 0 0 1 0 1 0 t t t t t P P 0 u u u u u 0 1 0 d d d d d Vd.h=vmpy(Vu.h,Rt.h):<<1:md:sat +0 0 0 1 1 1 1 1 1 1 0 v v v v v P P 1 u u u u u 1 1 1 d d d d d Vd.uh=vmpy(Vu.uh,Vv.uh):>>16 +0 0 0 1 1 1 1 1 0 1 1 v v v v v P P 0 u u u u u 0 0 0 d d d d d Vd.w=vmpyieo(Vu.h,Vv.h) +0 0 0 1 1 0 0 1 0 1 0 t t t t t P P 1 u u u u u 0 1 0 x x x x x Vx.w+=vmpyi(Vu.w,Rt.b) +0 0 0 1 1 0 0 1 0 1 1 t t t t t P P 0 u u u u u 0 0 0 d d d d d Vd.h=vmpyi(Vu.h,Rt.b) +0 0 0 1 1 0 0 1 0 1 1 t t t t t P P 1 u u u u u 0 0 1 x x x x x Vx.h+=vmpyi(Vu.h,Rt.b) +0 0 0 1 1 0 0 1 1 0 0 t t t t t P P 0 u u u u u 1 1 0 d d d d d Vd.w=vmpyi(Vu.w,Rt.ub) +0 0 0 1 1 0 0 1 1 0 0 t t t t t P P 1 u u u u u 0 0 1 x x x x x Vx.w+=vmpyi(Vu.w,Rt.ub) +0 0 0 1 1 0 0 1 1 0 1 t t t t t P P 0 u u u u u 0 0 0 d d d d d Vd.w=vmpyi(Vu.w,Rt.b) +0 0 0 1 1 0 0 1 0 1 1 t t t t t P P 0 u u u u u 0 1 0 d d d d d Vd.uw=vmpye(Vu.uh,Rt.uh) +0 0 0 1 1 0 0 1 1 0 0 t t t t t P P 1 u u u u u 0 1 1 x x x x x Vx.uw+=vmpye(Vu.uh,Rt.uh) +0 0 0 1 1 0 0 1 0 0 0 t t t t t P P 0 u u u u u 0 1 1 d d d d d Vd.uw=vrmpy(Vu.ub,Rt.ub) +0 0 0 1 1 0 0 1 0 0 0 t t t t t P P 0 u u u u u 1 0 0 d d d d d Vd.w=vrmpy(Vu.ub,Rt.b) +0 0 0 1 1 0 0 1 0 0 0 t t t t t P P 1 u u u u u 1 0 0 x x x x x Vx.uw+=vrmpy(Vu.ub,Rt.ub) +0 0 0 1 1 0 0 1 0 0 0 t t t t t P P 1 u u u u u 1 0 1 x x x x x Vx.w+=vrmpy(Vu.ub,Rt.b) +0 0 0 1 1 1 0 0 0 0 0 v v v v v P P 0 u u u u u 0 0 0 d d d d d Vd.uw=vrmpy(Vu.ub,Vv.ub) +0 0 0 1 1 1 0 0 0 0 0 v v v v v P P 0 u u u u u 0 0 1 d d d d d Vd.w=vrmpy(Vu.b,Vv.b) +0 0 0 1 1 1 0 0 0 0 0 v v v v v P P 0 u u u u u 0 1 0 d d d d d Vd.w=vrmpy(Vu.ub,Vv.b) +0 0 0 1 1 0 0 1 1 0 1 t t t t t P P 0 - - - - 0 0 0 1 d d d d d Vd=vsplat(Rt) +0 0 0 1 1 0 0 1 1 1 0 t t t t t P P 0 - - - - - 0 0 1 d d d d d Vd.h=vsplat(Rt) +0 0 0 1 1 0 0 1 1 1 0 t t t t t P P 0 - - - - - 0 1 0 d d d d d Vd.b=vsplat(Rt) +0 0 0 1 1 0 0 1 0 1 1 t t t t t P P 1 u u u u u 1 0 0 - - - x x Qx4|=vand(Vu,Rt) +0 0 0 1 1 0 0 1 1 0 1 t t t t t P P 0 u u u u u 0 1 0 - 1 0 d d Qd4=vand(Vu,Rt) +0 0 0 1 1 0 0 1 0 1 1 t t t t t P P 1 - - 0 u u 0 1 1 x x x x x Vx|=vand(Qu4,Rt) +0 0 0 1 1 0 0 1 0 1 1 t t t t t P P 1 - - 1 u u 0 1 1 x x x x x Vx|=vand(!Qu4,Rt) +0 0 0 1 1 0 0 1 1 0 1 t t t t t P P 0 - - 0 u u 1 0 1 d d d d d Vd=vand(Qu4,Rt) +0 0 0 1 1 0 0 1 1 0 1 t t t t t P P 0 - - 1 u u 1 0 1 d d d d d Vd=vand(!Qu4,Rt) +0 0 0 1 1 1 0 0 1 1 0 v v v v v P P 0 u u u u u 0 0 0 d d d d d Vd.ub=vabsdiff(Vu.ub,Vv.ub) +0 0 0 1 1 1 0 0 1 1 0 v v v v v P P 0 u u u u u 0 0 1 d d d d d Vd.uh=vabsdiff(Vu.h,Vv.h) +0 0 0 1 1 1 0 0 1 1 0 v v v v v P P 0 u u u u u 0 1 0 d d d d d Vd.uh=vabsdiff(Vu.uh,Vv.uh) +0 0 0 1 1 1 0 0 1 1 0 v v v v v P P 0 u u u u u 0 1 1 d d d d d Vd.uw=vabsdiff(Vu.w,Vv.w) +0 0 0 1 1 0 0 1 1 0 1 t t t t t P P 1 - - - - - 0 0 1 x x x x x Vx.w=vinsert(Rt) +0 0 0 1 1 0 0 1 0 1 1 t t t t t P P 0 u u u u u 0 0 1 d d d d d Vd=vror(Vu,Rt) +0 0 0 1 1 0 1 1 v v v v v t t t P P 0 u u u u u 0 0 0 d d d d d Vd=valign(Vu,Vv,Rt) +0 0 0 1 1 0 1 1 v v v v v t t t P P 0 u u u u u 0 0 1 d d d d d Vd=vlalign(Vu,Vv,Rt) +0 0 0 1 1 1 1 0 0 0 1 v v v v v P P 1 u u u u u i i i d d d d d Vd=valign(Vu,Vv,#u3) +0 0 0 1 1 1 1 0 0 1 1 v v v v v P P 1 u u u u u i i i d d d d d Vd=vlalign(Vu,Vv,#u3) +0 0 0 1 1 1 1 1 0 0 1 v v v v v P P 0 u u u u u 0 0 1 d d d d d Vd=vdelta(Vu,Vv) +0 0 0 1 1 1 1 1 0 0 1 v v v v v P P 0 u u u u u 0 1 1 d d d d d Vd=vrdelta(Vu,Vv) +0 0 0 1 1 1 1 0 - - 0 - - - 0 0 P P 0 u u u u u 1 1 0 d d d d d Vd.h=vdeal(Vu.h) +0 0 0 1 1 1 1 0 - - 0 - - - 0 0 P P 0 u u u u u 1 1 1 d d d d d Vd.b=vdeal(Vu.b) +0 0 0 1 1 1 1 0 - - 0 - - - 0 1 P P 0 u u u u u 1 1 1 d d d d d Vd.h=vshuff(Vu.h) +0 0 0 1 1 1 1 0 - - 0 - - - 1 0 P P 0 u u u u u 0 0 0 d d d d d Vd.b=vshuff(Vu.b) +0 0 0 1 1 1 1 1 0 0 1 v v v v v P P 0 u u u u u 1 1 1 d d d d d Vd.b=vdeale(Vu.b,Vv.b) +0 0 0 1 1 1 1 1 1 1 0 v v v v v P P 0 u u u u u 0 1 0 d d d d d Vd.b=vpacke(Vu.h,Vv.h) +0 0 0 1 1 1 1 1 1 1 0 v v v v v P P 0 u u u u u 0 1 1 d d d d d Vd.h=vpacke(Vu.w,Vv.w) +0 0 0 1 1 1 1 1 1 1 0 v v v v v P P 0 u u u u u 1 0 1 d d d d d Vd.ub=vpack(Vu.h,Vv.h):sat +0 0 0 1 1 1 1 1 1 1 0 v v v v v P P 0 u u u u u 1 1 0 d d d d d Vd.b=vpack(Vu.h,Vv.h):sat +0 0 0 1 1 1 1 1 1 1 0 v v v v v P P 0 u u u u u 1 1 1 d d d d d Vd.uh=vpack(Vu.w,Vv.w):sat +0 0 0 1 1 1 1 1 1 1 1 v v v v v P P 0 u u u u u 0 0 0 d d d d d Vd.h=vpack(Vu.w,Vv.w):sat +0 0 0 1 1 1 1 1 1 1 1 v v v v v P P 0 u u u u u 0 0 1 d d d d d Vd.b=vpacko(Vu.h,Vv.h) +0 0 0 1 1 1 1 1 1 1 1 v v v v v P P 0 u u u u u 0 1 0 d d d d d Vd.h=vpacko(Vu.w,Vv.w) +0 0 0 1 1 0 0 1 1 0 1 t t t t t P P 0 - - - - - 0 1 0 - 0 1 d d Qd4=vsetq(Rt) +0 0 0 1 1 0 0 1 1 0 1 t t t t t P P 0 - - - - - 0 1 0 - 1 1 d d Qd4=vsetq2(Rt) +0 0 0 1 1 0 0 0 v v v v v t t t P P 0 u u u u u 0 1 1 d d d d d Vd.b=vlut32(Vu.b,Vv.b,Rt):nomatch +0 0 0 1 1 0 1 1 v v v v v t t t P P 1 u u u u u 0 0 1 d d d d d Vd.b=vlut32(Vu.b,Vv.b,Rt) +0 0 0 1 1 1 1 0 0 0 1 v v v v v P P 0 u u u u u i i i d d d d d Vd.b=vlut32(Vu.b,Vv.b,#u3) +0 0 0 1 1 0 1 0 1 0 1 v v v v v P P 1 u u u u u 1 1 1 x x x x x Vxx.w=vasrinto(Vu.w,Vv.w) +0 0 0 1 1 0 0 1 1 1 1 t t t t t P P 1 y y y y y 0 0 1 x x x x x vshuff(Vy,Vx,Rt) +0 0 0 1 1 0 0 1 1 1 1 t t t t t P P 1 y y y y y 0 1 0 x x x x x vdeal(Vy,Vx,Rt) +0 0 0 1 1 0 1 1 v v v v v t t t P P 1 u u u u u 0 1 1 d d d d d Vdd=vshuff(Vu,Vv,Rt) +0 0 0 1 1 0 1 1 v v v v v t t t P P 1 u u u u u 1 0 0 d d d d d Vdd=vdeal(Vu,Vv,Rt) +0 0 0 1 1 0 0 0 v v v v v t t t P P 0 u u u u u 1 0 0 d d d d d Vdd.h=vlut16(Vu.b,Vv.h,Rt):nomatch +0 0 0 1 1 0 1 1 v v v v v t t t P P 1 u u u u u 1 0 1 x x x x x Vx.b|=vlut32(Vu.b,Vv.b,Rt) +0 0 0 1 1 0 1 1 v v v v v t t t P P 1 u u u u u 1 1 0 d d d d d Vdd.h=vlut16(Vu.b,Vv.h,Rt) +0 0 0 1 1 0 1 1 v v v v v t t t P P 1 u u u u u 1 1 1 x x x x x Vxx.h|=vlut16(Vu.b,Vv.h,Rt) +0 0 0 1 1 1 0 0 1 1 0 v v v v v P P 1 u u u u u i i i x x x x x Vx.b|=vlut32(Vu.b,Vv.b,#u3) +0 0 0 1 1 1 0 0 1 1 1 v v v v v P P 1 u u u u u i i i x x x x x Vxx.h|=vlut16(Vu.b,Vv.h,#u3) +0 0 0 1 1 1 1 0 0 1 1 v v v v v P P 0 u u u u u i i i d d d d d Vdd.h=vlut16(Vu.b,Vv.h,#u3) +0 0 0 1 1 1 1 0 - - 0 - - - 0 1 P P 0 u u u u u 0 0 0 d d d d d Vdd.uh=vunpack(Vu.ub) +0 0 0 1 1 1 1 0 - - 0 - - - 0 1 P P 0 u u u u u 0 0 1 d d d d d Vdd.uw=vunpack(Vu.uh) +0 0 0 1 1 1 1 0 - - 0 - - - 0 1 P P 0 u u u u u 0 1 0 d d d d d Vdd.h=vunpack(Vu.b) +0 0 0 1 1 1 1 0 - - 0 - - - 0 1 P P 0 u u u u u 0 1 1 d d d d d Vdd.w=vunpack(Vu.h) +0 0 0 1 1 1 1 0 - - 0 - - 0 0 0 P P 1 u u u u u 0 0 0 x x x x x Vxx.h|=vunpacko(Vu.b) +0 0 0 1 1 1 1 0 - - 0 - - 0 0 0 P P 1 u u u u u 0 0 1 x x x x x Vxx.w|=vunpacko(Vu.h) +0 0 1 0 1 1 1 1 0 0 1 t t t t t P P u v v v v v 0 1 0 w w w w w vscatter(Rt,Mu,Vvv.w).h=Vw32 +0 0 1 0 1 1 1 1 0 0 1 t t t t t P P u v v v v v 1 1 0 w w w w w vscatter(Rt,Mu,Vvv.w).h+=Vw32 +0 0 1 0 1 1 1 1 1 0 1 t t t t t P P u v v v v v 0 s s w w w w w if (Qs4) vscatter(Rt,Mu,Vvv.w).h=Vw32 +0 0 1 0 1 1 1 1 0 0 1 t t t t t P P u v v v v v 0 0 0 w w w w w vscatter(Rt,Mu,Vv.w).w=Vw32 +0 0 1 0 1 1 1 1 0 0 1 t t t t t P P u v v v v v 0 0 1 w w w w w vscatter(Rt,Mu,Vv.h).h=Vw32 +0 0 1 0 1 1 1 1 0 0 1 t t t t t P P u v v v v v 1 0 0 w w w w w vscatter(Rt,Mu,Vv.w).w+=Vw32 +0 0 1 0 1 1 1 1 0 0 1 t t t t t P P u v v v v v 1 0 1 w w w w w vscatter(Rt,Mu,Vv.h).h+=Vw32 +0 0 1 0 1 1 1 1 1 0 0 t t t t t P P u v v v v v 0 s s w w w w w if (Qs4) vscatter(Rt,Mu,Vv.w).w=Vw32 +0 0 1 0 1 1 1 1 1 0 0 t t t t t P P u v v v v v 1 s s w w w w w if (Qs4) vscatter(Rt,Mu,Vv.h).h=Vw32 + +0 0 0 1 1 0 0 0 v v v v v t t t P P 0 u u u u u 0 0 0 d d d d d Vd.b=vasr(Vu.h,Vv.h,Rt):sat +0 0 0 1 1 0 0 0 v v v v v t t t P P 0 u u u u u 0 0 1 d d d d d Vd.uh=vasr(Vu.uw,Vv.uw,Rt):rnd:sat +0 0 0 1 1 0 0 0 v v v v v t t t P P 0 u u u u u 0 1 0 d d d d d Vd.uh=vasr(Vu.w,Vv.w,Rt):rnd:sat +0 0 0 1 1 0 0 0 v v v v v t t t P P 0 u u u u u 1 1 1 d d d d d Vd.ub=vasr(Vu.uh,Vv.uh,Rt):rnd:sat +0 0 0 1 1 0 0 0 v v v v v t t t P P 1 u u u u u 1 0 0 d d d d d Vd.uh=vasr(Vu.uw,Vv.uw,Rt):sat +0 0 0 1 1 0 0 0 v v v v v t t t P P 1 u u u u u 1 0 1 d d d d d Vd.ub=vasr(Vu.uh,Vv.uh,Rt):sat + +0 0 0 1 1 0 1 1 v v v v v t t t P P 0 u u u u u 0 1 0 d d d d d Vd.h=vasr(Vu.w,Vv.w,Rt) +0 0 0 1 1 0 1 1 v v v v v t t t P P 0 u u u u u 0 1 1 d d d d d Vd.h=vasr(Vu.w,Vv.w,Rt):sat +0 0 0 1 1 0 1 1 v v v v v t t t P P 0 u u u u u 1 0 0 d d d d d Vd.h=vasr(Vu.w,Vv.w,Rt):rnd:sat +0 0 0 1 1 0 1 1 v v v v v t t t P P 0 u u u u u 1 0 1 d d d d d Vd.uh=vasr(Vu.w,Vv.w,Rt):sat +0 0 0 1 1 0 1 1 v v v v v t t t P P 0 u u u u u 1 1 0 d d d d d Vd.ub=vasr(Vu.h,Vv.h,Rt):sat +0 0 0 1 1 0 1 1 v v v v v t t t P P 0 u u u u u 1 1 1 d d d d d Vd.ub=vasr(Vu.h,Vv.h,Rt):rnd:sat +0 0 0 1 1 0 1 1 v v v v v t t t P P 1 u u u u u 0 0 0 d d d d d Vd.b=vasr(Vu.h,Vv.h,Rt):rnd:sat +0 0 0 1 1 1 1 0 v v 0 - - 0 1 1 P P 1 - - 0 0 0 0 1 0 d d d d d Vd.b=prefixsum(Qv4) +0 0 0 1 1 1 1 0 v v 0 - - 0 1 1 P P 1 - - 0 0 1 0 1 0 d d d d d Vd.h=prefixsum(Qv4) +0 0 0 1 1 1 1 0 v v 0 - - 0 1 1 P P 1 - - 0 1 0 0 1 0 d d d d d Vd.w=prefixsum(Qv4) +0 0 0 1 1 1 1 1 0 1 1 v v v v v P P 1 u u u u u 0 1 0 d d d d d Vd.qf16=vadd(Vu.qf16,Vv.qf16) +0 0 0 1 1 1 1 1 0 1 1 v v v v v P P 1 u u u u u 0 1 1 d d d d d Vd.qf16=vadd(Vu.hf,Vv.hf) +0 0 0 1 1 1 1 1 0 1 1 v v v v v P P 1 u u u u u 1 0 0 d d d d d Vd.qf16=vadd(Vu.qf16,Vv.hf) +0 0 0 1 1 1 1 1 1 0 1 v v v v v P P 1 u u u u u 0 0 0 d d d d d Vd.qf32=vadd(Vu.qf32,Vv.qf32) +0 0 0 1 1 1 1 1 1 0 1 v v v v v P P 1 u u u u u 0 0 1 d d d d d Vd.qf32=vadd(Vu.sf,Vv.sf) +0 0 0 1 1 1 1 1 1 0 1 v v v v v P P 1 u u u u u 0 1 0 d d d d d Vd.qf32=vadd(Vu.qf32,Vv.sf) +0 0 0 1 1 0 0 1 0 1 1 t t t t t P P 1 u u u u u 0 1 0 x x x x x Vx.w+=vasl(Vu.w,Rt) +0 0 0 1 1 0 0 1 0 1 1 t t t t t P P 1 u u u u u 1 0 1 x x x x x Vx.w+=vasr(Vu.w,Rt) +0 0 0 1 1 0 0 1 1 0 0 t t t t t P P 1 u u u u u 1 1 1 x x x x x Vx.h+=vasr(Vu.h,Rt) +0 0 0 1 1 0 0 1 1 0 1 t t t t t P P 1 u u u u u 1 0 1 x x x x x Vx.h+=vasl(Vu.h,Rt) + +# 0 0 0 1 1 0 0 0 v v v v v t t t P P 0 u u u u u 0 0 0 d d d d d Vd.b=vasr(Vu.h,Vv.h,Rt):sat +# 0 0 0 1 1 0 0 0 v v v v v t t t P P 0 u u u u u 0 0 1 d d d d d Vd.uh=vasr(Vu.uw,Vv.uw,Rt):rnd:sat +# 0 0 0 1 1 0 0 0 v v v v v t t t P P 0 u u u u u 0 1 0 d d d d d Vd.uh=vasr(Vu.w,Vv.w,Rt):rnd:sat +# 0 0 0 1 1 0 0 0 v v v v v t t t P P 0 u u u u u 1 1 1 d d d d d Vd.ub=vasr(Vu.uh,Vv.uh,Rt):rnd:sat +# 0 0 0 1 1 0 0 0 v v v v v t t t P P 1 u u u u u 1 0 0 d d d d d Vd.uh=vasr(Vu.uw,Vv.uw,Rt):sat +# 0 0 0 1 1 0 0 0 v v v v v t t t P P 1 u u u u u 1 0 1 d d d d d Vd.ub=vasr(Vu.uh,Vv.uh,Rt):sat + +0 0 0 1 1 0 0 1 0 1 1 t t t t t P P 0 u u u u u 1 0 1 d d d d d Vd.w=vasr(Vu.w,Rt) +0 0 0 1 1 0 0 1 0 1 1 t t t t t P P 0 u u u u u 1 1 0 d d d d d Vd.h=vasr(Vu.h,Rt) +0 0 0 1 1 0 0 1 0 1 1 t t t t t P P 0 u u u u u 1 1 1 d d d d d Vd.w=vasl(Vu.w,Rt) +0 0 0 1 1 0 0 1 1 0 0 t t t t t P P 0 u u u u u 0 0 0 d d d d d Vd.h=vasl(Vu.h,Rt) +0 0 0 1 1 0 0 1 1 0 0 t t t t t P P 0 u u u u u 0 0 1 d d d d d Vd.uw=vlsr(Vu.uw,Rt) +0 0 0 1 1 0 0 1 1 0 0 t t t t t P P 0 u u u u u 0 1 0 d d d d d Vd.uh=vlsr(Vu.uh,Rt) +0 0 0 1 1 0 0 1 1 0 0 t t t t t P P 0 u u u u u 0 1 1 d d d d d Vd.ub=vlsr(Vu.ub,Rt) + +# 0 0 0 1 1 0 1 1 v v v v v t t t P P 0 u u u u u 0 1 0 d d d d d Vd.h=vasr(Vu.w,Vv.w,Rt) +# 0 0 0 1 1 0 1 1 v v v v v t t t P P 0 u u u u u 0 1 1 d d d d d Vd.h=vasr(Vu.w,Vv.w,Rt):sat +# 0 0 0 1 1 0 1 1 v v v v v t t t P P 0 u u u u u 1 0 0 d d d d d Vd.h=vasr(Vu.w,Vv.w,Rt):rnd:sat +# 0 0 0 1 1 0 1 1 v v v v v t t t P P 0 u u u u u 1 0 1 d d d d d Vd.uh=vasr(Vu.w,Vv.w,Rt):sat +# 0 0 0 1 1 0 1 1 v v v v v t t t P P 0 u u u u u 1 1 0 d d d d d Vd.ub=vasr(Vu.h,Vv.h,Rt):sat +# 0 0 0 1 1 0 1 1 v v v v v t t t P P 0 u u u u u 1 1 1 d d d d d Vd.ub=vasr(Vu.h,Vv.h,Rt):rnd:sat +# 0 0 0 1 1 0 1 1 v v v v v t t t P P 1 u u u u u 0 0 0 d d d d d Vd.b=vasr(Vu.h,Vv.h,Rt):rnd:sat + +0 0 0 1 1 1 1 1 1 0 1 v v v v v P P 0 u u u u u 0 0 0 d d d d d Vd.w=vasr(Vu.w,Vv.w) +0 0 0 1 1 1 1 1 1 0 1 v v v v v P P 0 u u u u u 0 0 1 d d d d d Vd.w=vlsr(Vu.w,Vv.w) +0 0 0 1 1 1 1 1 1 0 1 v v v v v P P 0 u u u u u 0 1 0 d d d d d Vd.h=vlsr(Vu.h,Vv.h) +0 0 0 1 1 1 1 1 1 0 1 v v v v v P P 0 u u u u u 0 1 1 d d d d d Vd.h=vasr(Vu.h,Vv.h) +0 0 0 1 1 1 1 1 1 0 1 v v v v v P P 0 u u u u u 1 0 0 d d d d d Vd.w=vasl(Vu.w,Vv.w) +0 0 0 1 1 1 1 1 1 0 1 v v v v v P P 0 u u u u u 1 0 1 d d d d d Vd.h=vasl(Vu.h,Vv.h) +0 0 0 1 1 1 0 1 0 0 0 v v v v v P P 0 u u u u u 0 0 0 d d d d d Vd.uh=vasr(Vuu.w,Vv.uh):sat +0 0 0 1 1 1 0 1 0 0 0 v v v v v P P 0 u u u u u 0 0 1 d d d d d Vd.uh=vasr(Vuu.w,Vv.uh):rnd:sat +0 0 0 1 1 1 0 1 0 0 0 v v v v v P P 0 u u u u u 0 1 0 d d d d d Vd.ub=vasr(Vuu.uh,Vv.ub):sat +0 0 0 1 1 1 0 1 0 0 0 v v v v v P P 0 u u u u u 0 1 1 d d d d d Vd.ub=vasr(Vuu.uh,Vv.ub):rnd:sat +0 0 0 1 1 1 1 0 - - 0 - - 1 0 0 P P 1 u u u u u 0 0 0 d d d d d Vd.sf=Vu.qf32 +0 0 0 1 1 1 1 0 - - 0 - - 1 0 0 P P 1 u u u u u 0 1 1 d d d d d Vd.hf=Vu.qf16 +0 0 0 1 1 1 1 0 - - 0 - - 1 0 0 P P 1 u u u u u 1 1 0 d d d d d Vd.hf=Vuu.qf32 +0 0 0 1 1 1 1 1 0 1 1 v v v v v P P 0 u u u u u 1 0 0 d d d d d Vd.h=vround(Vu.w,Vv.w):sat +0 0 0 1 1 1 1 1 0 1 1 v v v v v P P 0 u u u u u 1 0 1 d d d d d Vd.uh=vround(Vu.w,Vv.w):sat +0 0 0 1 1 1 1 1 0 1 1 v v v v v P P 0 u u u u u 1 1 0 d d d d d Vd.b=vround(Vu.h,Vv.h):sat +0 0 0 1 1 1 1 1 0 1 1 v v v v v P P 0 u u u u u 1 1 1 d d d d d Vd.ub=vround(Vu.h,Vv.h):sat +0 0 0 1 1 1 1 1 1 1 1 v v v v v P P 0 u u u u u 0 1 1 d d d d d Vd.ub=vround(Vu.uh,Vv.uh):sat +0 0 0 1 1 1 1 1 1 1 1 v v v v v P P 0 u u u u u 1 0 0 d d d d d Vd.uh=vround(Vu.uw,Vv.uw):sat +0 0 0 1 1 0 1 0 1 0 0 v v v v v P P 1 u u u u u 1 1 1 d d d d d Vd.uw=vrotr(Vu.uw,Vv.uw) +0 0 0 1 1 1 1 1 0 1 1 v v v v v P P 1 u u u u u 1 0 1 d d d d d Vd.qf16=vsub(Vu.qf16,Vv.qf16) +0 0 0 1 1 1 1 1 0 1 1 v v v v v P P 1 u u u u u 1 1 0 d d d d d Vd.qf16=vsub(Vu.hf,Vv.hf) +0 0 0 1 1 1 1 1 0 1 1 v v v v v P P 1 u u u u u 1 1 1 d d d d d Vd.qf16=vsub(Vu.qf16,Vv.hf) +0 0 0 1 1 1 1 1 1 0 1 v v v v v P P 1 u u u u u 0 1 1 d d d d d Vd.qf32=vsub(Vu.qf32,Vv.qf32) +0 0 0 1 1 1 1 1 1 0 1 v v v v v P P 1 u u u u u 1 0 0 d d d d d Vd.qf32=vsub(Vu.sf,Vv.sf) +0 0 0 1 1 1 1 1 1 0 1 v v v v v P P 1 u u u u u 1 0 1 d d d d d Vd.qf32=vsub(Vu.qf32,Vv.sf) +0 0 0 1 1 1 1 0 - - 0 - - - 1 0 P P 0 u u u u u 1 0 1 d d d d d Vd.uw=vcl0(Vu.uw) +0 0 0 1 1 1 1 0 - - 0 - - - 1 0 P P 0 u u u u u 1 1 0 d d d d d Vd.h=vpopcount(Vu.h) +0 0 0 1 1 1 1 0 - - 0 - - - 1 0 P P 0 u u u u u 1 1 1 d d d d d Vd.uh=vcl0(Vu.uh) +0 0 0 1 1 1 1 0 - - 0 - - - 1 1 P P 0 u u u u u 1 0 0 d d d d d Vd.w=vnormamt(Vu.w) +0 0 0 1 1 1 1 0 - - 0 - - - 1 1 P P 0 u u u u u 1 0 1 d d d d d Vd.h=vnormamt(Vu.h) +0 0 0 1 1 1 1 1 0 0 0 v v v v v P P 1 u u u u u 0 0 0 d d d d d Vd.h=vadd(vclb(Vu.h),Vv.h) +0 0 0 1 1 1 1 1 0 0 0 v v v v v P P 1 u u u u u 0 0 1 d d d d d Vd.w=vadd(vclb(Vu.w),Vv.w) +0 0 1 0 1 0 0 0 1 0 0 t t t t t P P i v v i i i 0 0 0 s s s s s if (Qv4) vmem(Rt+#s4)=Vs +0 0 1 0 1 0 0 0 1 0 0 t t t t t P P i v v i i i 0 0 1 s s s s s if (!Qv4) vmem(Rt+#s4)=Vs +0 0 1 0 1 0 0 0 1 1 0 t t t t t P P i v v i i i 0 0 0 s s s s s if (Qv4) vmem(Rt+#s4):nt=Vs +0 0 1 0 1 0 0 0 1 1 0 t t t t t P P i v v i i i 0 0 1 s s s s s if (!Qv4) vmem(Rt+#s4):nt=Vs +0 0 1 0 1 0 0 1 1 0 0 x x x x x P P - v v i i i 0 0 0 s s s s s if (Qv4) vmem(Rx++#s3)=Vs +0 0 1 0 1 0 0 1 1 0 0 x x x x x P P - v v i i i 0 0 1 s s s s s if (!Qv4) vmem(Rx++#s3)=Vs +0 0 1 0 1 0 0 1 1 1 0 x x x x x P P - v v i i i 0 0 0 s s s s s if (Qv4) vmem(Rx++#s3):nt=Vs +0 0 1 0 1 0 0 1 1 1 0 x x x x x P P - v v i i i 0 0 1 s s s s s if (!Qv4) vmem(Rx++#s3):nt=Vs +0 0 1 0 1 0 1 1 1 0 0 x x x x x P P u v v - - - 0 0 0 s s s s s if (Qv4) vmem(Rx++Mu)=Vs +0 0 1 0 1 0 1 1 1 0 0 x x x x x P P u v v - - - 0 0 1 s s s s s if (!Qv4) vmem(Rx++Mu)=Vs +0 0 1 0 1 0 1 1 1 1 0 x x x x x P P u v v - - - 0 0 0 s s s s s if (Qv4) vmem(Rx++Mu):nt=Vs +0 0 1 0 1 0 1 1 1 1 0 x x x x x P P u v v - - - 0 0 1 s s s s s if (!Qv4) vmem(Rx++Mu):nt=Vs +0 0 1 0 1 0 0 0 0 0 1 t t t t t P P i - - i i i 0 0 1 - 0 s s s vmem(Rt+#s4)=Os8.new +0 0 1 0 1 0 0 0 0 1 1 t t t t t P P i - - i i i 0 0 1 - - s s s vmem(Rt+#s4):nt=Os8.new +0 0 1 0 1 0 0 0 1 0 1 t t t t t P P i v v i i i 0 1 0 0 0 s s s if (Pv) vmem(Rt+#s4)=Os8.new +0 0 1 0 1 0 0 0 1 0 1 t t t t t P P i v v i i i 0 1 1 0 1 s s s if (!Pv) vmem(Rt+#s4)=Os8.new +0 0 1 0 1 0 0 0 1 1 1 t t t t t P P i v v i i i 0 1 0 1 0 s s s if (Pv) vmem(Rt+#s4):nt=Os8.new +0 0 1 0 1 0 0 0 1 1 1 t t t t t P P i v v i i i 0 1 1 1 1 s s s if (!Pv) vmem(Rt+#s4):nt=Os8.new +0 0 1 0 1 0 0 1 0 0 1 x x x x x P P - - - i i i 0 0 1 - 0 s s s vmem(Rx++#s3)=Os8.new +0 0 1 0 1 0 0 1 0 1 1 x x x x x P P - - - i i i 0 0 1 - - s s s vmem(Rx++#s3):nt=Os8.new +0 0 1 0 1 0 0 1 1 0 1 x x x x x P P - v v i i i 0 1 0 0 0 s s s if (Pv) vmem(Rx++#s3)=Os8.new +0 0 1 0 1 0 0 1 1 0 1 x x x x x P P - v v i i i 0 1 1 0 1 s s s if (!Pv) vmem(Rx++#s3)=Os8.new +0 0 1 0 1 0 0 1 1 1 1 x x x x x P P - v v i i i 0 1 0 1 0 s s s if (Pv) vmem(Rx++#s3):nt=Os8.new +0 0 1 0 1 0 0 1 1 1 1 x x x x x P P - v v i i i 0 1 1 1 1 s s s if (!Pv) vmem(Rx++#s3):nt=Os8.new +0 0 1 0 1 0 1 1 0 0 1 x x x x x P P u - - - - - 0 0 1 - 0 s s s vmem(Rx++Mu)=Os8.new +0 0 1 0 1 0 1 1 0 1 1 x x x x x P P u - - - - - 0 0 1 - - s s s vmem(Rx++Mu):nt=Os8.new +0 0 1 0 1 0 1 1 1 0 1 x x x x x P P u v v - - - 0 1 0 0 0 s s s if (Pv) vmem(Rx++Mu)=Os8.new +0 0 1 0 1 0 1 1 1 0 1 x x x x x P P u v v - - - 0 1 1 0 1 s s s if (!Pv) vmem(Rx++Mu)=Os8.new +0 0 1 0 1 0 1 1 1 1 1 x x x x x P P u v v - - - 0 1 0 1 0 s s s if (Pv) vmem(Rx++Mu):nt=Os8.new +0 0 1 0 1 0 1 1 1 1 1 x x x x x P P u v v - - - 0 1 1 1 1 s s s if (!Pv) vmem(Rx++Mu):nt=Os8.ne +0 0 1 0 1 0 0 0 0 0 1 t t t t t P P i - - i i i 0 0 0 s s s s s vmem(Rt+#s4)=Vs +0 0 1 0 1 0 0 0 0 1 1 t t t t t P P i - - i i i 0 0 0 s s s s s vmem(Rt+#s4):nt=Vs +0 0 1 0 1 0 0 0 1 0 1 t t t t t P P i v v i i i 0 0 0 s s s s s if (Pv) vmem(Rt+#s4)=Vs +0 0 1 0 1 0 0 0 1 0 1 t t t t t P P i v v i i i 0 0 1 s s s s s if (!Pv) vmem(Rt+#s4)=Vs +0 0 1 0 1 0 0 0 1 1 1 t t t t t P P i v v i i i 0 0 0 s s s s s if (Pv) vmem(Rt+#s4):nt=Vs +0 0 1 0 1 0 0 0 1 1 1 t t t t t P P i v v i i i 0 0 1 s s s s s if (!Pv) vmem(Rt+#s4):nt=Vs +0 0 1 0 1 0 0 1 0 0 1 x x x x x P P - - - i i i 0 0 0 s s s s s vmem(Rx++#s3)=Vs +0 0 1 0 1 0 0 1 0 1 1 x x x x x P P - - - i i i 0 0 0 s s s s s vmem(Rx++#s3):nt=Vs +0 0 1 0 1 0 0 1 1 0 1 x x x x x P P - v v i i i 0 0 0 s s s s s if (Pv) vmem(Rx++#s3)=Vs +0 0 1 0 1 0 0 1 1 0 1 x x x x x P P - v v i i i 0 0 1 s s s s s if (!Pv) vmem(Rx++#s3)=Vs +0 0 1 0 1 0 0 1 1 1 1 x x x x x P P - v v i i i 0 0 0 s s s s s if (Pv) vmem(Rx++#s3):nt=Vs +0 0 1 0 1 0 0 1 1 1 1 x x x x x P P - v v i i i 0 0 1 s s s s s if (!Pv) vmem(Rx++#s3):nt=Vs +0 0 1 0 1 0 1 1 0 0 1 x x x x x P P u - - - - - 0 0 0 s s s s s vmem(Rx++Mu)=Vs +0 0 1 0 1 0 1 1 0 1 1 x x x x x P P u - - - - - 0 0 0 s s s s s vmem(Rx++Mu):nt=Vs +0 0 1 0 1 0 1 1 1 0 1 x x x x x P P u v v - - - 0 0 0 s s s s s if (Pv) vmem(Rx++Mu)=Vs +0 0 1 0 1 0 1 1 1 0 1 x x x x x P P u v v - - - 0 0 1 s s s s s if (!Pv) vmem(Rx++Mu)=Vs +0 0 1 0 1 0 1 1 1 1 1 x x x x x P P u v v - - - 0 0 0 s s s s s if (Pv) vmem(Rx++Mu):nt=Vs +0 0 1 0 1 0 1 1 1 1 1 x x x x x P P u v v - - - 0 0 1 s s s s s if (!Pv) vmem(Rx++Mu):nt=Vs +0 0 1 0 1 0 0 0 0 0 1 t t t t t P P i - - i i i 1 1 1 s s s s s vmemu(Rt+#s4)=Vs +0 0 1 0 1 0 0 0 1 0 1 t t t t t P P i v v i i i 1 1 0 s s s s s if (Pv) vmemu(Rt+#s4)=Vs +0 0 1 0 1 0 0 0 1 0 1 t t t t t P P i v v i i i 1 1 1 s s s s s if (!Pv) vmemu(Rt+#s4)=Vs +0 0 1 0 1 0 0 1 0 0 1 x x x x x P P - - - i i i 1 1 1 s s s s s vmemu(Rx++#s3)=Vs +0 0 1 0 1 0 0 1 1 0 1 x x x x x P P - v v i i i 1 1 0 s s s s s if (Pv) vmemu(Rx++#s3)=Vs +0 0 1 0 1 0 0 1 1 0 1 x x x x x P P - v v i i i 1 1 1 s s s s s if (!Pv) vmemu(Rx++#s3)=Vs +0 0 1 0 1 0 1 1 0 0 1 x x x x x P P u - - - - - 1 1 1 s s s s s vmemu(Rx++Mu)=Vs +0 0 1 0 1 0 1 1 1 0 1 x x x x x P P u v v - - - 1 1 0 s s s s s if (Pv) vmemu(Rx++Mu)=Vs +0 0 1 0 1 0 1 1 1 0 1 x x x x x P P u v v - - - 1 1 1 s s s s s if (!Pv) vmemu(Rx++Mu)=Vs +0 0 1 0 1 0 0 0 0 0 1 t t t t t P P i - - i i i 0 0 1 - 1 - - - vmem(Rt+#s4):scatter_release +0 0 1 0 1 0 0 1 0 0 1 x x x x x P P - - - i i i 0 0 1 - 1 - - - vmem(Rx++#s3):scatter_release +0 0 1 0 1 0 1 1 0 0 1 x x x x x P P u - - - - - 0 0 1 - 1 - - - vmem(Rx++Mu):scatter_release + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Ghidra/Processors/Hexagon/data/languages/hexagon_left.sinc b/Ghidra/Processors/Hexagon/data/languages/hexagon_left.sinc new file mode 100644 index 0000000000..e7dcf8d175 --- /dev/null +++ b/Ghidra/Processors/Hexagon/data/languages/hexagon_left.sinc @@ -0,0 +1,648 @@ +# +# First/Left Packed 'EE' Instructions +# NOTE: It may be that Left-side patterns can ignore bits 0-12 +# + +# (v4,left,5,7) add -- "Rd16 = add ( Rs16 , #-1 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 - 1 0 0 1 1 s s s s d d d d - - - - - - - - - - - - - - - - + +:add Rd4l,rs4l,MinusOne EndPackedLeft is iclass3031=1 & iclass28=1 & op2427=3 & Rd4l & MinusOne & rs4l & $(END_PACKED_LEFT) { + Rd4l = rs4l - 1; + build EndPackedLeft; +} + +# (v4,left,3) add -- "Rd16 = add ( Ru16 , #-1 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 0 0 1 1 u u u u d d d d - - 1 - - - - - - - - - - - - - + +:add Rd4l,rs4l,MinusOne EndPackedLeft is iclass=3 & op2427=3 & op13=1 & Rd4l & MinusOne & rs4l & $(END_PACKED_LEFT) { + Rd4l = rs4l - 1; + build EndPackedLeft; +} + +# (v4,left,5,7) add -- "Rd16 = add ( Rs16 , #1 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 - 1 0 0 0 1 s s s s d d d d - - - - - - - - - - - - - - - - + +:add Rd4l,rs4l,One EndPackedLeft is iclass3031=1 & iclass28=1 & op2427=1 & Rd4l & One & rs4l & $(END_PACKED_LEFT) { + Rd4l = rs4l + 1; + build EndPackedLeft; +} + +# (v4,left,3) add -- "Rd16 = add ( Ru16 , #1 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 0 0 0 1 u u u u d d d d - - 1 - - - - - - - - - - - - - + +:add Rd4l,rs4l,One EndPackedLeft is iclass=3 & op2427=1 & op13=1 & Rd4l & One & rs4l & $(END_PACKED_LEFT) { + Rd4l = rs4l + 1; + build EndPackedLeft; +} + +# (v4,left,2) add -- "Rd16 = add ( Sp , #U6:2 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 1 I I I I I I d d d d - - 1 - - - - - - - - - - - - - + +:add Rd4l,SP,Uimm8_2025_shift2 EndPackedLeft is iclass=2 & op2627=3 & op13=1 & Rd4l & SP & Uimm8_2025_shift2 & $(END_PACKED_LEFT) { + Rd4l = SP + zext(Uimm8_2025_shift2); + build EndPackedLeft; +} + +# (v4,left,4,6) add -- "Rd16 = add ( Sp , #u6:2 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 - 0 1 1 i i i i i i d d d d - - - - - - - - - - - - - - - - + +:add Rd4l,SP,Uimm8_2025_shift2 EndPackedLeft is iclass3031=1 & iclass28=0 & op2627=3 & Rd4l & SP & Uimm8_2025_shift2 & $(END_PACKED_LEFT) { + Rd4l = SP + zext(Uimm8_2025_shift2); + build EndPackedLeft; +} + +# (v4,left,3) add -- "Rx16 = add ( Rs16 , Rx16 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 1 0 0 0 s s s s x x x x - - 1 - - - - - - - - - - - - - + +:add Rd4l,rs4l,rd4l EndPackedLeft is iclass=3 & op2427=8 & op13=1 & Rd4l & rd4l & rs4l & $(END_PACKED_LEFT) { + Rd4l = rs4l + rd4l; + build EndPackedLeft; +} + +# (v4,left,5,7) add -- "Rx16 = add ( Rs16 , Rx16 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 - 1 1 0 0 0 s s s s x x x x - - - - - - - - - - - - - - - - + +:add Rd4l,rs4l,rd4l EndPackedLeft is iclass3031=1 & iclass28=1 & op2427=8 & Rd4l & rd4l & rs4l & $(END_PACKED_LEFT) { + Rd4l = rs4l + rd4l; + build EndPackedLeft; +} + +# (v4,left,2) add -- "Rx16 = add ( Rx16 , #S7x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 0 I I I I I I I x x x x - - 1 - - - - - - - - - - - - - + +:add Rd4l,rd4l,Simm32_2026x EndPackedLeft is iclass=2 & op27=0 & op13=1 & Rd4l & rd4l & Simm32_2026x & $(END_PACKED_LEFT) { + Rd4l = rd4l + Simm32_2026x; + build EndPackedLeft; +} + +# (v4,left,4,6) add -- "Rx16 = add ( Rx16 , #S7x )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 - 0 0 I I I I I I I x x x x - - - - - - - - - - - - - - - - + +:add Rd4l,rd4l,Simm32_2026x EndPackedLeft is iclass3031=1 & iclass28=0 & op27=0 & Rd4l & rd4l & Simm32_2026x & $(END_PACKED_LEFT) { + Rd4l = rd4l + Simm32_2026x; + build EndPackedLeft; +} + +# (v4,left,5,7) and -- "Rd16 = and ( Rs16 , #1 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 - 1 0 0 1 0 s s s s d d d d - - - - - - - - - - - - - - - - + +:and Rd4l,rs4l,One EndPackedLeft is iclass3031=1 & iclass28=1 & op2427=2 & Rd4l & One & rs4l & $(END_PACKED_LEFT) { + Rd4l = rs4l & 1; + build EndPackedLeft; +} + +# (v4,left,5,7) and -- "Rd16 = and ( Rs16 , #255 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 - 1 0 1 1 1 s s s s d d d d - - - - - - - - - - - - - - - - + +:and Rd4l,rs4l,FF EndPackedLeft is iclass3031=1 & iclass28=1 & op2427=7 & Rd4l & FF & rs4l & $(END_PACKED_LEFT) { + Rd4l = rs4l & 0xff; + build EndPackedLeft; +} + +# (v4,left,3) and -- "Rd16 = and ( Ru16 , #1 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 0 0 1 0 u u u u d d d d - - 1 - - - - - - - - - - - - - + +:and Rd4l,rs4l,One EndPackedLeft is iclass=3 & op2427=2 & op13=1 & Rd4l & One & rs4l & $(END_PACKED_LEFT) { + Rd4l = rs4l & 1; + build EndPackedLeft; +} + +# (v4,left,3) and -- "Rd16 = and ( Ru16 , #255 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 0 1 1 1 u u u u d d d d - - 1 - - - - - - - - - - - - - + +:and Rd4l,rs4l,FF EndPackedLeft is iclass=3 & op2427=7 & op13=1 & Rd4l & FF & rs4l & $(END_PACKED_LEFT) { + Rd4l = rs4l & 0xff; + build EndPackedLeft; +} + +# (v4,left,5,7) assign -- "Rd16 = #-1" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 - 1 1 0 1 + + 0 + + d d d d - - - - - - - - - - - - - - - - + +:assign Rd4l,MinusOne EndPackedLeft is iclass3031=1 & iclass28=1 & op2127=0x50 & op20=0 & Rd4l & MinusOne & $(END_PACKED_LEFT) { + Rd4l = -1; + build EndPackedLeft; +} + +# (v4,left,2) assign -- "Rd16 = #U6x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 0 I I I I I I d d d d - - 1 - - - - - - - - - - - - - + +:assign Rd4l,Uimm32_2025x EndPackedLeft is iclass=2 & op2627=2 & op13=1 & Rd4l & Uimm32_2025x & $(END_PACKED_LEFT) { + Rd4l = Uimm32_2025x; + build EndPackedLeft; +} + +# (v4,left,4,6) assign -- "Rd16 = #U6x" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 - 0 1 0 I I I I I I d d d d - - - - - - - - - - - - - - - - + +:assign Rd4l,Uimm32_2025x EndPackedLeft is iclass3031=1 & iclass28=0 & op2627=2 & Rd4l & Uimm32_2025x & $(END_PACKED_LEFT) { + Rd4l = Uimm32_2025x; + build EndPackedLeft; +} + +# (v4,left,5,7) assign -- "Rd16 = Rs16" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 - 1 0 0 0 0 s s s s d d d d - - - - - - - - - - - - - - - - + +:assign Rd4l,rs4l EndPackedLeft is iclass3031=1 & iclass28=1 & op2427=0 & Rd4l & rs4l & $(END_PACKED_LEFT) { + Rd4l = rs4l; + build EndPackedLeft; +} + +# (v4,left,3) assign -- "Rd16 = Ru16" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 0 0 0 0 u u u u d d d d - - 1 1 - - - - - - - - - - - - + +:assign Rd4l,rs4l EndPackedLeft is iclass=3 & op2427=0 & op13=1 & Rd4l & rs4l & $(END_PACKED_LEFT) { + Rd4l = rs4l; + build EndPackedLeft; +} + +# (v4,left,3) assign -- "Re16 = #-1" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 1 0 1 + + 0 + + e e e e - - 1 - - - - - - - - - - - - - + +:assign Rd4l,MinusOne EndPackedLeft is iclass=3 & op2127=0x50 & op20=0 & op13=1 & Rd4l & MinusOne & $(END_PACKED_LEFT) { + Rd4l = -1; + build EndPackedLeft; +} + +# (v4,left,5,7) assign -- "if ( ! p0 ) Rd16 = #0" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 - 1 1 0 1 + + 1 1 1 d d d d - - - - - - - - - - - - - - - - +# +# (v4,left,5,7) assign -- "if ( ! p0 .new ) Rd16 = #0" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 - 1 1 0 1 + + 1 0 1 d d d d - - - - - - - - - - - - - - - - +# +# (v4,left,5,7) assign -- "if ( p0 ) Rd16 = #0" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 - 1 1 0 1 + + 1 1 0 d d d d - - - - - - - - - - - - - - - - +# +# (v4,left,5,7) assign -- "if ( p0 .new ) Rd16 = #0" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 - 1 1 0 1 + + 1 0 0 d d d d - - - - - - - - - - - - - - - - + +:assign^P0Cond_N21_S20 rd4l,Zero EndPackedLeft is iclass3031=1 & iclass28=1 & op2227=0x29 & rd4l & P0Cond_N21_S20 & Zero & $(END_PACKED_LEFT) { + build P0Cond_N21_S20; + build EndPackedLeft; + <> + if (ConditionReg == 0) goto ; + rd4l = 0; + +} + +# (v4,left,3) assign -- "if ( ! p0 ) Re16 = #0" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 1 0 1 + + 1 1 1 e e e e - - 1 - - - - - - - - - - - - - +# +# (v4,left,3) assign -- "if ( ! p0 .new ) Re16 = #0" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 1 0 1 + + 1 0 1 e e e e - - 1 - - - - - - - - - - - - - +# +# (v4,left,3) assign -- "if ( p0 ) Re16 = #0" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 1 0 1 + + 1 1 0 e e e e - - 1 - - - - - - - - - - - - - +# +# (v4,left,3) assign -- "if ( p0 .new ) Re16 = #0" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 1 0 1 + + 1 0 0 e e e e - - 1 - - - - - - - - - - - - - + +:assign^P0Cond_N21_S20 rd4l,Zero EndPackedLeft is iclass=3 & op2227=0x29 & op13=1 & rd4l & P0Cond_N21_S20 & Zero & $(END_PACKED_LEFT) { + build P0Cond_N21_S20; + build EndPackedLeft; + <> + if (ConditionReg == 0) goto ; + rd4l = 0; + +} + +# (v4,left,3) cmp.eq -- "p0 = cmp.eq ( Rs16 , #U2 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 1 0 0 1 s s s s - - I I - - 1 - - - - - - - - - - - - - + +:cmp.eq P0dest,rs4l,Uimm2_1617 EndPackedLeft is iclass=3 & op2427=9 & op13=1 & P0dest & rs4l & Uimm2_1617 & $(END_PACKED_LEFT) { + bool:1 = (rs4l == zext(Uimm2_1617)); + P0dest = P0dest & (bool * 0xff); + build EndPackedLeft; +} + +# (v4,left,5,7) cmp.eq -- "p0 = cmp.eq ( Rs16 , #U2 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 - 1 1 0 0 1 s s s s - - I I - - - - - - - - - - - - - - - - + +:cmp.eq P0dest,rs4l,Uimm2_1617 EndPackedLeft is iclass3031=1 & iclass28=1 & op2427=9 & P0dest & rs4l & Uimm2_1617 & $(END_PACKED_LEFT) { + bool:1 = (rs4l == zext(Uimm2_1617)); + P0dest = P0dest & (bool * 0xff); + build EndPackedLeft; +} + +# (v4,left,5,7) combine -- "Rdd8 = combine ( #n2 , #u2 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 - 1 1 1 + 0 + i i n n d d d - - - - - - - - - - - - - - - - + +:combine Rdd3l,Uimm2_1920,Uimm2_2122 EndPackedLeft is iclass3031=1 & iclass28=1 & op2327=0x18 & Uimm2_1920 & Uimm2_2122 & Rdd3l & $(END_PACKED_LEFT) { + Rdd3l = (zext(Uimm2_1920) << 32) + zext(Uimm2_2122); + build EndPackedLeft; +} + +# Simplification: "Rdd8 = #u2" +:assign Rdd3l,Uimm2_2122 EndPackedLeft is iclass3031=1 & iclass28=1 & op2327=0x18 & op1920=0 & Uimm2_2122 & Rdd3l & $(END_PACKED_LEFT) { + Rdd3l = zext(Uimm2_2122); + build EndPackedLeft; +} + +# (v4,left,3) combine -- "Rdd8 = combine ( #n2 , #u2 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 1 1 + 0 + i i n n d d d - - 1 - - - - - - - - - - - - - + +:combine Rdd3l,Uimm2_1920,Uimm2_2122 EndPackedLeft is iclass=3 & op2327=0x18 & op13=1 & Uimm2_1920 & Uimm2_2122 & Rdd3l & $(END_PACKED_LEFT) { + Rdd3l = (zext(Uimm2_1920) << 32) + zext(Uimm2_2122); + build EndPackedLeft; +} + +# Simplification: "Rdd8 = #u2" +:assign Rdd3l,Uimm2_2122 EndPackedLeft is iclass=3 & op2327=0x18 & op1920=0 & op13=1 & Uimm2_2122 & Rdd3l & $(END_PACKED_LEFT) { + Rdd3l = zext(Uimm2_2122); + build EndPackedLeft; +} + +# (v4,left,5,7) combine -- "Rdd8 = combine ( #0 , Rs16 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 - 1 1 1 + 1 s s s s 0 d d d - - - - - - - - - - - - - - - - + +:combine Rdd3l,Zero,rs4l EndPackedLeft is iclass3031=1 & iclass28=1 & op2427=13 & op19=0 & rs4l & Zero & Rdd3l & $(END_PACKED_LEFT) { + Rdd3l = zext(rs4l); + build EndPackedLeft; +} + +# (v4,left,3) combine -- "Ree8 = combine ( #0 , Ru16 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 1 1 + 1 u u u u 0 e e e - - 1 - - - - - - - - - - - - - + +:combine Rdd3l,Zero,rs4l EndPackedLeft is iclass=3 & op2427=13 & op19=0 & op13=1 & rs4l & Zero & Rdd3l & $(END_PACKED_LEFT) { + Rdd3l = zext(rs4l); + build EndPackedLeft; +} + +# (v4,left,5,7) combine -- "Rdd8 = combine ( Rs16 , #0 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 - 1 1 1 + 1 s s s s 1 d d d - - - - - - - - - - - - - - - - + +:combine Rdd3l,rs4l,Zero EndPackedLeft is iclass3031=1 & iclass28=1 & op2427=13 & op19=1 & rs4l & Zero & Rdd3l & $(END_PACKED_LEFT) { + Rdd3l = zext(rs4l) << 32; + build EndPackedLeft; +} + +# (v4,left,3) combine -- "Ree8 = combine ( Ru16 , #0 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 1 1 + 1 u u u u 1 e e e - - 1 - - - - - - - - - - - - - + +:combine Rdd3l,rs4l,Zero EndPackedLeft is iclass=3 & op2427=13 & op19=1 & op13=1 & rs4l & Zero & Rdd3l & $(END_PACKED_LEFT) { + Rdd3l = zext(rs4l) << 32; + build EndPackedLeft; +} + +# (v4,left,3) deallocframe -- "deallocframe" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 1 1 1 1 0 0 - - - 0 - - - - 0 - - - - - - - - - - - - - + +:deallocframe EndPackedLeft is iclass=3 & op2227=0x3c & op18=0 & op13=0 & $(END_PACKED_LEFT) { + build EndPackedLeft; + <> + deallocframe(FP); +} + +# (v4,left,9,13) deallocframe -- "deallocframe" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 - 0 1 1 1 1 1 0 0 - - - 0 - - - - 1 - - - - - - - - - - - - - + +:deallocframe EndPackedLeft is iclass31=1 & iclass2829=1 & op2227=0x3c & op18=0 & op13=1 & $(END_PACKED_LEFT) { + build EndPackedLeft; + <> + deallocframe(FP); +} + +# (v4,left,9,13) memb -- "Rd16 = memb ( Ru16 + #U3:0 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 - 0 1 0 I I I u u u u d d d d - - 1 - - - - - - - - - - - - - + +:memb Rd4l,MemRsRelU3Lb EndPackedLeft is iclass31=1 & iclass2829=1 & op27=0 & op13=1 & MemRsRelU3Lb & Rd4l & $(END_PACKED_LEFT) { + Rd4l = sext(MemRsRelU3Lb); + build EndPackedLeft; +} + +# (v4,left,3) memb -- "Rd16 = memb ( Rs16 + #u3:0 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 0 i i i s s s s d d d d - - 0 - - - - - - - - - - - - - + +:memb Rd4l,MemRsRelU3Lb EndPackedLeft is iclass=3 & op27=0 & op13=0 & MemRsRelU3Lb & Rd4l & $(END_PACKED_LEFT) { + Rd4l = sext(MemRsRelU3Lb); + build EndPackedLeft; +} + +# (v4,left,15) memb -- "memb ( Rs16 + #U4:0 ) = #n1" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 1 0 0 1 n s s s s I I I I - - 0 - - - - - - - - - - - - - + +:memb StMemRsRelC15Lb,Uimm1_24 EndPackedLeft is iclass=15 & op2527=1 & op13=0 & StMemRsRelC15Lb & Uimm1_24 & $(END_PACKED_LEFT) { + StMemRsRelC15Lb = Uimm1_24; + build EndPackedLeft; +} + +# (v4,left,11) memb -- "memb ( Rs16 + #U4:0 ) = Rt16" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 1 I I I I s s s s t t t t - - - - - - - - - - - - - - - - + +:memb MemRsRelU4Lb,rt4l EndPackedLeft is iclass=11 & MemRsRelU4Lb & rt4l & $(END_PACKED_LEFT) { + MemRsRelU4Lb = rt4l:1; + build EndPackedLeft; +} + +# (v4,left,9,13) memd -- "Rdd8 = memd ( Sp + #U5:3 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 - 0 1 1 1 1 0 I I I I I d d d - - 1 - - - - - - - - - - - - - + +:memd Rdd3l,MemSpRelU5Ld EndPackedLeft is iclass31=1 & iclass2829=1 & op2427=14 & op13=1 & MemSpRelU5Ld & Rdd3l & $(END_PACKED_LEFT) { + Rdd3l = MemSpRelU5Ld; + build EndPackedLeft; +} + +# (v4,left,3) memd -- "Rdd8 = memd ( Sp + #u5:3 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 1 1 1 0 i i i i i d d d - - 0 - - - - - - - - - - - - - + +:memd Rdd3l,MemSpRelU5Ld EndPackedLeft is iclass=3 & op2427=14 & op13=0 & MemSpRelU5Ld & Rdd3l & $(END_PACKED_LEFT) { + Rdd3l = MemSpRelU5Ld; + build EndPackedLeft; +} + +# (v4,left,14) memd -- "memd ( Sp + #S6:3 ) = Rtt8" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 1 I I I I I I t t t - - 0 - - - - - - - - - - - - - + +:memd MemSpRelS6Ld,rtt3l EndPackedLeft is iclass=14 & op2527=5 & op13=0 & MemSpRelS6Ld & rtt3l & $(END_PACKED_LEFT) { + MemSpRelS6Ld = rtt3l; + build EndPackedLeft; +} + +# (v4,left,8,12) memh -- "Rd16 = memh ( Rs16 + #U3:1 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 - 0 0 0 I I I s s s s d d d d - - 1 - - - - - - - - - - - - - + +:memh Rd4l,MemRsRelU3Lh EndPackedLeft is iclass31=1 & iclass2829=0 & op27=0 & op13=1 & MemRsRelU3Lh & Rd4l & $(END_PACKED_LEFT) { + Rd4l = sext(MemRsRelU3Lh); + build EndPackedLeft; +} + +# (v4,left,2) memh -- "Rd16 = memh ( Rs16 + #u3:1 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 0 i i i s s s s d d d d - - 0 - - - - - - - - - - - - - + +:memh Rd4l,MemRsRelU3Lh EndPackedLeft is iclass=2 & op27=0 & op13=0 & MemRsRelU3Lh & Rd4l & $(END_PACKED_LEFT) { + Rd4l = sext(MemRsRelU3Lh); + build EndPackedLeft; +} + +# (v4,left,14) memh -- "memh ( Rs16 + #U3:1 ) = Rt16" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 0 I I I s s s s t t t t - - 0 - - - - - - - - - - - - - + +:memh MemRsRelU3Lh,rt4l EndPackedLeft is iclass=14 & op27=0 & op13=0 & MemRsRelU3Lh & rt4l & $(END_PACKED_LEFT) { + MemRsRelU3Lh = rt4l:2; + build EndPackedLeft; +} + +# (v4,left,1) memub -- "Rd16 = memub ( Rs16 + #u4:0 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 1 i i i i s s s s d d d d - - - - - - - - - - - - - - - - + +:memub Rd4l,MemRsRelU4Lb EndPackedLeft is iclass=1 & MemRsRelU4Lb & Rd4l & $(END_PACKED_LEFT) { + Rd4l = zext(MemRsRelU4Lb); + build EndPackedLeft; +} + +# (v4,left,9,13) memub -- "Rd16 = memub ( Ru16 + #U4:0 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 - 0 1 I I I I u u u u d d d d - - 0 - - - - - - - - - - - - - + +:memub Rd4l,MemRsRelU4Lb EndPackedLeft is iclass31=1 & iclass2829=1 & op13=0 & MemRsRelU4Lb & Rd4l & $(END_PACKED_LEFT) { + Rd4l = zext(MemRsRelU4Lb); + build EndPackedLeft; +} + +# (v4,left,2) memuh -- "Rd16 = memuh ( Rs16 + #u3:1 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 1 i i i s s s s d d d d - - 0 - - - - - - - - - - - - - + +:memuh Rd4l,MemRsRelU3Lh EndPackedLeft is iclass=2 & op27=1 & op13=0 & MemRsRelU3Lh & Rd4l & $(END_PACKED_LEFT) { + Rd4l = zext(MemRsRelU3Lh); + build EndPackedLeft; +} + +# (v4,left,8,12) memuh -- "Rd16 = memuh ( Ru16 + #U3:1 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 - 0 0 1 I I I u u u u d d d d - - 1 - - - - - - - - - - - - - + +:memuh Rd4l,MemRsRelU3Lh EndPackedLeft is iclass31=1 & iclass2829=0 & op27=1 & op13=1 & MemRsRelU3Lh & Rd4l & $(END_PACKED_LEFT) { + Rd4l = zext(MemRsRelU3Lh); + build EndPackedLeft; +} + +# (v4,left,0) memw -- "Rd16 = memw ( Rs16 + #u4:2 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 0 0 i i i i s s s s d d d d - - - - - - - - - - - - - - - - + +:memw Rd4l,MemRsRelU4Lw EndPackedLeft is iclass=0 & MemRsRelU4Lw & Rd4l & $(END_PACKED_LEFT) { + Rd4l = MemRsRelU4Lw; + build EndPackedLeft; +} + +# (v4,left,8,12) memw -- "Rd16 = memw ( Ru16 + #U4:2 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 - 0 0 I I I I u u u u d d d d - - 0 - - - - - - - - - - - - - + +:memw Rd4l,MemRsRelU4Lw EndPackedLeft is iclass31=1 & iclass2829=0 & op13=0 & MemRsRelU4Lw & Rd4l & $(END_PACKED_LEFT) { + Rd4l = MemRsRelU4Lw; + build EndPackedLeft; +} + +# (v4,left,9,13) memw -- "Rd16 = memw ( Sp + #U5:2 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 - 0 1 1 1 0 I I I I I d d d d - - 1 - - - - - - - - - - - - - + +:memw Rd4l,MemSpRelU5Lw EndPackedLeft is iclass31=1 & iclass2829=1 & op2527=6 & op13=1 & MemSpRelU5Lw & Rd4l & $(END_PACKED_LEFT) { + Rd4l = MemSpRelU5Lw; + build EndPackedLeft; +} + +# (v4,left,3) memw -- "Rd16 = memw ( Sp + #u5:2 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 1 1 0 i i i i i d d d d - - 0 - - - - - - - - - - - - - + +:memw Rd4l,MemSpRelU5Lw EndPackedLeft is iclass=3 & op2527=6 & op13=0 & MemSpRelU5Lw & Rd4l & $(END_PACKED_LEFT) { + Rd4l = MemSpRelU5Lw; + build EndPackedLeft; +} + +# (v4,left,15) memw -- "memw ( Rs16 + #U4:2 ) = #n1" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 1 0 0 0 n s s s s I I I I - - 0 - - - - - - - - - - - - - + +:memw StMemRsRelC15Lw,Uimm1_24 EndPackedLeft is iclass=15 & op2527=0 & op13=0 & StMemRsRelC15Lw & Uimm1_24 & $(END_PACKED_LEFT) { + StMemRsRelC15Lw = zext(Uimm1_24); + build EndPackedLeft; +} + +# (v4,left,10) memw -- "memw ( Rs16 + #U4:2 ) = Rt16" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 0 I I I I s s s s t t t t - - - - - - - - - - - - - - - - + +:memw MemRsRelU4Lw,rt4l EndPackedLeft is iclass=10 & MemRsRelU4Lw & rt4l & $(END_PACKED_LEFT) { + MemRsRelU4Lw = rt4l; + build EndPackedLeft; +} + +# (v4,left,14) memw -- "memw ( Sp + #U5:2 ) = Rt16" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 0 1 0 0 I I I I I t t t t - - 0 - - - - - - - - - - - - - + +:memw MemSpRelU5Lw,rt4l EndPackedLeft is iclass=14 & op2527=4 & op13=0 & MemSpRelU5Lw & rt4l & $(END_PACKED_LEFT) { + MemSpRelU5Lw = rt4l; + build EndPackedLeft; +} + +# (v4,left,5,7) sxtb -- "Rd16 = sxtb ( Rs16 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 - 1 0 1 0 1 s s s s d d d d - - - - - - - - - - - - - - - - + +:sxtb Rd4l,rs4l EndPackedLeft is iclass3031=1 & iclass28=1 & op2427=5 & Rd4l & rs4l & $(END_PACKED_LEFT) { + Rd4l = (rs4l << 24) s>> 24; + build EndPackedLeft; +} + +# (v4,left,3) sxtb -- "Rd16 = sxtb ( Ru16 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 0 1 0 1 u u u u d d d d - - 1 - - - - - - - - - - - - - + +:sxtb Rd4l,rs4l EndPackedLeft is iclass=3 & op2427=5 & op13=1 & Rd4l & rs4l & $(END_PACKED_LEFT) { + Rd4l = (rs4l << 24) s>> 24; + build EndPackedLeft; +} + +# (v4,left,5,7) sxth -- "Rd16 = sxth ( Rs16 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 - 1 0 1 0 0 s s s s d d d d - - - - - - - - - - - - - - - - + +:sxth Rd4l,rs4l EndPackedLeft is iclass3031=1 & iclass28=1 & op2427=4 & Rd4l & rs4l & $(END_PACKED_LEFT) { + Rd4l = (rs4l << 16) s>> 16; + build EndPackedLeft; +} + +# (v4,left,3) sxth -- "Rd16 = sxth ( Ru16 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 0 1 0 0 u u u u d d d d - - 1 - - - - - - - - - - - - - + +:sxth Rd4l,rs4l EndPackedLeft is iclass=3 & op2427=4 & op13=1 & Rd4l & rs4l & $(END_PACKED_LEFT) { + Rd4l = (rs4l << 16) s>> 16; + build EndPackedLeft; +} + +# (v4,left,5,7) zxth -- "Rd16 = zxth ( Rs16 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 - 1 0 1 1 0 s s s s d d d d - - - - - - - - - - - - - - - - + +:zxth Rd4l,rs4l EndPackedLeft is iclass3031=1 & iclass28=1 & op2427=6 & Rd4l & rs4l & $(END_PACKED_LEFT) { + Rd4l = rs4l & 0xffff; + build EndPackedLeft; +} + +# (v4,left,3) zxth -- "Rd16 = zxth ( Ru16 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 1 0 1 1 0 u u u u d d d d - - 1 - - - - - - - - - - - - - + +:zxth Rd4l,rs4l EndPackedLeft is iclass=3 & op2427=6 & op13=1 & Rd4l & rs4l & $(END_PACKED_LEFT) { + Rd4l = rs4l & 0xffff; + build EndPackedLeft; +} \ No newline at end of file diff --git a/Ghidra/Processors/Hexagon/data/languages/hexagon_right.sinc b/Ghidra/Processors/Hexagon/data/languages/hexagon_right.sinc new file mode 100644 index 0000000000..ed7f7c5226 --- /dev/null +++ b/Ghidra/Processors/Hexagon/data/languages/hexagon_right.sinc @@ -0,0 +1,776 @@ +# +# Second/Right Packed 'EE' Instructions +# + + +# (v4,right,2,3) add -- "Rd16 = add ( Rs16 , #-1 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 - - - - - - - - - - - - - - - 1 1 0 0 1 1 s s s s d d d d + +:add Rd4r,rs4r,MinusOne EndPackedRight is iclass2931=1 & op0813=0x33 & Rd4r & MinusOne & rs4r & $(END_PACKED_RIGHT) { + Rd4r = rs4r - 1; + build EndPackedRight; +} + +# (v4,right,2,3) add -- "Rd16 = add ( Rs16 , #1 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 - - - - - - - - - - - - - - - 1 1 0 0 0 1 s s s s d d d d + +:add Rd4r,rs4r,One EndPackedRight is iclass2931=1 & op0813=0x31 & Rd4r & One & rs4r & $(END_PACKED_RIGHT) { + Rd4r = rs4r + 1; + build EndPackedRight; +} + +# (v4,right,2) add -- "Rd16 = add ( Sp , #u6:2 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 - - - - - - - - - - - - - - 1 0 1 1 i i i i i i d d d d + +:add Rd4r,SP,Uimm8_0409_shift2 EndPackedRight is iclass=2 & op1013=11 & Rd4r & SP & Uimm8_0409_shift2 & $(END_PACKED_RIGHT) { + Rd4r = SP + zext(Uimm8_0409_shift2); + build EndPackedRight; +} + +# (v4,right,2,3) add -- "Rx16 = add ( Rs16 , Rx16 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 - - - - - - - - - - - - - - - 1 1 1 0 0 0 s s s s x x x x + +:add Rd4r,rs4r,rd4r EndPackedRight is iclass2931=1 & op0813=0x38 & Rd4r & rd4r & rs4r & $(END_PACKED_RIGHT) { + Rd4r = rs4r + rd4r; + build EndPackedRight; +} + +# (v4,right,2) add -- "Rx16 = add ( Rx16 , #s7 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 - - - - - - - - - - - - - - 1 0 0 i i i i i i i x x x x + +:add Rd4r,rd4r,Simm8_0410 EndPackedRight is iclass=2 & op1113=4 & Rd4r & rd4r & Simm8_0410 & $(END_PACKED_RIGHT) { + Rd4r = rd4r + sext(Simm8_0410); + build EndPackedRight; +} + +# (v4,right,6,7) allocframe -- "allocframe ( #u5:3 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 - - - - - - - - - - - - - - - 1 1 1 1 0 i i i i i - - - - +# +# (v4,right,10,11) allocframe -- "allocframe ( #u5:3 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 - - - - - - - - - - - - - - - 1 1 1 1 0 i i i i i - - - - + +:allocframe Uimm8_0408_shift3 EndPackedRight is (iclass2931=3 | iclass2931=5) & op0913=0x1e & Uimm8_0408_shift3 & $(END_PACKED_RIGHT) { + allocframe(SP, Uimm8_0408_shift3); + build EndPackedRight; +} + +# (v4,right,12,13) allocframe -- "allocframe ( #u5:3 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 - - - - - - - - - - - - - - - - 1 1 1 0 i i i i i - - - - + +:allocframe Uimm8_0408_shift3 EndPackedRight is iclass2931=6 & op0912=14 & Uimm8_0408_shift3 & $(END_PACKED_RIGHT) { + allocframe(SP, Uimm8_0408_shift3); + build EndPackedRight; +} + +# (v4,right,14,15) allocframe -- "allocframe ( #u5:3 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 - - - - - - - - - - - - - - - 0 1 1 1 0 i i i i i - - - - + +:allocframe Uimm8_0408_shift3 EndPackedRight is iclass2931=7 & op0913=0x0e & Uimm8_0408_shift3 & $(END_PACKED_RIGHT) { + allocframe(SP, Uimm8_0408_shift3); + build EndPackedRight; +} + +# (v4,right,2,3) and -- "Rd16 = and ( Rs16 , #1 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 - - - - - - - - - - - - - - - 1 1 0 0 1 0 s s s s d d d d + +:and Rd4r,rs4r,One EndPackedRight is iclass2931=1 & op0813=0x32 & Rd4r & One & rs4r & $(END_PACKED_RIGHT) { + Rd4r = rs4r & 1; + build EndPackedRight; +} + +# (v4,right,2,3) and -- "Rd16 = and ( Rs16 , #255 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 - - - - - - - - - - - - - - - 1 1 0 1 1 1 s s s s d d d d + +:and Rd4r,rs4r,FF EndPackedRight is iclass2931=1 & op0813=0x37 & Rd4r & FF & rs4r & $(END_PACKED_RIGHT) { + Rd4r = rs4r & 0xff; + build EndPackedRight; +} + +# (v4,right,2,3) assign -- "Rd16 = #-1" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 - - - - - - - - - - - - - - - 1 1 1 0 1 + + 0 + + d d d d + +:assign Rd4r,MinusOne EndPackedRight is iclass2931=1 & op13=1 & op0412=0x1a0 & Rd4r & MinusOne & $(END_PACKED_RIGHT) { + Rd4r = -1; + build EndPackedRight; +} + +# (v4,right,2) assign -- "Rd16 = #u6" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 - - - - - - - - - - - - - - 1 0 1 0 i i i i i i d d d d + +:assign Rd4r,Uimm8_0409 EndPackedRight is iclass=2 & op1013=10 & Rd4r & Uimm8_0409 & $(END_PACKED_RIGHT) { + Rd4r = zext(Uimm8_0409); + build EndPackedRight; +} + +# (v4,right,2,3) assign -- "Rd16 = Rs16" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 - - - - - - - - - - - - - - - 1 1 0 0 0 0 s s s s d d d d + +:assign Rd4r,rs4r EndPackedRight is iclass2931=1 & op13=1 & op0812=0x10 & Rd4r & rs4r & $(END_PACKED_RIGHT) { + Rd4r = rs4r; + build EndPackedRight; +} + +# (v4,right,2,3) assign -- "if ( ! p0 ) Rd16 = #0" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 - - - - - - - - - - - - - - - 1 1 1 0 1 + + 1 1 1 d d d d +# +# (v4,right,2,3) assign -- "if ( ! p0 .new ) Rd16 = #0" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 - - - - - - - - - - - - - - - 1 1 1 0 1 + + 1 0 1 d d d d +# +# (v4,right,2,3) assign -- "if ( p0 ) Rd16 = #0" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 - - - - - - - - - - - - - - - 1 1 1 0 1 + + 1 1 0 d d d d +# +# (v4,right,2,3) assign -- "if ( p0 .new ) Rd16 = #0" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 - - - - - - - - - - - - - - - 1 1 1 0 1 + + 1 0 0 d d d d + +:assign^P0Cond_N05_S04 rd4r,Zero EndPackedRight is iclass2931=1 & op13=1 & op0612=0x69 & rd4r & Zero & P0Cond_N05_S04 & $(END_PACKED_RIGHT) { + build P0Cond_N05_S04; + build EndPackedRight; + <> + if (ConditionReg == 0) goto ; + rd4r = 0; + +} + +# (v4,right,2,3) cmp.eq -- "p0 = cmp.eq ( Rs16 , #u2 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 - - - - - - - - - - - - - - - 1 1 1 0 0 1 s s s s - - i i + +:cmp.eq P0,rs4r,Uimm8_0001 EndPackedRight is iclass2931=1 & op13=1 & op0812=0x19 & P0 & rs4r & Uimm8_0001 & $(END_PACKED_RIGHT) { + bool:1 = (rs4r == zext(Uimm8_0001)); + P0.new = P0.new & (bool * 0xff); + build EndPackedRight; + <> + P0 = P0.new; +} + +# (v4,right,2,3) combine -- "Rdd8 = combine ( #n2 , #u2 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 - - - - - - - - - - - - - - - 1 1 1 1 + 0 - i i n n d d d + +:combine Rdd3r,Uimm2_0304,Uimm2_0506 EndPackedRight is iclass2931=1 & op0813=0x3c & Uimm2_0304 & Uimm2_0506 & Rdd3r & Zero & $(END_PACKED_RIGHT) { + Rdd3r = (zext(Uimm2_0304) << 32) + zext(Uimm2_0506); + build EndPackedRight; +} + +# (v4,right,2,3) combine -- "Rdd8 = combine ( #0 , Rs16 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 - - - - - - - - - - - - - - - 1 1 1 1 + 1 s s s s 0 d d d + +:combine Rdd3r,Zero,rs4r EndPackedRight is iclass2931=1 & op0813=0x3d & op3=0 & rs4r & Rdd3r & Zero & $(END_PACKED_RIGHT) { + Rdd3r = zext(rs4r); + build EndPackedRight; +} + +# (v4,right,2,3) combine -- "Rdd8 = combine ( Rs16 , #0 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 - - - - - - - - - - - - - - - 1 1 1 1 + 1 s s s s 1 d d d + +:combine Rdd3r,rs4r,Zero EndPackedRight is iclass2931=1 & op0813=0x3d & op3=1 & rs4r & Rdd3r & Zero & $(END_PACKED_RIGHT) { + Rdd3r = zext(rs4r) << 32; + build EndPackedRight; +} + +# (v4,right,0,1,4,5) dealloc_return -- "dealloc_return" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 - 0 - - - - - - - - - - - - - - - 1 1 1 1 1 1 0 1 - - - 0 - - + +:dealloc_return EndPackedRight is iclass31=0 & iclass29=0 & op13=1 & op0612=0x7d & op2=0 & $(END_PACKED_RIGHT) { + build EndPackedRight; + <> + deallocframe(FP); + return [LR]; +} + +# (v4,right,2,3) dealloc_return -- "dealloc_return" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 - - - - - - - - - - - - - - - 0 1 1 1 1 1 0 1 - - - 0 - - + +:dealloc_return EndPackedRight is iclass2931=1 & op13=0 & op0612=0x7d & op2=0 & $(END_PACKED_RIGHT) { + build EndPackedRight; + <> + deallocframe(FP); + return [LR]; +} + +# (v4,right,0,1,4,5) dealloc_return -- "if ( ! p0 ) dealloc_return" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 - 0 - - - - - - - - - - - - - - - 1 1 1 1 1 1 0 1 - - - 1 0 1 +# +# (v4,right,0,1,4,5) dealloc_return:nt -- "if ( ! p0 .new ) dealloc_return:nt" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 - 0 - - - - - - - - - - - - - - - 1 1 1 1 1 1 0 1 - - - 1 1 1 +# +# (v4,right,0,1,4,5) dealloc_return -- "if ( p0 ) dealloc_return" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 - 0 - - - - - - - - - - - - - - - 1 1 1 1 1 1 0 1 - - - 1 0 0 +# +# (v4,right,0,1,4,5) dealloc_return:nt -- "if ( p0 .new ) dealloc_return:nt" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 - 0 - - - - - - - - - - - - - - - 1 1 1 1 1 1 0 1 - - - 1 1 0 + +:dealloc_return^FlowP0Cond_N01_S00^NotTaken01 EndPackedRight is iclass31=0 & iclass29=0 & op13=1 & op0612=0x7d & op2=1 & FlowP0Cond_N01_S00 & NotTaken01 & $(END_PACKED_RIGHT) { + build FlowP0Cond_N01_S00; + build EndPackedRight; + <> + if (ConditionReg == 0) goto ; + deallocframe(FP); + return [LR]; + +} + +# (v4,right,2,3) dealloc_return -- "if ( ! p0 ) dealloc_return" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 - - - - - - - - - - - - - - - 0 1 1 1 1 1 0 1 - - - 1 0 1 +# +# (v4,right,2,3) dealloc_return:nt -- "if ( ! p0 .new ) dealloc_return:nt" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 - - - - - - - - - - - - - - - 0 1 1 1 1 1 0 1 - - - 1 1 1 +# +# (v4,right,2,3) dealloc_return -- "if ( p0 ) dealloc_return" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 - - - - - - - - - - - - - - - 0 1 1 1 1 1 0 1 - - - 1 0 0 +# +# (v4,right,2,3) dealloc_return:nt -- "if ( p0 .new ) dealloc_return:nt" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 - - - - - - - - - - - - - - - 0 1 1 1 1 1 0 1 - - - 1 1 0 + +:dealloc_return^FlowP0Cond_N01_S00^NotTaken01 EndPackedRight is iclass2931=1 & op13=0 & op0612=0x7d & op2=1 & FlowP0Cond_N01_S00 & NotTaken01 & $(END_PACKED_RIGHT) { + build FlowP0Cond_N01_S00; + build EndPackedRight; + <> + if (ConditionReg == 0) goto ; + deallocframe(FP); + return [LR]; + +} + +# (v4,right,0,1,4,5) deallocframe -- "deallocframe" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 - 0 - - - - - - - - - - - - - - - 1 1 1 1 1 1 0 0 - - - 0 - - + +:deallocframe EndPackedRight is iclass31=0 & iclass29=0 & op13=1 & op0612=0x7c & op2=0 & $(END_PACKED_RIGHT) { + build EndPackedRight; + <> + deallocframe(FP); +} + +# (v4,right,2,3) deallocframe -- "deallocframe" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 - - - - - - - - - - - - - - - 0 1 1 1 1 1 0 0 - - - 0 - - + +:deallocframe EndPackedRight is iclass2931=1 & op13=0 & op0612=0x7c & op2=0 & $(END_PACKED_RIGHT) { + build EndPackedRight; + <> + deallocframe(FP); +} + +# (v4,right,0,1,4,5) jumpr -- "jumpr Lr" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 - 0 - - - - - - - - - - - - - - - 1 1 1 1 1 1 1 1 - - - 0 - - + +:jumpr LR EndPackedRight is iclass31=0 & iclass29=0 & op13=1 & op0612=0x7f & op2=0 & LR & $(END_PACKED_RIGHT) { + dest:4 = LR; + build EndPackedRight; + <> + return [dest]; +} + +# (v4,right,2,3) jumpr -- "jumpr Lr" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 - - - - - - - - - - - - - - - 0 1 1 1 1 1 1 1 - - - 0 - - + +:jumpr LR EndPackedRight is iclass2931=1 & op13=0 & op0612=0x7f & op2=0 & LR & $(END_PACKED_RIGHT) { + dest:4 = LR; + build EndPackedRight; + <> + return [dest]; +} + +# (v4,right,0,1,4,5) jumpr -- "if ( ! p0 ) jumpr Lr" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 - 0 - - - - - - - - - - - - - - - 1 1 1 1 1 1 1 1 - - - 1 0 1 +# +# (v4,right,0,1,4,5) jumpr:nt -- "if ( ! p0 .new ) jumpr:nt Lr" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 - 0 - - - - - - - - - - - - - - - 1 1 1 1 1 1 1 1 - - - 1 1 1 +# +# (v4,right,0,1,4,5) jumpr -- "if ( p0 ) jumpr Lr" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 - 0 - - - - - - - - - - - - - - - 1 1 1 1 1 1 1 1 - - - 1 0 0 +# +# (v4,right,0,1,4,5) jumpr:nt -- "if ( p0 .new ) jumpr:nt Lr" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 - 0 - - - - - - - - - - - - - - - 1 1 1 1 1 1 1 1 - - - 1 1 0 + +# Conditional Return +:jumpr^FlowP0Cond_N01_S00^NotTaken01 LR EndPackedRight is iclass31=0 & iclass29=0 & op13=1 & op0612=0x7f & op2=1 & FlowP0Cond_N01_S00 & NotTaken01 & LR & $(END_PACKED_RIGHT) { + dest:4 = LR; + build FlowP0Cond_N01_S00; + build EndPackedRight; + <> + if (ConditionReg == 0) goto ; + return [dest]; + +} + +# (v4,right,2,3) jumpr -- "if ( ! p0 ) jumpr Lr" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 - - - - - - - - - - - - - - - 0 1 1 1 1 1 1 1 - - - 1 0 1 +# +# (v4,right,2,3) jumpr:nt -- "if ( ! p0 .new ) jumpr:nt Lr" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 - - - - - - - - - - - - - - - 0 1 1 1 1 1 1 1 - - - 1 1 1 +# +# (v4,right,2,3) jumpr -- "if ( p0 ) jumpr Lr" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 - - - - - - - - - - - - - - - 0 1 1 1 1 1 1 1 - - - 1 0 0 +# +# (v4,right,2,3) jumpr:nt -- "if ( p0 .new ) jumpr:nt Lr" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 - - - - - - - - - - - - - - - 0 1 1 1 1 1 1 1 - - - 1 1 0 + +:jumpr^FlowP0Cond_N01_S00^NotTaken01 LR EndPackedRight is iclass2931=1 & op13=0 & op0612=0x7f & op2=1 & FlowP0Cond_N01_S00 & NotTaken01 & LR & $(END_PACKED_RIGHT) { + dest:4 = LR; + build FlowP0Cond_N01_S00; + build EndPackedRight; + <> + if (ConditionReg == 0) goto ; + return [dest]; + +} + +# (v4,right,0,1,4,5) memb -- "Rd16 = memb ( Rs16 + #u3:0 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 - 0 - - - - - - - - - - - - - - - 1 1 0 i i i s s s s d d d d + +:memb Rd4r,MemRsRelU3Rb EndPackedRight is iclass31=0 & iclass29=0 & op1113=6 & MemRsRelU3Rb & Rd4r & $(END_PACKED_RIGHT) { + Rd4r = sext(MemRsRelU3Rb); + build EndPackedRight; +} + +# (v4,right,2,3) memb -- "Rd16 = memb ( Rs16 + #u3:0 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 - - - - - - - - - - - - - - - 0 1 0 i i i s s s s d d d d + +:memb Rd4r,MemRsRelU3Rb EndPackedRight is iclass2931=1 & op1113=2 & MemRsRelU3Rb & Rd4r & $(END_PACKED_RIGHT) { + Rd4r = sext(MemRsRelU3Rb); + build EndPackedRight; +} + +# (v4,right,6,7) memb -- "memb ( Rs16 + #u4:0 ) = #n1" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 - - - - - - - - - - - - - - - 1 1 0 0 1 n s s s s i i i i +# +# (v4,right,10,11) memb -- "memb ( Rs16 + #u4:0 ) = #n1" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 - - - - - - - - - - - - - - - 1 1 0 0 1 n s s s s i i i i + +:memb MemRsRelU4Rnb,Uimm1_08 EndPackedRight is (iclass2931=3 | iclass2931=5) & op0913=0x19 & MemRsRelU4Rnb & Uimm1_08 & $(END_PACKED_RIGHT) { + MemRsRelU4Rnb = Uimm1_08; + build EndPackedRight; +} + +# (v4,right,12,13) memb -- "memb ( Rs16 + #u4:0 ) = #n1" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 - - - - - - - - - - - - - - - - 1 0 0 1 n s s s s i i i i + +:memb MemRsRelU4Rnb,Uimm1_08 EndPackedRight is iclass2931=6 & op0912=9 & MemRsRelU4Rnb & Uimm1_08 & $(END_PACKED_RIGHT) { + MemRsRelU4Rnb = Uimm1_08; + build EndPackedRight; +} + +# (v4,right,14,15) memb -- "memb ( Rs16 + #u4:0 ) = #n1" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 - - - - - - - - - - - - - - - 0 1 0 0 1 n s s s s i i i i + +:memb MemRsRelU4Rnb,Uimm1_08 EndPackedRight is iclass2931=7 & op0913=9 & MemRsRelU4Rnb & Uimm1_08 & $(END_PACKED_RIGHT) { + MemRsRelU4Rnb = Uimm1_08; + build EndPackedRight; +} + +# (v4,right,6,7) memb -- "memb ( Rs16 + #u4:0 ) = Rt16" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 - - - - - - - - - - - - - - - 0 1 i i i i s s s s t t t t +# +# (v4,right,10,11) memb -- "memb ( Rs16 + #u4:0 ) = Rt16" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 - - - - - - - - - - - - - - - 0 1 i i i i s s s s t t t t + +:memb MemRsRelU4Rb,rt4r EndPackedRight is (iclass2931=3 | iclass2931=5) & op1213=1 & MemRsRelU4Rb & rt4r & $(END_PACKED_RIGHT) { + MemRsRelU4Rb = rt4r:1; + build EndPackedRight; +} + +# (v4,right,8,9) memb -- "memb ( Rs16 + #u4:0 ) = Rt16" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 - - - - - - - - - - - - - - - - 1 i i i i s s s s t t t t + +:memb MemRsRelU4Rb,rt4r EndPackedRight is iclass2931=4 & op12=1 & MemRsRelU4Rb & rt4r & $(END_PACKED_RIGHT) { + MemRsRelU4Rb = rt4r:1; + build EndPackedRight; +} + +# (v4,right,0,1,4,5) memd -- "Rdd8 = memd ( Sp + #u5:3 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 - 0 - - - - - - - - - - - - - - - 1 1 1 1 1 0 i i i i i d d d +:memd Rdd3r,MemSpRelU5Rd EndPackedRight is iclass31=0 & iclass29=0 & op0813=0x3e & MemSpRelU5Rd & Rdd3r & $(END_PACKED_RIGHT) { + Rdd3r = MemSpRelU5Rd; + build EndPackedRight; +} + +# (v4,right,2,3) memd -- "Rdd8 = memd ( Sp + #u5:3 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 - - - - - - - - - - - - - - - 0 1 1 1 1 0 i i i i i d d d + +:memd Rdd3r,MemSpRelU5Rd EndPackedRight is iclass2931=1 & op0813=0x1e & MemSpRelU5Rd & Rdd3r & $(END_PACKED_RIGHT) { + Rdd3r = MemSpRelU5Rd; + build EndPackedRight; +} + +# (v4,right,6,7) memd -- "memd ( Sp + #s6:3 ) = Rtt8" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 - - - - - - - - - - - - - - - 1 0 1 0 1 i i i i i i t t t +# +# (v4,right,10,11) memd -- "memd ( Sp + #s6:3 ) = Rtt8" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 - - - - - - - - - - - - - - - 1 0 1 0 1 i i i i i i t t t + +:memd MemSpRelS6Rd,rtt3r EndPackedRight is (iclass2931=3 | iclass2931=5) & op0913=0x15 & MemSpRelS6Rd & rtt3r & $(END_PACKED_RIGHT) { + MemSpRelS6Rd = rtt3r; + build EndPackedRight; +} + +# (v4,right,12,13) memd -- "memd ( Sp + #s6:3 ) = Rtt8" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 - - - - - - - - - - - - - - - - 0 1 0 1 i i i i i i t t t + +:memd MemSpRelS6Rd,rtt3r EndPackedRight is iclass2931=6 & op0912=5 & MemSpRelS6Rd & rtt3r & $(END_PACKED_RIGHT) { + MemSpRelS6Rd = rtt3r; + build EndPackedRight; +} + +# (v4,right,14,15) memd -- "memd ( Sp + #s6:3 ) = Rtt8" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 - - - - - - - - - - - - - - - 0 0 1 0 1 i i i i i i t t t + +:memd MemSpRelS6Rd,rtt3r EndPackedRight is iclass2931=7 & op0913=0x05 & MemSpRelS6Rd & rtt3r & $(END_PACKED_RIGHT) { + MemSpRelS6Rd = rtt3r; + build EndPackedRight; +} + +# (v4,right,0,1,4,5) memh -- "Rd16 = memh ( Rs16 + #u3:1 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 - 0 - - - - - - - - - - - - - - - 1 0 0 i i i s s s s d d d d + +:memh Rd4r,MemRsRelU3Rh EndPackedRight is iclass31=0 & iclass29=0 & op1113=4 & MemRsRelU3Rh & Rd4r & $(END_PACKED_RIGHT) { + Rd4r = sext(MemRsRelU3Rh); + build EndPackedRight; +} + +# (v4,right,2) memh -- "Rd16 = memh ( Rs16 + #u3:1 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 - - - - - - - - - - - - - - 0 0 0 i i i s s s s d d d d + +:memh Rd4r,MemRsRelU3Rh EndPackedRight is iclass=2 & op1113=0 & MemRsRelU3Rh & Rd4r & $(END_PACKED_RIGHT) { + Rd4r = sext(MemRsRelU3Rh); + build EndPackedRight; +} + +# (v4,right,6,7) memh -- "memh ( Rs16 + #u3:1 ) = Rt16" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 - - - - - - - - - - - - - - - 1 0 0 i i i s s s s t t t t +# +# (v4,right,10,11) memh -- "memh ( Rs16 + #u3:1 ) = Rt16" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 - - - - - - - - - - - - - - - 1 0 0 i i i s s s s t t t t + +:memh MemRsRelU3Rh,rt4r EndPackedRight is (iclass2931=3 | iclass2931=5) & op1113=4 & MemRsRelU3Rh & rt4r & $(END_PACKED_RIGHT) { + MemRsRelU3Rh = rt4r:2; + build EndPackedRight; +} + +# (v4,right,12,13) memh -- "memh ( Rs16 + #u3:1 ) = Rt16" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 - - - - - - - - - - - - - - - - 0 0 i i i s s s s t t t t + +:memh MemRsRelU3Rh,rt4r EndPackedRight is iclass2931=6 & op1112=0 & MemRsRelU3Rh & rt4r & $(END_PACKED_RIGHT) { + MemRsRelU3Rh = rt4r:2; + build EndPackedRight; +} + +# (v4,right,14,15) memh -- "memh ( Rs16 + #u3:1 ) = Rt16" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 - - - - - - - - - - - - - - - 0 0 0 i i i s s s s t t t t + +:memh MemRsRelU3Rh,rt4r EndPackedRight is iclass2931=7 & op1113=0 & MemRsRelU3Rh & rt4r & $(END_PACKED_RIGHT) { + MemRsRelU3Rh = rt4r:2; + build EndPackedRight; +} + +# (v4,right,0,1,4,5) memub -- "Rd16 = memub ( Rs16 + #u4:0 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 - 0 - - - - - - - - - - - - - - - 0 1 i i i i s s s s d d d d + +:memub Rd4r,MemRsRelU4Rb EndPackedRight is iclass31=0 & iclass29=0 & op1213=1 & MemRsRelU4Rb & Rd4r & $(END_PACKED_RIGHT) { + Rd4r = zext(MemRsRelU4Rb); + build EndPackedRight; +} + +# (v4,right,0,1,4,5) memuh -- "Rd16 = memuh ( Rs16 + #u3:1 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 - 0 - - - - - - - - - - - - - - - 1 0 1 i i i s s s s d d d d + +:memuh Rd4r,MemRsRelU3Rh EndPackedRight is iclass31=0 & iclass29=0 & op1113=5 & MemRsRelU3Rh & Rd4r & $(END_PACKED_RIGHT) { + Rd4r = zext(MemRsRelU3Rh); + build EndPackedRight; +} + +# (v4,right,2) memuh -- "Rd16 = memuh ( Rs16 + #u3:1 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 0 - - - - - - - - - - - - - - 0 0 1 i i i s s s s d d d d + +:memuh Rd4r,MemRsRelU3Rh EndPackedRight is iclass=2 & op1113=1 & MemRsRelU3Rh & Rd4r & $(END_PACKED_RIGHT) { + Rd4r = zext(MemRsRelU3Rh); + build EndPackedRight; +} + +# (v4,right,0,1,4,5) memw -- "Rd16 = memw ( Rs16 + #u4:2 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 - 0 - - - - - - - - - - - - - - - 0 0 i i i i s s s s d d d d + +:memw Rd4r,MemRsRelU4Rw EndPackedRight is iclass31=0 & iclass29=0 & op1213=0 & MemRsRelU4Rw & Rd4r & $(END_PACKED_RIGHT) { + Rd4r = MemRsRelU4Rw; + build EndPackedRight; +} + +# (v4,right,6,7) memw -- "memw ( Rs16 + #u4:2 ) = #n1" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 - - - - - - - - - - - - - - - 1 1 0 0 0 n s s s s i i i i +# +# (v4,right,10,11) memw -- "memw ( Rs16 + #u4:2 ) = #n1" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 - - - - - - - - - - - - - - - 1 1 0 0 0 n s s s s i i i i + +:memw StMemRsRelC15Rw,Uimm1_08 EndPackedRight is (iclass2931=3 | iclass2931=5) & op13=1 & op0912=8 & StMemRsRelC15Rw & Uimm1_08 & $(END_PACKED_RIGHT) { + StMemRsRelC15Rw = zext(Uimm1_08); + build EndPackedRight; +} + +# (v4,right,12,13) memw -- "memw ( Rs16 + #u4:2 ) = #n1" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 - - - - - - - - - - - - - - - - 1 0 0 0 n s s s s i i i i + +:memw StMemRsRelC15Rw,Uimm1_08 EndPackedRight is iclass2931=6 & op0912=8 & StMemRsRelC15Rw & Uimm1_08 & $(END_PACKED_RIGHT) { + StMemRsRelC15Rw = zext(Uimm1_08); + build EndPackedRight; +} + +# (v4,right,14,15) memw -- "memw ( Rs16 + #u4:2 ) = #n1" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 - - - - - - - - - - - - - - - 0 1 0 0 0 n s s s s i i i i + +:memw StMemRsRelC15Rw,Uimm1_08 EndPackedRight is iclass2931=7 & op13=0 & op0912=8 & StMemRsRelC15Rw & Uimm1_08 & $(END_PACKED_RIGHT) { + StMemRsRelC15Rw = zext(Uimm1_08); + build EndPackedRight; +} + +# (v4,right,8,9) memw -- "memw ( Rs16 + #u4:2 ) = Rt16" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 0 - - - - - - - - - - - - - - - - 0 i i i i s s s s t t t t + +:memw MemRsRelU4Rw,rt4r EndPackedRight is iclass2931=4 & op12=0 & MemRsRelU4Rw & rt4r & $(END_PACKED_RIGHT) { + MemRsRelU4Rw = rt4r; + build EndPackedRight; +} + +# (v4,right,6,7) memw -- "memw ( Rs16 + #u4:2 ) = Rt16" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 - - - - - - - - - - - - - - - 0 0 i i i i s s s s t t t t +# +# (v4,right,10,11) memw -- "memw ( Rs16 + #u4:2 ) = Rt16" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 - - - - - - - - - - - - - - - 0 0 i i i i s s s s t t t t + +:memw MemRsRelU4Rw,rt4r EndPackedRight is (iclass2931=5 | iclass2931=3) & op1213=0 & MemRsRelU4Rw & rt4r & $(END_PACKED_RIGHT) { + MemRsRelU4Rw = rt4r; + build EndPackedRight; +} + +# (v4,right,0,1,4,5) memw -- "Rd16 = memw ( Sp + #u5:2 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 - 0 - - - - - - - - - - - - - - - 1 1 1 1 0 i i i i i d d d d + +:memw Rd4r,MemSpRelU5Rw EndPackedRight is iclass31=0 & iclass29=0 & op0913=0x1e & MemSpRelU5Rw & Rd4r & $(END_PACKED_RIGHT) { + Rd4r = MemSpRelU5Rw; + build EndPackedRight; +} + +# (v4,right,2,3) memw -- "Rd16 = memw ( Sp + #u5:2 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 - - - - - - - - - - - - - - - 0 1 1 1 0 i i i i i d d d d + +:memw Rd4r,MemSpRelU5Rw EndPackedRight is iclass2931=1 & op0913=0x0e & MemSpRelU5Rw & Rd4r & $(END_PACKED_RIGHT) { + Rd4r = MemSpRelU5Rw; + build EndPackedRight; +} + +# (v4,right,6,7) memw -- "memw ( Sp + #u5:2 ) = Rt16" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 1 1 - - - - - - - - - - - - - - - 1 0 1 0 0 i i i i i t t t t +# +# (v4,right,10,11) memw -- "memw ( Sp + #u5:2 ) = Rt16" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 0 1 - - - - - - - - - - - - - - - 1 0 1 0 0 i i i i i t t t t + +:memw MemSpRelU5Rw,rt4r EndPackedRight is (iclass2931=3 | iclass2931=5) & op0913=0x14 & MemSpRelU5Rw & rt4r & $(END_PACKED_RIGHT) { + MemSpRelU5Rw = rt4r; + build EndPackedRight; +} + +# (v4,right,12,13) memw -- "memw ( Sp + #u5:2 ) = Rt16" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 0 - - - - - - - - - - - - - - - - 0 1 0 0 i i i i i t t t t + +:memw MemSpRelU5Rw,rt4r EndPackedRight is iclass2931=6 & op0912=4 & MemSpRelU5Rw & rt4r & $(END_PACKED_RIGHT) { + MemSpRelU5Rw = rt4r; + build EndPackedRight; +} + +# (v4,right,14,15) memw -- "memw ( Sp + #u5:2 ) = Rt16" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 1 1 1 - - - - - - - - - - - - - - - 0 0 1 0 0 i i i i i t t t t + +:memw MemSpRelU5Rw,rt4r EndPackedRight is iclass2931=7 & op0913=0x04 & MemSpRelU5Rw & rt4r & $(END_PACKED_RIGHT) { + MemSpRelU5Rw = rt4r; + build EndPackedRight; +} + +# (v4,right,2,3) sxtb -- "Rd16 = sxtb ( Rs16 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 - - - - - - - - - - - - - - - 1 1 0 1 0 1 s s s s d d d d + +:sxtb Rd4r,rs4r EndPackedRight is iclass2931=1 & op0813=0x35 & rs4r & Rd4r & $(END_PACKED_RIGHT) { + Rd4r = (rs4r << 24) s>> 24; + build EndPackedRight; +} + +# (v4,right,2,3) sxth -- "Rd16 = sxth ( Rs16 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 - - - - - - - - - - - - - - - 1 1 0 1 0 0 s s s s d d d d + +:sxth Rd4r,rs4r EndPackedRight is iclass2931=1 & op0813=0x34 & rs4r & Rd4r & $(END_PACKED_RIGHT) { + Rd4r = (rs4r << 16) s>> 16; + build EndPackedRight; +} + +# (v4,right,2,3) zxth -- "Rd16 = zxth ( Rs16 )" +# _________________________________________________________________________________________________ +# |31|30|29|28|27|26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|09|08|07|06|05|04|03|02|01|00| +# 0 0 1 - - - - - - - - - - - - - - - 1 1 0 1 1 0 s s s s d d d d + +:zxth Rd4r,rs4r EndPackedRight is iclass2931=1 & op0813=0x36 & rs4r & Rd4r & $(END_PACKED_RIGHT) { + Rd4r = rs4r & 0xffff; + build EndPackedRight; +} \ No newline at end of file diff --git a/Ghidra/Processors/Hexagon/data/patterns/Hexagon_patterns.xml b/Ghidra/Processors/Hexagon/data/patterns/Hexagon_patterns.xml new file mode 100755 index 0000000000..ac73cb6687 --- /dev/null +++ b/Ghidra/Processors/Hexagon/data/patterns/Hexagon_patterns.xml @@ -0,0 +1,72 @@ + + + + + + + 01000000 00111111 ........ 0.0..... + 01000000 00011111 ........ 001..... + + 11000000 00111111 ........ 0.0..... + 11000000 00011111 ........ 001..... + + 00011110 11000000 00011110 10010110 + 00011110 01000000 00011110 10010110 ........ 11...... ........ ........ + 00011110 01000000 00011110 10010110 ........ 00...... ........ ........ + 00011110 01000000 00011110 10010110 ........ 01...... ........ ........ ........ 11...... ........ ........ + 00011110 01000000 00011110 10010110 ........ 01...... ........ ........ ........ 00...... ........ ........ + 00011110 01000000 00011110 10010110 ........ 01...... ........ ........ ........ 01...... ........ ........ ........ 11...... ........ ........ + + .......0 11...... ........ 0101100. + .......0 01...... ........ 0101100. ........ 11...... ........ ........ + .......0 01...... ........ 0101100. ........ 00...... ........ ........ + .......0 01...... ........ 0101100. ........ 01...... ........ ........ ........ 11...... ........ ........ + .......0 01...... ........ 0101100. ........ 01...... ........ ........ ........ 00...... ........ ........ + .......0 01...... ........ 0101100. ........ 01...... ........ ........ ........ 01...... ........ ........ ........ 11...... ........ ........ + + 00000000 01000000 100..... 01010010 + 00000000 01000000 100..... 01010010 ........ 11...... ........ ........ + 00000000 01000000 100..... 01010010 ........ 00...... ........ ........ + 00000000 01000000 100..... 01010010 ........ 01...... ........ ........ ........ 11...... ........ ........ + 00000000 01000000 100..... 01010010 ........ 01...... ........ ........ ........ 00...... ........ ........ + 00000000 01000000 100..... 01010010 ........ 01...... ........ ........ ........ 01...... ........ ........ ........ 11...... ........ ........ + + + + + + + ........ .1000... 10011101 10100000 + ....0000 0011110. ........ 011..... + ....0000 0011110. ........ 101..... + ....0000 00.1110. ........ 110..... + ....0000 0001110. ........ 111..... + + + ........ 01...... ........ ........ ........ .1000... 10011101 10100000 + ........ 01...... ........ ........ ....0000 0011110. ........ 011..... + ........ 01...... ........ ........ ....0000 0011110. ........ 101..... + ........ 01...... ........ ........ ....0000 00.1110. ........ 110..... + ........ 01...... ........ ........ ....0000 0001110. ........ 111..... + + + ........ 01...... ........ ........ ........ 01...... ........ ........ ........ .1000... 10011101 10100000 + ........ 01...... ........ ........ ........ 01...... ........ ........ ....0000 0011110. ........ 011..... + ........ 01...... ........ ........ ........ 01...... ........ ........ ....0000 0011110. ........ 101..... + ........ 01...... ........ ........ ........ 01...... ........ ........ ....0000 00.1110. ........ 110..... + ........ 01...... ........ ........ ........ 01...... ........ ........ ....0000 0001110. ........ 111..... + + + ........ 01...... ........ ........ ........ 01...... ........ ........ ........ 01...... ........ ........ ........ 11000... 10011101 10100000 + ........ 01...... ........ ........ ........ 01...... ........ ........ ........ 01...... ........ ........ ....0000 0011110. ........ 011..... + ........ 01...... ........ ........ ........ 01...... ........ ........ ........ 01...... ........ ........ ....0000 0011110. ........ 101..... + ........ 01...... ........ ........ ........ 01...... ........ ........ ........ 01...... ........ ........ ....0000 00.1110. ........ 110..... + ........ 01...... ........ ........ ........ 01...... ........ ........ ........ 01...... ........ ........ ....0000 0001110. ........ 111..... + + + + + + + + diff --git a/Ghidra/Processors/Hexagon/data/patterns/patternconstraints.xml b/Ghidra/Processors/Hexagon/data/patterns/patternconstraints.xml new file mode 100755 index 0000000000..23217b7b69 --- /dev/null +++ b/Ghidra/Processors/Hexagon/data/patterns/patternconstraints.xml @@ -0,0 +1,5 @@ + + + Hexagon_patterns.xml + + \ No newline at end of file diff --git a/Ghidra/Processors/Hexagon/developer_scripts/VerifyHexagonTestVectors.java b/Ghidra/Processors/Hexagon/developer_scripts/VerifyHexagonTestVectors.java new file mode 100755 index 0000000000..abd80d2e8b --- /dev/null +++ b/Ghidra/Processors/Hexagon/developer_scripts/VerifyHexagonTestVectors.java @@ -0,0 +1,1201 @@ +/* ### + * IP: GHIDRA + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +//Verify Hexagon test vectors with external .s file +//@category Languages + +import java.io.*; +import java.math.BigInteger; +import java.util.*; + +import ghidra.app.script.GhidraScript; +import ghidra.program.model.address.*; +import ghidra.program.model.lang.Language; +import ghidra.program.model.lang.Register; +import ghidra.program.model.listing.*; +import ghidra.program.model.mem.Memory; +import ghidra.program.model.symbol.Symbol; +import ghidra.program.model.symbol.SymbolType; +import ghidra.util.Msg; +import ghidra.util.StringUtilities; +import ghidra.util.exception.AssertException; + +public class VerifyHexagonTestVectors extends GhidraScript { + + Memory memory; + Listing listing; + BookmarkManager bookmarkMgr; + + Map mismatchMap = new HashMap(); + + List labels; + + @Override + protected void run() throws Exception { + + if (currentProgram == null || + !"Hexagon".equals(currentProgram.getLanguage().getProcessor().toString())) { + popup("Current program is not a Hexagon binary!"); + return; + } + + memory = currentProgram.getMemory(); + listing = currentProgram.getListing(); + bookmarkMgr = currentProgram.getBookmarkManager(); + + buildRegisterRenameMap(); + + buildLabelList(); // original label use should be replaced by address + + File tvFile = askFile("Choose Hexagon Test Vector .s File", "Open"); + if (tvFile == null) { + return; + } + + OrigInstructionEnumeration origInstrEnumeration = new OrigInstructionEnumeration(tvFile); + GhidraInstructionEnumeration ghidraInstrEnumeration = new GhidraInstructionEnumeration(); + + OrigInstruction nextOrigInstr = null; + GhidraInstruction nextGhidraInstr = null; + while (true) { + + if (nextOrigInstr == null && origInstrEnumeration.hasMoreElements()) { + nextOrigInstr = origInstrEnumeration.nextElement(); + } + + if (nextGhidraInstr == null && ghidraInstrEnumeration.hasMoreElements()) { + nextGhidraInstr = ghidraInstrEnumeration.nextElement(); + } + + if (nextOrigInstr == null) { + if (nextGhidraInstr == null) { + break; // done + } + markError(nextGhidraInstr.addr, "Sync Error", "Ran out of test vectors early"); + Msg.showError(this, null, "Test Vector Sync Error", + "Ran out of test vectors early at " + nextGhidraInstr.addr); + break; + } + + if (nextGhidraInstr == null) { + Msg.showError(this, null, "Test Vector Sync Error", + "Ran out of instruction memory early " + tvFile.getName() + ":" + + nextOrigInstr.lineNo); + break; + } + + if (!"nop".equals(nextOrigInstr.instr)) { + // skip injected nop + // NOTE: this may cause endloop's to be lost + while ("nop".equals(nextGhidraInstr.instr)) { + if (ghidraInstrEnumeration.hasMoreElements()) { + nextGhidraInstr = ghidraInstrEnumeration.nextElement(); + } + else { + break; + } + } + } + + if (nextOrigInstr.hasAssignment()) { + if (nextGhidraInstr.mnemonic != null && + nextOrigInstr.instr.replace(" ", "").indexOf(nextGhidraInstr.mnemonic) >= 0) { + nextGhidraInstr.assumeAssignment(nextOrigInstr.isMemStore()); + } + } + + String origInstr = nextOrigInstr.toString().replace(" ", "").toUpperCase(); + String ghidraInstr = nextGhidraInstr.toString(true).replace(" ", "").toUpperCase(); + if (!origInstr.equals(ghidraInstr)) { + String key = origInstr + ghidraInstr; + Mismatch mismatch = mismatchMap.get(key); + if (mismatch != null) { + ++mismatch.count; + } + else { + mismatch = new Mismatch(nextOrigInstr, nextGhidraInstr); + mismatchMap.put(key, mismatch); + } + } + + nextOrigInstr = null; + nextGhidraInstr = null; + + } + + ArrayList list = new ArrayList(); + list.addAll(mismatchMap.values()); + Collections.sort(list, new Comparator() { + + @Override + public int compare(Mismatch arg0, Mismatch arg1) { + return arg0.origInstr.lineNo - arg1.origInstr.lineNo; + } + }); + + for (Mismatch mismatch : list) { + + String lineNo = + StringUtilities.pad(Integer.toString(mismatch.origInstr.lineNo), ' ', 5); + String instr = StringUtilities.pad(mismatch.origInstr.toString(), ' ', 50); + + String tail = ""; + if (mismatch.count > 1) { + tail = " (" + mismatch.count + " occurances)"; + } + + System.out.println( + lineNo + ": " + instr + " >?> " + mismatch.ghidraInstr.addr.toString() + ": " + + mismatch.ghidraInstr.toString(true) + tail); + + } + } + + private void buildLabelList() { + labels = new ArrayList(); + for (Symbol s : currentProgram.getSymbolTable().getAllSymbols(false)) { + if (s.getSymbolType() == SymbolType.LABEL) { + labels.add(s); + } + } + } + + private class Mismatch { + + int count = 1; + OrigInstruction origInstr; + GhidraInstruction ghidraInstr; + + Mismatch(OrigInstruction origInstr, GhidraInstruction ghidraInstr) { + this.origInstr = origInstr; + this.ghidraInstr = ghidraInstr; + } + } + + private static final long R_REG_BASE_ADDR = 0; // 0-31 + private static final long C_REG_BASE_ADDR = 0x200; // 0-13,24-29 + private static final long G_REG_BASE_ADDR = 0x400; // 0-3, 24-29 + private static final long S_REG_BASE_ADDR = 0x800; // 0-63 + + private Map regRenameMap = new HashMap(); + + private void buildRegisterRenameMap() { + addRegisterRange(R_REG_BASE_ADDR, 0, 31, "R"); + addRegisterRange(C_REG_BASE_ADDR, 0, 13, "C"); + addRegisterRange(C_REG_BASE_ADDR, 24, 29, "C"); + addRegisterRange(G_REG_BASE_ADDR, 0, 3, "G"); + addRegisterRange(G_REG_BASE_ADDR, 24, 29, "G"); + addRegisterRange(S_REG_BASE_ADDR, 0, 63, "S"); + } + + private void addRegisterRange(long baseOffset, int startIndex, int endIndex, String regPrefix) { + AddressFactory addrFactory = currentProgram.getAddressFactory(); + AddressSpace regSpace = addrFactory.getRegisterSpace(); + Language lang = currentProgram.getLanguage(); + for (int i = startIndex; i < (endIndex + 1); i++) { + Address regAddr = regSpace.getAddress(baseOffset + ((i - startIndex) * 4)); + Register reg = lang.getRegister(regAddr, 4); + if (reg == null) { + throw new AssertException("Register expected at " + regAddr.toString(true)); + } + String defaultName = regPrefix + i; + //System.out.println("Reg: " + defaultName); + if (defaultName.equals(reg.getName())) { + continue; + } + regRenameMap.put(defaultName, reg.getName()); + } + } + + private void markError(Address addr, String type, String msg) { + if (bookmarkMgr.getBookmarks(addr).length == 0) { + bookmarkMgr.setBookmark(addr, BookmarkType.ERROR, type, msg); + } + } + + private class OrigInstructionEnumeration implements Enumeration { + + private List testVectors; + private int nextIndex = 0; + private OrigInstruction nextElement; + private OrigInstruction nextNextElement; + + OrigInstructionEnumeration(File tvFile) throws IOException { + testVectors = readInstructions(tvFile); + } + + @Override + public boolean hasMoreElements() { + if (nextElement == null && nextIndex < testVectors.size()) { + if (nextNextElement != null) { + nextElement = nextNextElement; + nextNextElement = null; + } + else { + getNextElement(); + } + } + return nextElement != null; + } + + private void getNextElement() { + + TestVector testVector = testVectors.get(nextIndex++); + String origInstrStr = testVector.instr; + + int index = origInstrStr.indexOf(';'); + if (index > 0) { + String left = origInstrStr.substring(0, index).trim(); + nextElement = new OrigInstruction(testVector.lineNo, left, true, false, false); + origInstrStr = origInstrStr.substring(index + 1).trim(); + } + + // check for endloop elements + boolean endloop0 = false; + boolean endloop1 = false; + try { + while (testVectors.get(nextIndex).instr.startsWith(":endloop")) { + String endloop = testVectors.get(nextIndex++).instr; + if (endloop.endsWith("0")) { + endloop0 = true; + } + else if (endloop.endsWith("1")) { + endloop1 = true; + } + } + } + catch (IndexOutOfBoundsException e) { + // ignore + } + + if (nextElement != null) { + nextNextElement = + new OrigInstruction(testVector.lineNo, origInstrStr, false, endloop0, endloop1); + } + else { + nextElement = + new OrigInstruction(testVector.lineNo, origInstrStr, false, endloop0, endloop1); + } + } + + @Override + public OrigInstruction nextElement() { + hasMoreElements(); + OrigInstruction instr = nextElement; + nextElement = null; + return instr; + } + + } + + private class GhidraInstructionEnumeration implements Enumeration { + + Address nextInstrAddr; + GhidraInstruction nextElement; + GhidraInstruction nextNextElement; + Register packetOffsetCtxReg; + + GhidraInstructionEnumeration() { + nextInstrAddr = memory.getMinAddress(); + packetOffsetCtxReg = currentProgram.getLanguage().getRegister("packetOffset"); + } + + @Override + public boolean hasMoreElements() { + if (nextElement == null) { + if (nextNextElement != null) { + nextElement = nextNextElement; + nextNextElement = null; + } + else { + getNextElement(); + } + } + return nextElement != null; + } + + private void getNextElement() { + if (nextInstrAddr == null) { + return; + } + if (!memory.contains(nextInstrAddr)) { + nextInstrAddr = null; + return; + } + Instruction instr = listing.getInstructionAt(nextInstrAddr); + if (instr == null) { + nextElement = new GhidraInstruction(nextInstrAddr, null); + } + else if (instr.toString().startsWith("immext")) { + nextInstrAddr = nextInstrAddr.add(4); + getNextElement(); + return; + } + else { + String instrStr = instr.toString(); + + Address[] flows = instr.getFlows(); + if (flows.length == 1) { + + // Replace absolute flow address with relative offset + + String flowOffsetStr = "0x" + flows[0].toString(); + + BigInteger value = instr.getValue(packetOffsetCtxReg, false); + int packetOffset = (int) (value != null ? value.longValue() : 0); + + Address packetStartAddr = instr.getMinAddress().subtract(packetOffset * 4); + long relOffset = flows[0].subtract(packetStartAddr); + if ((relOffset & 0xc0000000L) == 0xc0000000L) { + relOffset = (relOffset << 32) >> 32; // sign fixup + } + + boolean isNegative = relOffset < 0; + String relOffsetStr; + if (isNegative) { + relOffsetStr = "#-0x" + Long.toHexString(-relOffset); + } + else { + relOffsetStr = "#0x" + Long.toHexString(relOffset); + } + + instrStr = instrStr.replace(flowOffsetStr, relOffsetStr); + + } + + int index = instrStr.indexOf(';'); + if (index > 0) { + String left = instrStr.substring(0, index).trim(); + nextElement = new GhidraInstruction(nextInstrAddr, left); + instrStr = instrStr.substring(index + 1).trim(); + } + + if (nextElement != null) { + nextNextElement = new GhidraInstruction(nextInstrAddr, instrStr); + } + else { + nextElement = new GhidraInstruction(nextInstrAddr, instrStr); + } + + } + nextInstrAddr = nextInstrAddr.add(4); + } + + @Override + public GhidraInstruction nextElement() { + hasMoreElements(); + GhidraInstruction instr = nextElement; + nextElement = null; + return instr; + } + + } + + private class OrigInstruction { + + private boolean isLeft; + private int lineNo; + private String instr; + private boolean endloop0; + private boolean endloop1; + + OrigInstruction(int lineNo, String instr, boolean isLeft, boolean endloop0, + boolean endloop1) { + this.lineNo = lineNo; + this.instr = instr; + this.isLeft = isLeft; + this.endloop0 = endloop0; + this.endloop1 = endloop1; + parse(); + } + + boolean isLeftInstruction() { + return isLeft; + } + + boolean hasAssignment() { + if (isMemStore()) { + return true; + } + int equalIndex = instr.indexOf('='); + int parenIndex = instr.indexOf('('); + if (parenIndex > 0 && instr.startsWith("if ")) { + parenIndex = instr.indexOf('(', parenIndex + 1); + } + return equalIndex > 0 && (parenIndex < 0 || parenIndex > equalIndex); + } + + boolean isMemStore() { + int memOpIndex = instr.indexOf("mem"); + int equalIndex = instr.indexOf('='); + + return (memOpIndex >= 0 && memOpIndex < equalIndex); + } + + private void parse() { + + // Add missing conditional parens + addParens(); + + // Rename registers + for (String oldName : regRenameMap.keySet()) { + renameRegister(oldName, regRenameMap.get(oldName)); + } + + // ignore ## - treat as # + instr = instr.replace("##", "#"); + + // Convert shift expressions to single constant e.g., (#0x2 << 2) + fixShiftedConstantExpression(); + + // Convert decimal constants to hex + changeDecimalToHex(); + + // ignore << #0x0 + instr = instr.replace("<< #0x0", ""); + + replaceLabels(); + + } + + private void replaceLabels() { + for (Symbol s : labels) { + if (instr.indexOf(s.getName()) >= 0) { + String addrStr = "0x" + s.getAddress().toString(); + instr = instr.replace(s.getName(), addrStr); + } + } + } + + private void addParens() { + if (!instr.startsWith("if ")) { + return; + } + // Assumes lower-case mnemonic and upper-case reg name + + int condStartIndex = -1; + int condEndIndex = -1; + + int index = 2; + int mode = 0; + while (index < instr.length() && condEndIndex < 0) { + char c = instr.charAt(index); + switch (mode) { + case 0: // looking for start + if (c == '(') { + return; + } + if (c == '!') { + condStartIndex = index; + } + else if (c != ' ') { + if (condStartIndex < 0) { + condStartIndex = index; + } + mode = 1; + } + break; + case 1: // on-reg + if (c == ' ') { + mode = 2; + } + break; + case 2: // after reg + if (c == '.') { + if (instr.substring(index).startsWith(".new")) { + index += 3; + } + else { + return; // unexpected + } + } + else if (c != ' ') { + condEndIndex = index; + } + break; + } + ++index; + } + + if (condEndIndex > 0) { + + instr = instr.substring(0, condStartIndex) + "( " + + instr.substring(condStartIndex, condEndIndex) + ") " + + instr.substring(condEndIndex); + } + } + + private void fixShiftedConstantExpression() { + try { + for (int index = instr.indexOf("#("); index >= 0 && index < instr.length(); index = + instr.indexOf("#(", index)) { + + int expEndIndex = instr.indexOf(')', index); + if (expEndIndex <= 0) { + return; // unexpected + } + + long expVal = getShiftedConstantValue(instr.substring(index + 2, expEndIndex)); + + boolean isNegative = expVal < 0; + String prefix = "#0x"; + if (isNegative) { + prefix = "#-0x"; + expVal = -expVal; + } + instr = instr.substring(0, index) + prefix + Long.toHexString(expVal) + + instr.substring(expEndIndex + 1); + + ++index; + } + } + catch (NumberFormatException e) { + Msg.error(this, e.getMessage()); + } + } + + private long getShiftedConstantValue(String constantShiftExp) throws NumberFormatException { + int shiftIndex = constantShiftExp.indexOf("<<"); + + String leftConstStr = (shiftIndex < 0) ? constantShiftExp + : constantShiftExp.substring(0, shiftIndex).trim(); + + boolean isNegative = leftConstStr.startsWith("-"); + if (isNegative) { + leftConstStr = leftConstStr.substring(1); + } + long leftConst; + if (leftConstStr.startsWith("0x")) { + leftConstStr = leftConstStr.substring(2); + leftConst = Long.parseLong(leftConstStr, 16); + } + else { + leftConst = Long.parseLong(leftConstStr); + } + if (isNegative) { + leftConst = -leftConst; + } + + if (shiftIndex < 0) { + return leftConst; + } + + String rightConstStr = constantShiftExp.substring(shiftIndex + 2).trim(); + int rightConst = Integer.parseInt(rightConstStr); + return leftConst << rightConst; + } + + private void changeDecimalToHex() { + for (int index = instr.indexOf('#'); index >= 0 && index < (instr.length() - 1); index = + instr.indexOf('#', index)) { + if (instr.charAt(++index) == '-') { + ++index; + } + if (instr.substring(index).startsWith("0x")) { + continue; // already hex + } + int valStartIndex = index; + StringBuilder buf = new StringBuilder(); + while (index < instr.length()) { + char c = instr.charAt(index); + if (!Character.isDigit(c)) { + break; + } + buf.append(c); + ++index; + } + if (buf.length() == 0) { + continue; + } + int val = Integer.parseInt(buf.toString()); + String hexStr = "0x" + Integer.toHexString(val); + instr = instr.substring(0, valStartIndex) + hexStr + + instr.substring(valStartIndex + buf.length()); + } + } + + private void renameRegister(String oldName, String newName) { + // Assume only 32-bit regs + int nameLen = oldName.length(); + int newNameLen = newName.length(); + for (int index = instr.indexOf(oldName); index >= 0 && index < instr.length(); index = + instr.indexOf(oldName, index)) { + int indexAfterName = index + nameLen; + if ((index == 0 || instr.charAt(index - 1) != ':') && + (indexAfterName == instr.length() || (instr.charAt(indexAfterName) != ':') && + !Character.isDigit(instr.charAt(indexAfterName)))) { + instr = instr.substring(0, index) + newName + instr.substring(indexAfterName); + index += newNameLen; + } + else { + index = indexAfterName; + } + } + } + + @Override + public String toString() { + StringBuilder buf = new StringBuilder(instr); + if (endloop0) { + buf.append(" :endloop0"); + } + if (endloop1) { + buf.append(" :endloop1"); + } + return buf.toString(); + } + + } + + private class GhidraOperand { + + String str; + + GhidraOperand(String str) { + this.str = str.replace("##", "#"); // ignore ## - treat as # + this.str = this.str.replace("#0)", "#0x0)"); + removeZeroPadding(); + fixDoubleRegs(); + } + + private void removeZeroPadding() { + for (int index = str.indexOf("#0x0"); index >= 0 && index < str.length(); index = + str.indexOf("#0x0", index)) { + + index += 3; + int startIndex = -1; + + while (index < (str.length() - 1) && str.charAt(index) == '0') { + char nextChar = str.charAt(index + 1); + if (!Character.isDigit(nextChar)) { + break; + } + if (startIndex < 0) { + startIndex = index; + } + ++index; + } + + if (startIndex > 0) { + str = str.substring(0, startIndex) + str.substring(index); + } + } + } + + private void fixDoubleRegs() { + for (int index = 0; index <= str.length() - 4; ++index) { + char c = str.charAt(index); + if (c != 'R' && c != 'S' && c != 'C' && c != 'G') { + continue; + } + int numLen = getRegNumberLength(index + 1); + if (numLen < 0) { + continue; + } + index += numLen; + if (c == str.charAt(index + 1)) { + str = str.substring(0, index + 1) + ":" + str.substring(index + 2); + } + } + } + + private int getRegNumberLength(int startIndex) { + if (startIndex >= str.length() - 2) { + return -1; + } + if (!Character.isDigit(str.charAt(startIndex++))) { + return -1; + } + if (!Character.isDigit(str.charAt(startIndex))) { + return 1; + } + return 2; + } + + @Override + public String toString() { + return str; + } + + } + + private class GhidraInstruction { + + private Address addr; + private String instr; + private boolean endloop0; + private boolean endloop1; + + private GhidraOperand conditional; + private String mnemonic; + private String assignmentOperator; // = += -= etc. + private GhidraOperand outArg; + private List modifiers; // :sat :<<1 etc. + private List inArgs = new ArrayList(); + private boolean storeMemOp; + + GhidraInstruction(Address addr, String instr) { + this.addr = addr; + this.instr = instr; + parse(); + } + + boolean isMissing() { + return instr == null; + } + + @Override + public String toString() { + return toString(false); + } + + public String toString(boolean buildIt) { + if (instr == null) { + return "!MISSING!"; + } + StringBuilder buf = new StringBuilder(); + if (buildIt) { + if (conditional != null) { + buf.append("if ("); + buf.append(conditional.toString()); + buf.append(") "); + } + boolean isFlow = false; + if (outArg != null) { + boolean addParens = false; + if (mnemonic != null && inArgs.size() == 1 && storeMemOp) { + buf.append(mnemonic); + if (!outArg.str.startsWith("(")) { + buf.append('('); + addParens = true; + } + } + buf.append(outArg.toString()); + if (addParens) { + buf.append(')'); + } + buf.append(' '); + buf.append(assignmentOperator); + buf.append(' '); + } + if (mnemonic != null) { + if (!storeMemOp) { + buf.append(mnemonic); + } + } + else if (assignmentOperator == null) { + buf.append("!BAD-PARSE!"); + } + if (inArgs.size() == 1 && assignmentOperator != null && + (mnemonic == null || mnemonic.startsWith("mem"))) { + // omit parens + buf.append(' '); + buf.append(inArgs.get(0).toString()); + } + else if (inArgs.size() == 1 && mnemonic != null && + (mnemonic.startsWith("jump") || mnemonic.startsWith("call"))) { + + if (modifiers != null) { + for (String modifier : modifiers) { + buf.append(" :"); + buf.append(modifier); + } + } + + // omit parens + isFlow = true; + buf.append(' '); + buf.append(inArgs.get(0).toString()); + } + else if (inArgs.size() == 1 && inArgs.get(0).str.startsWith("(")) { + buf.append(inArgs.get(0).toString()); + } + else if (inArgs.size() != 0) { + buf.append('('); + for (int i = 0; i < inArgs.size(); i++) { + if (i != 0) { + buf.append(", "); + } + buf.append(inArgs.get(i).toString()); + } + buf.append(')'); + } + + if (!isFlow && modifiers != null) { + for (String modifier : modifiers) { + buf.append(" :"); + buf.append(modifier); + } + } + } + else { + buf.append(instr); + } + + if (endloop0) { + buf.append(" :endloop0"); + } + if (endloop1) { + buf.append(" :endloop1"); + } + return buf.toString(); + } + + boolean assumeAssignment(boolean storeMemOp) { + this.storeMemOp = storeMemOp; + if (assignmentOperator != null || outArg != null) { + return true; // already handled + } + if (inArgs.size() != 0) { + outArg = inArgs.remove(0); + assignmentOperator = "="; + return true; + } + return false; + } + + private void parse() { + if (instr == null) { + return; + } + String instrStr = instr; + int index = instrStr.indexOf(":endloop0"); + if (index > 0) { + instrStr = instrStr.replace(":endloop0", "").trim(); + endloop0 = true; + } + index = instrStr.indexOf(":endloop1"); + if (index > 0) { + instrStr = instrStr.replace(":endloop1", "").trim(); + endloop0 = true; + } + + instr = instrStr.trim(); + + index = instr.indexOf(' '); + if (index < 0) { + mnemonic = instr; + } + else { + mnemonic = instr.substring(0, index); + } + + if (mnemonic.startsWith("mem")) { + // normalize low halfword memory load/store + instr = instr.replace(".L", ""); + } + + if (index > 0) { + parseOperands(instr.substring(index).trim()); + } + +// if (instr.startsWith("assign")) { +// if (inArgs.size() == 2) { +// outArg = inArgs.remove(0); +// assignmentOperator = "="; +// } +// mnemonic = null; +// return; +// } + + index = indexOfSpecial(mnemonic); + if (index > 0) { + + String addOns = mnemonic.substring(index); + mnemonic = mnemonic.substring(0, index); + + // handle conditional + if (mnemonic != null && addOns.startsWith(".if")) { + if (addOns.charAt(3) == '(') { + index = addOns.indexOf(')'); + if (index > 0) { + conditional = new GhidraOperand(addOns.substring(4, index)); + addOns = addOns.substring(index + 1); + } + else { + mnemonic = null; // Bad mnemonic + } + } + else { + // assume conditional flow - use first argument + if (inArgs.size() >= 2) { + conditional = inArgs.remove(0); + addOns = addOns.substring(3); + } + else { + mnemonic = null; // Bad mnemonic + } + } + } + + // handle cmp modifiers .eq .lt etc. + if (mnemonic != null && addOns.startsWith(".")) { + mnemonic += "."; + index = 1; + while (index < addOns.length()) { + char c = addOns.charAt(index); + if (!Character.isLetter(c)) { + break; + } + mnemonic += c; + ++index; + } + addOns = addOns.substring(index); + } + + // explicit assignment operator - e.g., += -= ^= |= etc. + index = addOns.indexOf("="); + if (index >= 0) { + assignmentOperator = addOns.substring(0, index + 1); + addOns = addOns.substring(index + 1); + if (inArgs.size() != 0) { + outArg = inArgs.remove(0); + if (assignmentOperator == null) { + assignmentOperator = "="; + } + } + else { + mnemonic = null; // Bad mnemonic + } + } + + if (mnemonic != null && addOns.length() != 0) { + char modifierChar = addOns.charAt(0); + if (modifierChar != '.' && modifierChar != ':') { + mnemonic = modifierChar + mnemonic; + addOns = addOns.substring(1); + } + } + + // split-up modifiers + if (mnemonic != null && addOns.startsWith(":")) { + modifiers = new ArrayList(); +// TODO: Verify split + for (String modifier : addOns.substring(1).split(":")) { + if (!modifiers.add(modifier)) { + mnemonic = null; // duplicate + } + } + addOns = ""; // consumed everything + if (modifiers.isEmpty()) { + mnemonic = null; + } + } + + if (addOns.length() != 0) { + mnemonic = null; + } + + } + + if (mnemonic == null) { + Msg.error(this, "Failed to morph: " + instr); + return; + } + + // known assignments which are frequently switched at assembly time + if (instr.startsWith("assign")) { + assumeAssignment(false); + mnemonic = null; + } + else if (mnemonic.startsWith("cmp.")) { + assumeAssignment(false); + } + else if (mnemonic.startsWith("mem") && inArgs.size() == 2) { + assumeAssignment(inArgs.get(0).str.startsWith("(")); + } + +// if (assignmentOperator == null && inArgs.size() > 1) { +// checkPcodeForAssignment(); // TODO: won't work well for right-side packed instr +// } + + } + + private void parseOperands(String operands) { + + operands = operands.trim(); + if (operands.startsWith(",")) { + operands = operands.substring(1).trim(); + } + else if (operands.length() == 0) { + return; + } + + int index = 0; + int startIndex = 0; + int parenCnt = 0; + while (index < operands.length()) { + int leftParenIndex = operands.indexOf('(', index); + int rightParenIndex = operands.indexOf(')', index); + int commaIndex = operands.indexOf(',', index); + int endIndex = -1; + if (commaIndex < 0) { + endIndex = operands.length(); + } + else if (parenCnt == 0 && (leftParenIndex < 0 || commaIndex < leftParenIndex)) { + endIndex = commaIndex; + index = commaIndex; + } + else if (parenCnt > 0 || leftParenIndex < commaIndex) { + // inside group or new group starts before comma + if (leftParenIndex >= 0 && leftParenIndex < rightParenIndex) { + // new group starts before next closure + ++parenCnt; + index = leftParenIndex; + } + if (parenCnt > 0 && rightParenIndex >= 0) { + --parenCnt; + index = rightParenIndex; + } + } + + if (endIndex >= 0) { + inArgs.add(new GhidraOperand(operands.substring(startIndex, endIndex))); + startIndex = endIndex + 1; + index = endIndex; + endIndex = -1; + } + + ++index; + } + + if (startIndex < operands.length()) { + inArgs.add(new GhidraOperand(operands.substring(startIndex))); + } +// +// +// +// +// +// int parenIndex = operands.indexOf('('); +// int commaIndex = operands.indexOf(','); +// +//// if (parenIndex < 0) { +//// TODO: Verify split +// for (String opStr : operands.split(",")) { +// inArgs.add(new GhidraOperand(opStr)); +// } +// return; +// } +// +// if (commaIndex > 0 && commaIndex < parenIndex) { +// inArgs.add(new GhidraOperand(operands.substring(0, commaIndex))); +// parseOperands(operands.substring(commaIndex + 1)); +// return; +// } +// +// // assume no nested paren groups +// +// int rightParenIndex = operands.indexOf(')'); +// if (rightParenIndex > 0) { +// inArgs.add(new GhidraOperand(operands.substring(0, rightParenIndex + 1))); +// parseOperands(operands.substring(rightParenIndex + 1)); +// return; +// } + + // no closing paren found +// TODO: generate error + + } + } + + /** + * Find index of first special character. + * @param str + * @return index or -1 if whitespace or end-of-string encountered before + * matching a non-alpha or numeric character + */ + private static int indexOfSpecial(String str) { + for (int i = 0; i < str.length(); i++) { + char c = str.charAt(i); + if ((c >= 'A' && c <= 'Z') || (c >= 'a' && c <= 'z') || (c >= '0' && c <= '9') || + c == '_') { + continue; + } + if (c == ' ' || c == '\t') { + break; + } + return i; + } + return -1; + } + + private class TestVector { + final int lineNo; + final String instr; + + TestVector(int lineNo, String instr) { + this.lineNo = lineNo; + this.instr = instr; + } + } + + private List readInstructions(File tvFile) throws IOException { + + int row = 1; + ArrayList list = new ArrayList(); + BufferedReader r = new BufferedReader(new FileReader(tvFile)); + try { + String line; + while ((line = r.readLine()) != null) { + line = line.trim(); + if (line.endsWith(":")) { + // skip labels + continue; + } + int index = line.indexOf("//"); + if (index >= 0) { + line = line.substring(0, index).trim(); + } + boolean addEndLoop0 = false; + boolean addEndLoop1 = false; + index = line.indexOf(":endloop0"); + if (index >= 0) { + line = line.replace(":endloop0", "").trim(); + addEndLoop0 = true; + } + index = line.indexOf(":endloop1"); + if (index >= 0) { + line = line.replace(":endloop1", "").trim(); + addEndLoop1 = true; + } + if (line.startsWith("{") || line.startsWith("}")) { + line = line.substring(1).trim(); + } + if (line.endsWith("}")) { + line = line.substring(0, line.length() - 1).trim(); + } + if (line.endsWith(";")) { + line = line.substring(0, line.length() - 1).trim(); + } + if (line.length() != 0 && !line.startsWith(".")) { + list.add(new TestVector(row, line)); + } + if (addEndLoop0) { + list.add(new TestVector(row, ":endloop0")); + } + if (addEndLoop1) { + list.add(new TestVector(row, ":endloop1")); + } + ++row; + } + } + finally { + r.close(); + } + return list; + } + +} diff --git a/Ghidra/Processors/Hexagon/src/main/java/ghidra/app/plugin/core/analysis/HexagonAnalyzer.java b/Ghidra/Processors/Hexagon/src/main/java/ghidra/app/plugin/core/analysis/HexagonAnalyzer.java new file mode 100755 index 0000000000..29f904e3e2 --- /dev/null +++ b/Ghidra/Processors/Hexagon/src/main/java/ghidra/app/plugin/core/analysis/HexagonAnalyzer.java @@ -0,0 +1,226 @@ +/* ### + * IP: GHIDRA + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +package ghidra.app.plugin.core.analysis; + +import ghidra.app.services.AnalysisPriority; +import ghidra.app.util.viewer.field.HexagonParallelInstructionHelper; +import ghidra.program.model.address.*; +import ghidra.program.model.data.DataType; +import ghidra.program.model.lang.*; +import ghidra.program.model.listing.*; +import ghidra.program.model.pcode.Varnode; +import ghidra.program.model.scalar.Scalar; +import ghidra.program.model.symbol.*; +import ghidra.program.util.SymbolicPropogator; +import ghidra.program.util.VarnodeContext; +import ghidra.util.exception.CancelledException; +import ghidra.util.task.TaskMonitor; + +public class HexagonAnalyzer extends ConstantPropagationAnalyzer { + private final static String PROCESSOR_NAME = "Hexagon"; + + private Register r25Register; + private Register lrRegister; + private Register lrNewRegister; + + HexagonParallelInstructionHelper helper = new HexagonParallelInstructionHelper(); + + protected int pass; + + public HexagonAnalyzer() { + super(PROCESSOR_NAME); + setPriority(AnalysisPriority.CODE_ANALYSIS.after()); + } + + @Override + public boolean canAnalyze(Program program) { + Language language = program.getLanguage(); + r25Register = program.getRegister("R25"); + lrRegister = program.getRegister("LR"); + lrNewRegister = program.getRegister("LR.new"); + if (language.getProcessor().equals(Processor.findOrPossiblyCreateProcessor("Hexagon")) && + r25Register != null && lrRegister != null && lrNewRegister != null) { + return true; + } + return false; + } + + @Override + + public AddressSetView flowConstants(final Program program, Address flowStart, + AddressSetView flowSet, final SymbolicPropogator symEval, final TaskMonitor monitor) + throws CancelledException { + + // follow all flows building up context + // use context to fill out addresses on certain instructions + ConstantPropagationContextEvaluator eval = + new ConstantPropagationContextEvaluator(monitor, trustWriteMemOption) { + @Override + public boolean evaluateContext(VarnodeContext context, Instruction instr) { +// if (instr.getMnemonicString().equals("assign")) { +// Register destReg = instr.getRegister(0); +// if (destReg.getBitLength() == 16) { +// String regName = destReg.getName(); +// Register shadowDest = +// program.getRegister(regName.substring(0, regName.length() - 1)); +// Scalar s = instr.getScalar(1); +// if (s != null) { +// context.setValue(shadowDest, s.getBigInteger()); +// } +// context.propogateResults(true); +// BigInteger rval = context.getValue(program.getRegister("R0"), false); +// Msg.info(this, rval == null ? "NULL" : rval.toString(16)); +// rval = context.getValue(program.getRegister("R0.L"), false); +// Msg.info(this, rval == null ? "NULL" : rval.toString(16)); +// rval = context.getValue(program.getRegister("R0.H"), false); +// Msg.info(this, rval == null ? "NULL" : rval.toString(16)); +// } +// } + + FlowType ftype = instr.getFlowType(); + if (ftype.isComputed() && ftype.isJump()) { + // TODO: MUST get the value... of the PC???? + Varnode destVal = null; // context.getRegisterVarnodeValue(indirectFlowDestReg); + if (destVal != null) { + if (isLinkRegister(context, destVal)) { + // need to set the return override + instr.setFlowOverride(FlowOverride.RETURN); + } + } + } + return false; + } + + private boolean isLinkRegister(VarnodeContext context, Varnode destVal) { + Address destAddr = destVal.getAddress(); + if (destVal.isRegister()) { + return (destAddr.equals(lrRegister.getAddress()) || + destAddr.equals(lrNewRegister.getAddress())); + } + else if (context.isSymbol(destVal) && destAddr.getOffset() == 0) { + String symbolSpaceName = destAddr.getAddressSpace().getName(); + return (symbolSpaceName.equals(lrRegister.getName()) || + symbolSpaceName.equals(lrNewRegister.getName())); + } + return false; + } + + @Override + public boolean evaluateReference(VarnodeContext context, Instruction instr, + int pcodeop, Address address, int size, DataType dataType, + RefType refType) { + + if (address.isExternalAddress()) { + return true; + } + + // do super check, then do our own checks + if (!super.evaluateReference(context, instr, pcodeop, address, size, dataType, + refType)) { + return false; + } + + if (refType.isData()) { +// // for instruction with more operands than two, will be a dual instruction +// // can only do this for single instructions. +// // Only way to tell if has a third operand and is not an empty string! +// List opRepList = instr.getDefaultOperandRepresentationList(2); +// if (opRepList != null && opRepList.size() != 0) { +// return true; +// } + // TODO: need to do this better. + // Maybe take a look at the register values to tag things on for read/write + // all Reads should be in (). Writes should be in () on the left side. + if (refType.isWrite()) { + // goes on first operand + instr.addOperandReference(0, address, refType, SourceType.ANALYSIS); + return false; + } + else if (refType.isRead()) { + // goes on second operand + instr.addOperandReference(1, address, refType, SourceType.ANALYSIS); + return false; + } + + } + // look backward for a good assign instruction that has this as a constant + // want to markup there if we find one. + return markupParallelInstruction(instr, refType, address); + } + + /** + * For parallel instruction effects, look back to see if there is a constant in the parallel chain + * to match this target address. + * + * @return true to just mark it up anywhere, false if we actually put the reference on here. + */ + private boolean markupParallelInstruction(Instruction instr, RefType refType, + Address address) { + Instruction prevInst = instr; + int count = 0; + while (helper.isParallelInstruction(prevInst) && count++ < 5) { + Address fallFrom = prevInst.getFallFrom(); + if (fallFrom == null) + break; + prevInst = program.getListing().getInstructionAt(fallFrom); + if (prevInst == null) + break; + int numOps = prevInst.getNumOperands(); + + for (int i = 0; i < numOps; i++) { + Scalar scalar = prevInst.getScalar(i); + if (scalar == null) + continue; + long unsignedValue = scalar.getUnsignedValue(); + if (unsignedValue == address.getOffset()) { + // found the value, mark it up + prevInst.addOperandReference(i, address, refType, + SourceType.ANALYSIS); + return false; + } + } + } + return true; // just go ahead and mark up the instruction + } + + @Override + public boolean evaluateDestination(VarnodeContext context, + Instruction instruction) { + FlowType flowType = instruction.getFlowType(); + if (!flowType.isJump()) { + return false; + } + // TODO: if this is a switch stmt, add to destSet + Reference[] refs = instruction.getReferencesFrom(); + if (refs.length <= 0 || + (refs.length == 1 && refs[0].getReferenceType().isData())) { + destSet.addRange(instruction.getMinAddress(), instruction.getMinAddress()); + } + return false; + } + }; + + eval.setTrustWritableMemory(trustWriteMemOption) + .setMinSpeculativeOffset(minSpeculativeRefAddress) + .setMaxSpeculativeOffset(maxSpeculativeRefAddress) + .setMinStoreLoadOffset(minStoreLoadRefAddress) + .setCreateComplexDataFromPointers(createComplexDataFromPointers); + + AddressSet resultSet = symEval.flowConstants(flowStart, flowSet, eval, true, monitor); + + return resultSet; + } +} diff --git a/Ghidra/Processors/Hexagon/src/main/java/ghidra/app/plugin/core/analysis/HexagonPrologEpilogAnalyzer.java b/Ghidra/Processors/Hexagon/src/main/java/ghidra/app/plugin/core/analysis/HexagonPrologEpilogAnalyzer.java new file mode 100755 index 0000000000..37db2616d1 --- /dev/null +++ b/Ghidra/Processors/Hexagon/src/main/java/ghidra/app/plugin/core/analysis/HexagonPrologEpilogAnalyzer.java @@ -0,0 +1,288 @@ +/* ### + * IP: GHIDRA + * NOTE: Need to review if these patterns are any indicators of code/original binary, even the address examples + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +package ghidra.app.plugin.core.analysis; + +import ghidra.app.cmd.function.CreateFunctionCmd; +import ghidra.app.services.*; +import ghidra.app.util.importer.MessageLog; +import ghidra.framework.options.Options; +import ghidra.program.model.address.Address; +import ghidra.program.model.address.AddressSetView; +import ghidra.program.model.lang.IncompatibleMaskException; +import ghidra.program.model.lang.MaskImpl; +import ghidra.program.model.listing.*; +import ghidra.program.model.mem.DumbMemBufferImpl; +import ghidra.program.model.symbol.SourceType; +import ghidra.util.Msg; +import ghidra.util.exception.*; +import ghidra.util.task.TaskMonitor; + +public class HexagonPrologEpilogAnalyzer extends AbstractAnalyzer { + private static final String NAME = "Hexagon Prolog/Epilog Functions"; + private static final String DESCRIPTION = + "Detects common Prolog/Epilog functions used within Hexagon code and marks them as inline"; + + private final static String PROCESSOR_NAME = "Hexagon"; + + private final static String OPTION_NAME_FIXUP_FUNCTIONS = "Prolog/Epilog Function Fixup"; + + private static final String OPTION_DESCRIPTION_FIXUP_FUNCTIONS = + "Select fixup type which should be applied to Prolog functions (save registers) and Epilog functions (restore registers and dealloc frame)."; + + public enum FIXUP_TYPES { + Name_Only, Inline, Call_Fixup + } + + private FIXUP_TYPES fixupType = FIXUP_TYPES.Call_Fixup; + + // Call fixup names as defined in cspec + private final static String CALL_FIXUP_PROLOG_NAME = "prolog_save_regs"; + private final static String CALL_FIXUP_EPILOG_NAME = "prolog_restore_regs"; + + // TODO: These patterns may be incomplete + private static InstructionMaskValue NOP = new InstructionMaskValue(0xffff3fff, 0x7f000000); // nop - ignore parse bits + private static InstructionMaskValue JUMPR_LR = new InstructionMaskValue(0xffff3fff, 0x529f0000); // jumpr lr - ignore parse bits + private static InstructionMaskValue JUMP = new InstructionMaskValue(0xfe000001, 0x58000000); // jump - ignore parse bits + private static InstructionMaskValue MEMD_PUSH = + new InstructionMaskValue(0xfdff0000, 0xa5de0000); // memd (FP+#-nn), - ignore parse bits + private static InstructionMaskValue MEMD_POP = new InstructionMaskValue(0xfdff0000, 0x95de0000); // memd ,(FP+#-nn) - ignore parse bits + private static InstructionMaskValue DEALLOCFRAME = new InstructionMaskValue(0xffff3fff, + 0x901e001e); // deallocframe - ignore parse bits + private static InstructionMaskValue DEALLOC_RETURN = new InstructionMaskValue(0xffff3fff, + 0x961e001e); // deallocreturn - ignore parse bits + + public HexagonPrologEpilogAnalyzer() { + super(NAME, DESCRIPTION, AnalyzerType.FUNCTION_ANALYZER); + setDefaultEnablement(true); + setPriority(AnalysisPriority.CODE_ANALYSIS.before()); + } + + @Override + public boolean canAnalyze(Program program) { + if (!PROCESSOR_NAME.equals(program.getLanguage().getProcessor().toString())) { + return false; + } + return true; + } + + private boolean setPrologEpilog(Program program, Address entryPoint, boolean isProlog, + TaskMonitor monitor) { + Listing listing = program.getListing(); + Function function = listing.getFunctionAt(entryPoint); + if (function == null) { + CreateFunctionCmd cmd = new CreateFunctionCmd(entryPoint); + if (!cmd.applyTo(program, monitor)) { + return false; + } + function = cmd.getFunction(); + } + else if (function.isInline()) { + return true; + } + setPrologEpilog(function, isProlog); + return true; + } + + private void setPrologEpilog(Function function, boolean isProlog) { + + if (fixupType == FIXUP_TYPES.Inline) { + function.setInline(true); + Msg.info(this, "Set inline " + (isProlog ? "prolog" : "epilog") + " function at " + + function.getEntryPoint()); + } + else if (fixupType == FIXUP_TYPES.Call_Fixup) { + function.setCallFixup(isProlog ? CALL_FIXUP_PROLOG_NAME : CALL_FIXUP_EPILOG_NAME); + Msg.info(this, "Set call-fixup " + (isProlog ? "prolog" : "epilog") + " function at " + + function.getEntryPoint()); + } + + if (function.getSymbol().getSource() == SourceType.DEFAULT) { + String name = isProlog ? "prolog_save_regs@" : "epilog_restore_regs@"; + try { + function.setName(name + function.getEntryPoint(), SourceType.ANALYSIS); + } + catch (DuplicateNameException e) { + // ignore + } + catch (InvalidInputException e) { + throw new AssertException(e); + } + } + } + + @Override + public boolean added(Program program, AddressSetView set, TaskMonitor monitor, MessageLog log) + throws CancelledException { + + monitor.setMessage("Find Prologs and Epilogs..."); + monitor.initialize(set.getNumAddresses()); + + int cnt = 0; + for (Function function : program.getListing().getFunctions(set, true)) { + monitor.checkCancelled(); + monitor.setProgress(++cnt); + if (function.isInline() || function.getCallFixup() != null) { + continue; + } + if (isProlog(program, function.getEntryPoint(), true, monitor)) { + setPrologEpilog(function, true); + } + else if (isEpilog(program, function.getEntryPoint(), true, monitor)) { + setPrologEpilog(function, false); + } + } + + return true; + } + + private boolean isProlog(Program program, Address entryPoint, boolean recurseOk, + TaskMonitor monitor) throws CancelledException { + DumbMemBufferImpl mem = new DumbMemBufferImpl(program.getMemory(), entryPoint); + int memdCnt = 0; + boolean returnPending = false; + byte[] bytes = new byte[4]; + for (int i = 0; i < 5; i++) { + if (mem.getBytes(bytes, i * 4) != 4) { + return false; + } + if (NOP.isMatch(bytes)) { + // ignore + } + else if (JUMPR_LR.isMatch(bytes)) { + returnPending = true; + } + else if (JUMP.isMatch(bytes)) { + if (!recurseOk || + !hasContinuationFunction(program, entryPoint.add(i * 4), true, monitor)) { + return false; + } + returnPending = true; + } + else if (MEMD_PUSH.isMatch(bytes)) { + ++memdCnt; + } + else { + return false; // unexpected instruction for prolog + } + if (returnPending && ((bytes[1] & 0x0c0) == 0x0c0)) { + break; // return pending and at end of parallel group + } + } + return (memdCnt != 0); + } + + private boolean isEpilog(Program program, Address entryPoint, boolean recurseOk, + TaskMonitor monitor) throws CancelledException { + DumbMemBufferImpl mem = new DumbMemBufferImpl(program.getMemory(), entryPoint); + int memdCnt = 0; + boolean returnPending = false; + byte[] bytes = new byte[4]; + for (int i = 0; i < 5; i++) { + if (mem.getBytes(bytes, i * 4) != 4) { + return false; + } + if (NOP.isMatch(bytes)) { + // ignore + } + else if (JUMPR_LR.isMatch(bytes) || DEALLOC_RETURN.isMatch(bytes)) { + returnPending = true; + } + else if (JUMP.isMatch(bytes)) { + if (!recurseOk || + !hasContinuationFunction(program, entryPoint.add(i * 4), false, monitor)) { + return false; + } + returnPending = true; + } + else if (MEMD_POP.isMatch(bytes)) { + ++memdCnt; + } + else if (DEALLOCFRAME.isMatch(bytes)) { + // ignore + } + else { + return false; // unexpected instruction for prolog + } + if (returnPending && ((bytes[1] & 0x0c0) == 0x0c0)) { + break; // return pending and at end of parallel group + } + } + return (memdCnt != 0); + } + + private boolean hasContinuationFunction(Program program, Address jumpFromAddr, + boolean checkProlog, TaskMonitor monitor) throws CancelledException { + Listing listing = program.getListing(); + Instruction instr = listing.getInstructionAt(jumpFromAddr); + if (instr == null) { + // unable to continue without instruction at jumpFromAddr + return false; + } + Address destAddr = instr.getAddress(0); + if (destAddr == null) { + return false; + } + if (checkProlog) { + return (isProlog(program, destAddr, false, monitor) && setPrologEpilog(program, + destAddr, true, monitor)); + } + return (isEpilog(program, destAddr, false, monitor) && setPrologEpilog(program, destAddr, + false, monitor)); + } + + @Override + public void registerOptions(Options options, Program program) { + options.registerOption(OPTION_NAME_FIXUP_FUNCTIONS, FIXUP_TYPES.Name_Only, null, + OPTION_DESCRIPTION_FIXUP_FUNCTIONS); + } + + @Override + public void optionsChanged(Options options, Program program) { + fixupType = options.getEnum(OPTION_NAME_FIXUP_FUNCTIONS, FIXUP_TYPES.Name_Only); + } + + private static class InstructionMaskValue { + + private MaskImpl mask; + private byte[] valueBytes; + + InstructionMaskValue(int maskValue, int value) { + mask = new MaskImpl(getBytes(maskValue)); + valueBytes = getBytes(value); + } + + public boolean isMatch(byte[] bytes) { + try { + return mask.equalMaskedValue(bytes, valueBytes); + } + catch (IncompatibleMaskException e) { + throw new AssertException(e); + } + } + } + + private static byte[] getBytes(int value) { + byte[] bytes = new byte[4]; + // TODO: Order may need to change !! + bytes[0] = (byte) value; + bytes[1] = (byte) (value >> 8); + bytes[2] = (byte) (value >> 16); + bytes[3] = (byte) (value >> 24); + return bytes; + } + +} diff --git a/Ghidra/Processors/Hexagon/src/main/java/ghidra/app/plugin/core/analysis/HexagonThunkAnalyzer.java b/Ghidra/Processors/Hexagon/src/main/java/ghidra/app/plugin/core/analysis/HexagonThunkAnalyzer.java new file mode 100755 index 0000000000..cf1abe5b75 --- /dev/null +++ b/Ghidra/Processors/Hexagon/src/main/java/ghidra/app/plugin/core/analysis/HexagonThunkAnalyzer.java @@ -0,0 +1,292 @@ +/* ### + * IP: GHIDRA + * NOTE: Need to review if these patterns are any indicators of code/original binary, even the address examples + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +package ghidra.app.plugin.core.analysis; + +import java.io.IOException; +import java.io.InputStream; +import java.util.ArrayList; +import java.util.List; + +import ghidra.app.cmd.function.CreateFunctionCmd; +import ghidra.app.services.*; +import ghidra.app.util.importer.MessageLog; +import ghidra.program.model.address.*; +import ghidra.program.model.listing.*; +import ghidra.program.model.mem.MemoryBlock; +import ghidra.program.model.symbol.*; +import ghidra.program.util.SymbolicPropogator; +import ghidra.util.bytesearch.*; +import ghidra.util.exception.CancelledException; +import ghidra.util.task.TaskMonitor; + +public class HexagonThunkAnalyzer extends AbstractAnalyzer { + private static final String NAME = "Hexagon Thunks"; + private static final String DESCRIPTION = + "Detects common Thunk pattern used within Hexagon code"; + + /** + * THUNK_PATTERN1 + * 
+	 *	1d 7f fd bf                      add                           SP,SP,#-0x8 
+	 *	fe fc 9d a7                   || memw                          (SP+#-0x8),R28
+	 *	aa ca bc 72                      assign                        R28.H,#0x8aaa
+	 *	aa cb bc 71                      assign                        R28.L,#0x8baa
+	 *	1d 41 1d b0                      add                           SP,SP,#0x8
+	 *	00 40 9c 52                   || jumpr                         R28
+	 *	1c c0 9d 91                   || memw                          R28,(SP)
+	 *
+ */ + private static final String THUNK_PATTERN1 = + "0x1d7ffdbf 0xfefc9da7 " + "..................11110001110010 " // first assign .H + + "..................11110001110001 " // second assign .L + + "0x1d411db0 0x00409c52 0x1cc09d91"; + + private final static String PROCESSOR_NAME = "Hexagon"; + + private BulkPatternSearcher sequenceSearchState; + + public HexagonThunkAnalyzer() { + super(NAME, DESCRIPTION, AnalyzerType.INSTRUCTION_ANALYZER); + setDefaultEnablement(true); + setPriority(AnalysisPriority.CODE_ANALYSIS.before()); + } + + @Override + public boolean canAnalyze(Program program) { + if (!PROCESSOR_NAME.equals(program.getLanguage().getProcessor().toString())) { + return false; + } + return true; + } + + private BulkPatternSearcher getSequenceSearchState() { + if (sequenceSearchState == null) { + List thunkPatterns = new ArrayList(); + thunkPatterns.add(new Pattern(new DittedBitSequence(THUNK_PATTERN1), 0, + new PostRule[0], new MatchAction[0])); + sequenceSearchState = new BulkPatternSearcher(thunkPatterns); + } + return sequenceSearchState; + } + + @Override + public boolean added(Program program, AddressSetView set, TaskMonitor monitor, MessageLog log) + throws CancelledException { + + monitor.setMessage("Search for Thunks..."); + + BulkPatternSearcher searchState = getSequenceSearchState(); + + long numAddrs = 0; + monitor.initialize(set.getNumAddresses()); + + MemoryBlock[] blocks = program.getMemory().getBlocks(); + for (int i = 0; i < blocks.length; ++i) { + monitor.setProgress(numAddrs); + MemoryBlock block = blocks[i]; + + numAddrs += block.getSize(); + + try { + if (set.intersects(block.getStart(), block.getEnd())) { + searchBlock(searchState, program, block, set, monitor, log); + } + } + catch (IOException e) { + log.appendMsg("Unable to scan block " + block.getName() + " for function starts"); + } + } + + return true; + } + + private void searchBlock(BulkPatternSearcher searchState, Program program, + MemoryBlock block, + AddressSetView restrictSet, TaskMonitor monitor, MessageLog log) throws IOException, + CancelledException { + + // if no restricted set, make restrict set the full block + AddressSet doneSet = new AddressSet(restrictSet); + if (doneSet.isEmpty()) { + doneSet.addRange(block.getStart(), block.getEnd()); + } + doneSet = doneSet.intersectRange(block.getStart(), block.getEnd()); + + long currentProgress = monitor.getProgress(); + + // pull each range off the restricted set + AddressRangeIterator addressRanges = doneSet.getAddressRanges(); + while (addressRanges.hasNext()) { + monitor.checkCancelled(); + AddressRange addressRange = addressRanges.next(); + + monitor.setProgress(currentProgress); + + currentProgress += addressRange.getLength(); + + ArrayList> mymatches = new ArrayList<>(); + + Address blockStartAddr = block.getStart(); + + long blockOffset = addressRange.getMinAddress().subtract(blockStartAddr); + + if (blockOffset <= 0) { + // don't go before the block start + blockOffset = 0; + } + + // compute number of bytes in the range + 1, and don't search more than that. + long maxBlockSearchLength = + addressRange.getMaxAddress().subtract(blockStartAddr) - blockOffset + 1; + + InputStream data = block.getData(); + data.skip(blockOffset); + + searchState.search(data, maxBlockSearchLength, mymatches, monitor); + monitor.checkCancelled(); + + // TODO: DANGER there is much offset<-->address calculation here + // should be OK, since they are all relative to the block. + for (int i = 0; i < mymatches.size(); ++i) { + monitor.checkCancelled(); + Match match = mymatches.get(i); + Pattern pattern = match.getPattern(); + long offset = blockOffset + match.getStart() + pattern.getMarkOffset(); + Address addr = blockStartAddr.add(offset); + createThunk(program, addr, monitor, log); + } + } + } + + private Address getThunkDestination(Function thunk, AddressSetView body) { + + Listing listing = thunk.getProgram().getListing(); + Instruction lastInstr = listing.getInstructionContaining(body.getMaxAddress()); + if (lastInstr == null) { + return null; + } + FlowType flowType = lastInstr.getFlowType(); + if (!flowType.isCall() && !flowType.isJump()) { + return null; + } + Reference flowRef = null; + for (Reference ref : lastInstr.getReferencesFrom()) { + RefType refType = ref.getReferenceType(); + if (!refType.isFlow()) { + continue; + } + if (flowRef != null) { + return null; + } + if (!refType.isCall() && !refType.isJump()) { + return null; + } + flowRef = ref; + } + return flowRef != null ? flowRef.getToAddress() : null; + } + + private void createThunk(Program program, Address addr, TaskMonitor monitor, MessageLog log) + throws CancelledException { + + // check existing function first + Function func = program.getFunctionManager().getFunctionAt(addr); + + if (func != null && func.isThunk()) { + return; + } + + // no instruction, ignore it + Instruction instruction = program.getListing().getInstructionAt(addr); + if (instruction == null) { + return; + } + + // don't know a body, make a dummy + AddressSet body; + body = new AddressSet(addr, addr.add(27)); + + // first get function to destination + // use the symbolic propagator to lay down the reference (restricted to this body). + SymbolicPropogator symEval = new SymbolicPropogator(program); + + symEval.flowConstants(addr, body, null, true, monitor); + + // if the found snippet is fallen into, at least get the to ref, so if + // this is found to be a thunk later, the reference is already there. + + // instruction falling into it, not a thunk + // instruction must not be a jump to this location either. + Address fallFrom = instruction.getFallFrom(); + if (fallFrom != null) { + Instruction fromInstr = program.getListing().getInstructionAt(fallFrom); + if (fromInstr != null) { + FlowType flowType = fromInstr.getFlowType(); + if (!flowType.isJump() || flowType.isConditional()) { + return; + } + Reference[] referencesFrom = fromInstr.getReferencesFrom(); + for (int i = 0; i < referencesFrom.length; i++) { + if (!referencesFrom.equals(addr)) { + return; + } + } + } + } + + // Then create the body. + + if (func == null) { + // must create it + CreateFunctionCmd createFunctionCmd = + new CreateFunctionCmd(null, addr, body, SourceType.ANALYSIS); + createFunctionCmd.applyTo(program); + func = program.getFunctionManager().getFunctionAt(addr); + } + if (func == null) { + return; + } + + Address thunkDest = getThunkDestination(func, body); + if (thunkDest == null) { + return; + } + + Listing listing = func.getProgram().getListing(); + + FunctionManager funcMgr = func.getProgram().getFunctionManager(); + Function thunkedFunc = funcMgr.getFunctionAt(thunkDest); + if (thunkedFunc == null) { + + Instruction instr = listing.getInstructionAt(thunkDest); + if (instr == null) { + return; + } + + CreateFunctionCmd cmd = new CreateFunctionCmd(thunkDest); + cmd.applyTo(func.getProgram()); + + thunkedFunc = funcMgr.getFunctionAt(thunkDest); + if (thunkedFunc == null) { + return; + } + } + + func.setThunkedFunction(thunkedFunc); + + } +} diff --git a/Ghidra/Processors/Hexagon/src/main/java/ghidra/app/plugin/core/analysis/HexagonUnsupportSemanticAnalyzer.java b/Ghidra/Processors/Hexagon/src/main/java/ghidra/app/plugin/core/analysis/HexagonUnsupportSemanticAnalyzer.java new file mode 100755 index 0000000000..d8ded140cf --- /dev/null +++ b/Ghidra/Processors/Hexagon/src/main/java/ghidra/app/plugin/core/analysis/HexagonUnsupportSemanticAnalyzer.java @@ -0,0 +1,190 @@ +/* ### + * IP: GHIDRA + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +package ghidra.app.plugin.core.analysis; + +import ghidra.app.services.*; +import ghidra.app.util.importer.MessageLog; +import ghidra.program.model.address.*; +import ghidra.program.model.lang.Register; +import ghidra.program.model.listing.*; +import ghidra.program.model.pcode.PcodeOp; +import ghidra.program.model.pcode.Varnode; +import ghidra.util.exception.CancelledException; +import ghidra.util.task.TaskMonitor; + +import java.math.BigInteger; +import java.util.Arrays; +import java.util.HashSet; + +public class HexagonUnsupportSemanticAnalyzer extends AbstractAnalyzer { + private static final String NAME = "Hexagon Unsupported Semantic Check"; + private static final String DESCRIPTION = + "Detects and bookmarks instruction packets which read a predicate register before it is written"; + + private final static String PROCESSOR_NAME = "Hexagon"; + private final static String BOOKMARK_CATEGORY_NAME = "Unsupported Semantics"; + + private static final String[] predicateNames = new String[] { "P0", "P1", "P2", "P3" }; + + private Register packetOffsetRegister; + + private HashSet pNewRegisters = new HashSet(); + + public HexagonUnsupportSemanticAnalyzer() { + super(NAME, DESCRIPTION, AnalyzerType.INSTRUCTION_ANALYZER); + setDefaultEnablement(true); + setSupportsOneTimeAnalysis(); + setPriority(AnalysisPriority.CODE_ANALYSIS); + } + + @Override + public boolean canAnalyze(Program program) { + if (!PROCESSOR_NAME.equals(program.getLanguage().getProcessor().toString())) { + return false; + } + + packetOffsetRegister = program.getRegister("packetOffset"); + + for (int i = 0; i < predicateNames.length; i++) { + Register predReg = program.getRegister(predicateNames[i] + ".new"); + pNewRegisters.add(predReg); + } + + return true; + } + + private boolean isStartOfPacket(Instruction instruction) { + BigInteger value = instruction.getValue(packetOffsetRegister, false); + return value == null || (value.intValue() == 0); + } + + @Override + public boolean added(Program program, AddressSetView set, TaskMonitor monitor, MessageLog log) + throws CancelledException { + + for (AddressRange range : set) { + added(program, range.getMinAddress(), range.getMaxAddress(), monitor, log); + } + return true; + } + + private Address getStartOfPacket(Program program, Address instrAddr) { + Listing listing = program.getListing(); + // assume we will only get aligned address + Instruction instr = listing.getInstructionAt(instrAddr); + try { + while (instr != null && !isStartOfPacket(instr)) { + Address prevAddr = instrAddr.subtractNoWrap(4); + instr = listing.getInstructionAt(prevAddr); + if (instr != null) { + instrAddr = instr.getAddress(); + } + } + } + catch (AddressOverflowException e) { + // ignore + } + return instrAddr; + } + + private int getPredicateNumber(Register preg) { + return preg.getName().charAt(1) - 0x30; + } + + private void added(Program program, Address minAddr, Address maxAddr, TaskMonitor monitor, + MessageLog log) { + + Listing listing = program.getListing(); + + boolean[] predWasWritten = new boolean[predicateNames.length]; + Arrays.fill(predWasWritten, false); + + Address instrAddr = getStartOfPacket(program, minAddr); // find start of packet + Instruction instr = listing.getInstructionAt(instrAddr); + + // skip past empty regions + if (instr == null) { + instr = listing.getInstructionAfter(instrAddr); + if (instr == null) { + return; + } + } + instrAddr = instr.getAddress(); + + while (instr != null && (instrAddr.compareTo(maxAddr) <= 0 || !isStartOfPacket(instr))) { + + if (isStartOfPacket(instr)) { + Arrays.fill(predWasWritten, false); + } + + for (PcodeOp op : instr.getPcode()) { + for (Varnode in : op.getInputs()) { + if (in.isRegister() && in.getSize() == 1) { + Register reg = program.getRegister(in.getAddress(), 1); + if (pNewRegisters.contains(reg)) { + int index = getPredicateNumber(reg); + if (!predWasWritten[index]) { + markUnsupportPredicateRead(instr, reg); + } + } + } + } + Varnode out = op.getOutput(); + if (out != null && out.isRegister() && out.getSize() == 1) { + Register reg = program.getRegister(out.getAddress(), 1); + if (pNewRegisters.contains(reg)) { + // We ignore write to P3P0_ since this should only occur for packet initialization + int index = getPredicateNumber(reg); + predWasWritten[index] = true; + } + } + } + + try { + instrAddr = instrAddr.addNoWrap(4); + } + catch (AddressOverflowException e) { + break; + } + instr = listing.getInstructionAt(instrAddr); + + if (instr == null) { + // skip past empty regions + instr = listing.getInstructionAfter(instrAddr); + if (instr != null) { + instrAddr = instr.getAddress(); + Arrays.fill(predWasWritten, false); + } + } + + } + + } + + private void markUnsupportPredicateRead(Instruction instr, Register predReg) { + instr.getProgram().getBookmarkManager().setBookmark(instr.getAddress(), + BookmarkType.WARNING, BOOKMARK_CATEGORY_NAME, + "Predicate " + predReg.getName() + " read before written"); + } + + @Override + public boolean removed(Program program, AddressSetView set, TaskMonitor monitor, MessageLog log) + throws CancelledException { + program.getBookmarkManager().removeBookmarks(set, BookmarkType.WARNING, + BOOKMARK_CATEGORY_NAME, monitor); + return true; + } +} diff --git a/Ghidra/Processors/Hexagon/src/main/java/ghidra/app/util/bin/format/elf/Hexagon_ElfConstants.java b/Ghidra/Processors/Hexagon/src/main/java/ghidra/app/util/bin/format/elf/Hexagon_ElfConstants.java new file mode 100644 index 0000000000..a3232852c5 --- /dev/null +++ b/Ghidra/Processors/Hexagon/src/main/java/ghidra/app/util/bin/format/elf/Hexagon_ElfConstants.java @@ -0,0 +1,71 @@ +/* ### + * IP: GHIDRA + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +package ghidra.app.util.bin.format.elf; + +public class Hexagon_ElfConstants { + + // Hexagon-specific e_flags + + // Object processor version flags, bits[11:0] + public static final int EF_HEXAGON_MACH_V2 = 0x00000001; // Hexagon V2 + public static final int EF_HEXAGON_MACH_V3 = 0x00000002; // Hexagon V3 + public static final int EF_HEXAGON_MACH_V4 = 0x00000003; // Hexagon V4 + public static final int EF_HEXAGON_MACH_V5 = 0x00000004; // Hexagon V5 + public static final int EF_HEXAGON_MACH_V55 = 0x00000005; // Hexagon V55 + public static final int EF_HEXAGON_MACH_V60 = 0x00000060; // Hexagon V60 + public static final int EF_HEXAGON_MACH_V62 = 0x00000062; // Hexagon V62 + public static final int EF_HEXAGON_MACH_V65 = 0x00000065; // Hexagon V65 + public static final int EF_HEXAGON_MACH_V66 = 0x00000066; // Hexagon V66 + public static final int EF_HEXAGON_MACH_V67 = 0x00000067; // Hexagon V67 + public static final int EF_HEXAGON_MACH_V67T = 0x00008067; // Hexagon V67T + public static final int EF_HEXAGON_MACH_V68 = 0x00000068; // Hexagon V68 + public static final int EF_HEXAGON_MACH_V69 = 0x00000069; // Hexagon V69 + public static final int EF_HEXAGON_MACH_V71 = 0x00000071; // Hexagon V71 + public static final int EF_HEXAGON_MACH_V71T = 0x00008071; // Hexagon V71T + public static final int EF_HEXAGON_MACH_V73 = 0x00000073; // Hexagon V73 + public static final int EF_HEXAGON_MACH = 0x000003ff; // Hexagon V.. + + // Highest ISA version flags + public static final int EF_HEXAGON_ISA_MACH = 0x00000000; // Same as specified in bits[11:0] of e_flags + public static final int EF_HEXAGON_ISA_V2 = 0x00000010; // Hexagon V2 ISA + public static final int EF_HEXAGON_ISA_V3 = 0x00000020; // Hexagon V3 ISA + public static final int EF_HEXAGON_ISA_V4 = 0x00000030; // Hexagon V4 ISA + public static final int EF_HEXAGON_ISA_V5 = 0x00000040; // Hexagon V5 ISA + public static final int EF_HEXAGON_ISA_V55 = 0x00000050; // Hexagon V55 ISA + public static final int EF_HEXAGON_ISA_V60 = 0x00000060; // Hexagon V60 ISA + public static final int EF_HEXAGON_ISA_V62 = 0x00000062; // Hexagon V62 ISA + public static final int EF_HEXAGON_ISA_V65 = 0x00000065; // Hexagon V65 ISA + public static final int EF_HEXAGON_ISA_V66 = 0x00000066; // Hexagon V66 ISA + public static final int EF_HEXAGON_ISA_V67 = 0x00000067; // Hexagon V67 ISA + public static final int EF_HEXAGON_ISA_V68 = 0x00000068; // Hexagon V68 ISA + public static final int EF_HEXAGON_ISA_V69 = 0x00000069; // Hexagon V69 ISA + public static final int EF_HEXAGON_ISA_V71 = 0x00000071; // Hexagon V71 ISA + public static final int EF_HEXAGON_ISA_V73 = 0x00000073; // Hexagon V73 ISA + public static final int EF_HEXAGON_ISA_V75 = 0x00000075; // Hexagon V75 ISA + public static final int EF_HEXAGON_ISA = 0x000003ff; // Hexagon V.. ISA + + // Hexagon-specific section indexes for common small data + public static final int SHN_HEXAGON_SCOMMON = 0xff00; // Other access sizes + public static final int SHN_HEXAGON_SCOMMON_1 = 0xff01; // Byte-sized access + public static final int SHN_HEXAGON_SCOMMON_2 = 0xff02; // Half-word-sized access + public static final int SHN_HEXAGON_SCOMMON_4 = 0xff03; // Word-sized access + public static final int SHN_HEXAGON_SCOMMON_8 = 0xff04; // Double-word-size access + + private Hexagon_ElfConstants() { + // no construct + } + +} diff --git a/Ghidra/Processors/Hexagon/src/main/java/ghidra/app/util/bin/format/elf/extend/Hexagon_ElfExtension.java b/Ghidra/Processors/Hexagon/src/main/java/ghidra/app/util/bin/format/elf/extend/Hexagon_ElfExtension.java new file mode 100644 index 0000000000..028a592094 --- /dev/null +++ b/Ghidra/Processors/Hexagon/src/main/java/ghidra/app/util/bin/format/elf/extend/Hexagon_ElfExtension.java @@ -0,0 +1,74 @@ +/* ### + * IP: GHIDRA + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +package ghidra.app.util.bin.format.elf.extend; + +import ghidra.app.util.bin.format.elf.*; +import ghidra.app.util.bin.format.elf.ElfDynamicType.ElfDynamicValueType; +import ghidra.program.model.lang.Language; + +public class Hexagon_ElfExtension extends ElfExtension { + + // Elf Program Header Extensions + public static final ElfProgramHeaderType PT_ARM_EXIDX = + new ElfProgramHeaderType(0x70000000, "PT_ARM_EXIDX", "Frame unwind information"); + + // Elf Section Header Extensions + public static final ElfSectionHeaderType SHT_ARM_EXIDX = + new ElfSectionHeaderType(0x70000001, "SHT_ARM_EXIDX", "Exception Index table"); + public static final ElfSectionHeaderType SHT_ARM_PREEMPTMAP = new ElfSectionHeaderType( + 0x70000002, "SHT_ARM_PREEMPTMAP", "BPABI DLL dynamic linking preemption map"); + public static final ElfSectionHeaderType SHT_ARM_ATTRIBUTES = new ElfSectionHeaderType( + 0x70000003, "SHT_ARM_ATTRIBUTES", "Object file compatibility attributes"); + public static final ElfSectionHeaderType SHT_ARM_DEBUGOVERLAY = + new ElfSectionHeaderType(0x70000004, "SHT_ARM_DEBUGOVERLAY", "See DBGOVL for details"); + public static final ElfSectionHeaderType SHT_ARM_OVERLAYSECTION = + new ElfSectionHeaderType(0x70000005, "SHT_ARM_OVERLAYSECTION", + "See Debugging Overlaid Programs (DBGOVL) for details"); + + // Elf Dynamic Type Extensions + + // DT_HEXAGON_SYMSZ: This value is equivalent to the value of DT_SYMENT multiplied by the value + // field "nchain" in the hash table pointed to by DT_HASH. + public static final ElfDynamicType DT_HEXAGON_SYMSZ = + new ElfDynamicType(0x70000000, "DT_HEXAGON_SYMSZ", + "Size in bytes of the DT_SYMTAB symbol table ", ElfDynamicValueType.VALUE); + + // DT_HEXAGON_VER: Currently can be a value of 2 or 3. Hexagon ABI requires a value of 3 + // although the default is 2. + public static final ElfDynamicType DT_HEXAGON_VER = new ElfDynamicType(0x70000001, + "DT_HEXAGON_VER", "Version of interface with dynamic linker", ElfDynamicValueType.VALUE); + + public static final ElfDynamicType DT_HEXAGON_PLT = new ElfDynamicType(0x70000002, + "DT_HEXAGON_PLT", "Image offset of the PLT", ElfDynamicValueType.VALUE); + + @Override + public boolean canHandle(ElfHeader elf) { + return elf.e_machine() == ElfConstants.EM_HEXAGON; + } + + @Override + public boolean canHandle(ElfLoadHelper elfLoadHelper) { + Language language = elfLoadHelper.getProgram().getLanguage(); + return canHandle(elfLoadHelper.getElfHeader()) && + "Hexagon".equals(language.getProcessor().toString()); + } + + @Override + public String getDataTypeSuffix() { + return "_Hexagon"; + } + +} diff --git a/Ghidra/Processors/Hexagon/src/main/java/ghidra/app/util/bin/format/elf/extend/Hexagon_ElfProgramHeaderConstants.java b/Ghidra/Processors/Hexagon/src/main/java/ghidra/app/util/bin/format/elf/extend/Hexagon_ElfProgramHeaderConstants.java new file mode 100644 index 0000000000..fd9c28f4ea --- /dev/null +++ b/Ghidra/Processors/Hexagon/src/main/java/ghidra/app/util/bin/format/elf/extend/Hexagon_ElfProgramHeaderConstants.java @@ -0,0 +1,34 @@ +/* ### + * IP: GHIDRA + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +package ghidra.app.util.bin.format.elf.extend; + +public class Hexagon_ElfProgramHeaderConstants { + + public static final int EF_HEXAGON_MACH_V4 = 0x3; // Hexagon V4 + public static final int EF_HEXAGON_MACH_V5 = 0x4; // Hexagon V5 + public static final int EF_HEXAGON_MACH_V55 = 0x5; // Hexagon V55 + public static final int EF_HEXAGON_MACH_V60 = 0x60; // Hexagon V60 + public static final int EF_HEXAGON_MACH_V61 = 0x61; // Hexagon V61 + public static final int EF_HEXAGON_MACH_V62 = 0x62; // Hexagon V62 + public static final int EF_HEXAGON_MACH_V65 = 0x65; // Hexagon V65 + public static final int EF_HEXAGON_MACH_V66 = 0x66; // Hexagon V66 + public static final int EF_HEXAGON_MACH_V67 = 0x67; // Hexagon V67 + public static final int EF_HEXAGON_MACH_V67T = 0x8067; // Hexagon V67 Small Core (V67t) + public static final int EF_HEXAGON_MACH_V68 = 0x68; // Hexagon V68 + public static final int EF_HEXAGON_MACH_V69 = 0x69; // Hexagon V69 + public static final int EF_HEXAGON_MACH_V71 = 0x71; // Hexagon V71 + +} diff --git a/Ghidra/Processors/Hexagon/src/main/java/ghidra/app/util/bin/format/elf/relocation/Hexagon_ElfRelocationHandler.java b/Ghidra/Processors/Hexagon/src/main/java/ghidra/app/util/bin/format/elf/relocation/Hexagon_ElfRelocationHandler.java new file mode 100644 index 0000000000..0b8cc1e736 --- /dev/null +++ b/Ghidra/Processors/Hexagon/src/main/java/ghidra/app/util/bin/format/elf/relocation/Hexagon_ElfRelocationHandler.java @@ -0,0 +1,219 @@ +/* ### + * IP: GHIDRA + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +package ghidra.app.util.bin.format.elf.relocation; + +import ghidra.app.util.bin.format.elf.*; +import ghidra.app.util.importer.MessageLog; +import ghidra.program.model.address.Address; +import ghidra.program.model.listing.Program; +import ghidra.program.model.mem.Memory; +import ghidra.program.model.mem.MemoryAccessException; +import ghidra.program.model.reloc.Relocation.Status; +import ghidra.program.model.reloc.RelocationResult; + +public class Hexagon_ElfRelocationHandler + extends AbstractElfRelocationHandler> { + + /** + * Constructor + */ + public Hexagon_ElfRelocationHandler() { + super(Hexagon_ElfRelocationType.class); + } + + @Override + public boolean canRelocate(ElfHeader elf) { + return elf.e_machine() == ElfConstants.EM_HEXAGON; + } + + @Override + public int getRelrRelocationType() { + return Hexagon_ElfRelocationType.R_HEXAGON_RELATIVE.typeId; + } + + @Override + protected RelocationResult relocate(ElfRelocationContext elfRelocationContext, + ElfRelocation relocation, Hexagon_ElfRelocationType type, Address relocationAddress, + ElfSymbol elfSymbol, Address symbolAddr, long symbolValue, String symbolName) + throws MemoryAccessException { + + Program program = elfRelocationContext.getProgram(); + Memory memory = program.getMemory(); + MessageLog log = elfRelocationContext.getLog(); + + long addend = relocation.getAddend(); + long offset = (int) relocationAddress.getOffset(); + + int symbolIndex = relocation.getSymbolIndex(); + + int byteLength = 4; // applied relocation length + + // Handle relative relocations that do not require symbolAddr or symbolValue + switch (type) { + + case R_HEXAGON_RELATIVE: + long imageBaseAdjustment = elfRelocationContext.getImageBaseWordAdjustmentOffset(); + int value = (int) (addend + imageBaseAdjustment); + memory.setInt(relocationAddress, value); + return new RelocationResult(Status.APPLIED, byteLength); + + case R_HEXAGON_COPY: + markAsUnsupportedCopy(program, relocationAddress, type, symbolName, symbolIndex, + elfSymbol.getSize(), elfRelocationContext.getLog()); + return RelocationResult.UNSUPPORTED; + + default: + break; + } + + // Check for unresolved symbolAddr and symbolValue required by remaining relocation types handled below + if (handleUnresolvedSymbol(elfRelocationContext, relocation, relocationAddress)) { + return RelocationResult.FAILURE; + } + + int value = (int) (symbolValue + addend); + int memValue = memory.getInt(relocationAddress); + + switch (type) { + case R_HEXAGON_B22_PCREL: + int dist = + (int) (Integer.toUnsignedLong(value) - Integer.toUnsignedLong((int) offset)); + if ((dist < -0x00800000) || (dist >= 0x00800000)) { + return RelocationResult.FAILURE; + } + memValue &= ~0x01ff3fff; + memValue |= 0x00003fff & dist; + memValue |= 0x01ff0000 & (dist << 2); + memory.setInt(relocationAddress, memValue); + break; + +// break; +// case R_HEXAGON_B15_PCREL: +// break; +// case R_HEXAGON_B7_PCREL: +// break; + + case R_HEXAGON_HI16: + value = (value >> 16) & 0xffff; + /* fallthrough */ + case R_HEXAGON_LO16: + memValue &= ~0x00c03fff; + memValue |= value & 0x3fff; + memValue |= (value & 0xc000) << 8; + memory.setInt(relocationAddress, memValue); + break; + + case R_HEXAGON_32: + memory.setInt(relocationAddress, value); + if (symbolIndex != 0 && addend != 0 && !elfSymbol.isSection()) { + warnExternalOffsetRelocation(program, relocationAddress, symbolAddr, symbolName, + addend, elfRelocationContext.getLog()); + applyComponentOffsetPointer(program, relocationAddress, addend); + } + break; + + case R_HEXAGON_16: + memory.setShort(relocationAddress, (short) value); + byteLength = 2; + break; + + case R_HEXAGON_8: + memory.setByte(relocationAddress, (byte) value); + byteLength = 1; + break; + +// case R_HEXAGON_GPREL16_0: +// break; +// case R_HEXAGON_GPREL16_1: +// break; +// case R_HEXAGON_GPREL16_2: +// break; +// case R_HEXAGON_GPREL16_3: +// break; +// case R_HEXAGON_HL16: +// break; +// case R_HEXAGON_B13_PCREL: +// break; +// case R_HEXAGON_B9_PCREL: +// break; +// case R_HEXAGON_B32_PCREL_X: +// break; +// case R_HEXAGON_32_6_X: +// break; +// case R_HEXAGON_B22_PCREL_X: +// break; +// case R_HEXAGON_B15_PCREL_X: +// break; +// case R_HEXAGON_B13_PCREL_X: +// break; +// case R_HEXAGON_B9_PCREL_X: +// break; +// case R_HEXAGON_B7_PCREL_X: +// break; +// case R_HEXAGON_16_X: +// break; +// case R_HEXAGON_12_X: +// break; +// case R_HEXAGON_11_X: +// break; +// case R_HEXAGON_10_X: +// break; +// case R_HEXAGON_9_X: +// break; +// case R_HEXAGON_8_X: +// break; +// case R_HEXAGON_7_X: +// break; +// case R_HEXAGON_6_X: +// break; + + case R_HEXAGON_32_PCREL: + dist = (int) (Integer.toUnsignedLong(value) - Integer.toUnsignedLong((int) offset)); + memory.setInt(relocationAddress, dist); + break; + + case R_HEXAGON_GLOB_DAT: + case R_HEXAGON_JMP_SLOT: { + memory.setInt(relocationAddress, value); + break; + } + +// case R_HEXAGON_PLT_B22_PCREL: +// break; +// case R_HEXAGON_GOTOFF_LO16: +// break; +// case R_HEXAGON_GOTOFF_HI16: +// break; +// case R_HEXAGON_GOTOFF_32: +// break; +// case R_HEXAGON_GOT_LO16: +// break; // TODO: See MIPS for similar HI/LO approach +// case R_HEXAGON_GOT_HI16: +// break; // TODO: See MIPS for similar HI/LO approach +// case R_HEXAGON_GOT_32: +// break; +// case R_HEXAGON_GOT_16: +// break; + + default: + markAsUnhandled(program, relocationAddress, type, symbolIndex, symbolName, log); + return RelocationResult.UNSUPPORTED; + } + + return new RelocationResult(Status.APPLIED, byteLength); + } + +} diff --git a/Ghidra/Processors/Hexagon/src/main/java/ghidra/app/util/bin/format/elf/relocation/Hexagon_ElfRelocationType.java b/Ghidra/Processors/Hexagon/src/main/java/ghidra/app/util/bin/format/elf/relocation/Hexagon_ElfRelocationType.java new file mode 100644 index 0000000000..1bc8e7cdbb --- /dev/null +++ b/Ghidra/Processors/Hexagon/src/main/java/ghidra/app/util/bin/format/elf/relocation/Hexagon_ElfRelocationType.java @@ -0,0 +1,151 @@ +/* ### + * IP: GHIDRA + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +package ghidra.app.util.bin.format.elf.relocation; + +public enum Hexagon_ElfRelocationType implements ElfRelocationType { + + /** + * NOTES: + * 1. The GP register is set to the starting address of the process's small data area, + * as referenced by the program symbol, "_SDA_BASE_". + * + * + */ + + /* V2 */ + R_HEXAGON_NONE(0), + R_HEXAGON_B22_PCREL(1), + R_HEXAGON_B15_PCREL(2), + R_HEXAGON_B7_PCREL(3), + R_HEXAGON_LO16(4), + R_HEXAGON_HI16(5), + R_HEXAGON_32(6), + R_HEXAGON_16(7), + R_HEXAGON_8(8), + R_HEXAGON_GPREL16_0(9), + R_HEXAGON_GPREL16_1(10), + R_HEXAGON_GPREL16_2(11), + R_HEXAGON_GPREL16_3(12), + R_HEXAGON_HL16(13), + + /* V3 */ + R_HEXAGON_B13_PCREL(14), + + /* V4 */ + R_HEXAGON_B9_PCREL(15), + + /* V4 (extenders) */ + R_HEXAGON_B32_PCREL_X(16), + R_HEXAGON_32_6_X(17), + + /* V4 (extended) */ + R_HEXAGON_B22_PCREL_X(18), + R_HEXAGON_B15_PCREL_X(19), + R_HEXAGON_B13_PCREL_X(20), + R_HEXAGON_B9_PCREL_X(21), + R_HEXAGON_B7_PCREL_X(22), + R_HEXAGON_16_X(23), + R_HEXAGON_12_X(24), + R_HEXAGON_11_X(25), + R_HEXAGON_10_X(26), + R_HEXAGON_9_X(27), + R_HEXAGON_8_X(28), + R_HEXAGON_7_X(29), + R_HEXAGON_6_X(30), + + /* V2 PIC */ + R_HEXAGON_32_PCREL(31), + R_HEXAGON_COPY(32), + R_HEXAGON_GLOB_DAT(33), + R_HEXAGON_JMP_SLOT(34), + R_HEXAGON_RELATIVE(35), + R_HEXAGON_PLT_B22_PCREL(36), + R_HEXAGON_GOTOFF_LO16(37), + R_HEXAGON_GOTOFF_HI16(38), + R_HEXAGON_GOTOFF_32(39), + R_HEXAGON_GOT_LO16(40), + R_HEXAGON_GOT_HI16(41), + R_HEXAGON_GOT_32(42), + R_HEXAGON_GOT_16(43), + + R_HEXAGON_DTPMOD_32(44), + R_HEXAGON_DTPREL_LO16(45), + R_HEXAGON_DTPREL_HI16(46), + R_HEXAGON_DTPREL_32(47), + R_HEXAGON_DTPREL_16(48), + R_HEXAGON_GD_PLT_B22_PCREL(49), + R_HEXAGON_GD_GOT_LO16(50), + R_HEXAGON_GD_GOT_HI16(51), + R_HEXAGON_GD_GOT_32(52), + R_HEXAGON_GD_GOT_16(53), + R_HEXAGON_IE_LO16(54), + R_HEXAGON_IE_HI16(55), + R_HEXAGON_IE_32(56), + R_HEXAGON_IE_GOT_LO16(57), + R_HEXAGON_IE_GOT_HI16(58), + R_HEXAGON_IE_GOT_32(59), + R_HEXAGON_IE_GOT_16(60), + R_HEXAGON_TPREL_LO16(61), + R_HEXAGON_TPREL_HI16(62), + R_HEXAGON_TPREL_32(63), + R_HEXAGON_TPREL_16(64), + R_HEXAGON_6_PCREL_X(65), + R_HEXAGON_GOTREL_32_6_X(66), + R_HEXAGON_GOTREL_16_X(67), + R_HEXAGON_GOTREL_11_X(68), + R_HEXAGON_GOT_32_6_X(69), + R_HEXAGON_GOT_16_X(70), + R_HEXAGON_GOT_11_X(71), + R_HEXAGON_DTPREL_32_6_X(72), + R_HEXAGON_DTPREL_16_X(73), + R_HEXAGON_DTPREL_11_X(74), + R_HEXAGON_GD_GOT_32_6_X(75), + R_HEXAGON_GD_GOT_16_X(76), + R_HEXAGON_GD_GOT_11_X(77), + R_HEXAGON_IE_32_6_X(78), + R_HEXAGON_IE_16_X(79), + R_HEXAGON_IE_GOT_32_6_X(80), + R_HEXAGON_IE_GOT_16_X(81), + R_HEXAGON_IE_GOT_11_X(82), + R_HEXAGON_TPREL_32_6_X(83), + R_HEXAGON_TPREL_16_X(84), + R_HEXAGON_TPREL_11_X(85), + R_HEXAGON_LD_PLT_B22_PCREL(86), + R_HEXAGON_LD_GOT_LO16(87), + R_HEXAGON_LD_GOT_HI16(88), + R_HEXAGON_LD_GOT_32(89), + R_HEXAGON_LD_GOT_16(90), + R_HEXAGON_LD_GOT_32_6_X(91), + R_HEXAGON_LD_GOT_16_X(92), + R_HEXAGON_LD_GOT_11_X(93), + R_HEXAGON_23_REG(94), + R_HEXAGON_GD_PLT_B22_PCREL_X(95), + R_HEXAGON_GD_PLT_B32_PCREL_X(96), + R_HEXAGON_LD_PLT_B22_PCREL_X(97), + R_HEXAGON_LD_PLT_B32_PCREL_X(98), + R_HEXAGON_27_REG(99); + + public final int typeId; + + private Hexagon_ElfRelocationType(int typeId) { + this.typeId = typeId; + } + + @Override + public int typeId() { + return typeId; + } +} diff --git a/Ghidra/Processors/Hexagon/src/main/java/ghidra/app/util/viewer/field/HexagonParallelInstructionHelper.java b/Ghidra/Processors/Hexagon/src/main/java/ghidra/app/util/viewer/field/HexagonParallelInstructionHelper.java new file mode 100755 index 0000000000..1e79fd8078 --- /dev/null +++ b/Ghidra/Processors/Hexagon/src/main/java/ghidra/app/util/viewer/field/HexagonParallelInstructionHelper.java @@ -0,0 +1,63 @@ +/* ### + * IP: GHIDRA + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +package ghidra.app.util.viewer.field; + +import ghidra.program.model.lang.ParallelInstructionLanguageHelper; +import ghidra.program.model.lang.Register; +import ghidra.program.model.listing.Instruction; + +import java.math.BigInteger; + +public class HexagonParallelInstructionHelper implements ParallelInstructionLanguageHelper { + + public HexagonParallelInstructionHelper() { + } + + @Override + public String getMnemonicPrefix(Instruction instr) { + if (isParallelInstruction(instr)) { + return "||"; + } + return null; + } + + @Override + public boolean isParallelInstruction(Instruction instruction) { + + Register packetOffsetReg = instruction.getRegister("packetOffset"); + if (packetOffsetReg == null) { + return false; + } + BigInteger value = instruction.getValue(packetOffsetReg, false); + return value.intValue() != 0; + } + + @Override + public boolean isEndOfParallelInstructionGroup(Instruction instruction) { + try { + byte[] bytes = instruction.getBytes(); + // assume little endian' + // End of packet instruction will have PP='11' or EE='00' + int bits = (bytes[1] & 0xC0) >> 6; + return (bits == 0 || bits == 3); + } + catch (Exception e) { + // ignore + } + return true; + } + +} diff --git a/Ghidra/Processors/Hexagon/src/main/java/ghidra/program/emulation/HexagonEmulateInstructionStateModifier.java b/Ghidra/Processors/Hexagon/src/main/java/ghidra/program/emulation/HexagonEmulateInstructionStateModifier.java new file mode 100755 index 0000000000..3c46d312e0 --- /dev/null +++ b/Ghidra/Processors/Hexagon/src/main/java/ghidra/program/emulation/HexagonEmulateInstructionStateModifier.java @@ -0,0 +1,697 @@ +/* ### + * IP: GHIDRA + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +package ghidra.program.emulation; + +import java.math.BigInteger; +import java.util.function.Function; + +import ghidra.pcode.emulate.Emulate; +import ghidra.pcode.emulate.EmulateInstructionStateModifier; +import ghidra.pcode.emulate.callother.OpBehaviorOther; +import ghidra.pcode.error.LowlevelError; +import ghidra.pcode.floatformat.*; +import ghidra.pcode.memstate.MemoryState; +import ghidra.pcode.utils.Utils; +import ghidra.program.model.pcode.Varnode; + +@Deprecated(forRemoval = true, since = "12.1") +public class HexagonEmulateInstructionStateModifier extends EmulateInstructionStateModifier { + + private static final FloatFormat fp64Format = FloatFormatFactory.getFloatFormat(8); + + private static final int FP64_BIAS = 1023; + private static final int FP64_MANTISSA_BITS = 52; + private static final int FP64_INFINITY_EXP = 0x7ff; + + public HexagonEmulateInstructionStateModifier(Emulate emu) { + super(emu); + registerPcodeOpBehavior("min", new SignedMinimumOpBehavior()); + registerPcodeOpBehavior("vlslh", new VectorLogicalShiftLeftOpBehavior("vlslh", 16, 7)); + registerPcodeOpBehavior("vlsrh", new VectorLogicalShiftRightOpBehavior("vlsrh", 16, 7)); + registerPcodeOpBehavior("vlslw", new VectorLogicalShiftLeftOpBehavior("vlslw", 32, 7)); + registerPcodeOpBehavior("vlsrw", new VectorLogicalShiftRightOpBehavior("vlsrw", 32, 7)); + registerPcodeOpBehavior("vmux", new VectorMultiplexOpBehavior()); + registerPcodeOpBehavior("vabsh", new VectorAbsoluteValueOpBehavior("vabsh", 16)); + registerPcodeOpBehavior("vabsw", new VectorAbsoluteValueOpBehavior("vabsw", 32)); + + registerPcodeOpBehavior("dfmpyfix", new DFMultiplyFixOpBehavior()); + registerPcodeOpBehavior("dfmpyhh", new DFMultiplyHHOpBehavior()); + registerPcodeOpBehavior("dfmpylh", new DFMultiplyLHOpBehavior()); + registerPcodeOpBehavior("dfmpyll", new DFMultiplyLLOpBehavior()); + + registerPcodeOpBehavior("isClassifiedFloat", new ClassifyFloatOpBehavior()); + } + + private static final long FP_ZERO_CLASS_MASK = 0x01; + private static final long FP_NORMAL_CLASS_MASK = 0x02; + private static final long FP_SUBNORMAL_CLASS_MASK = 0x04; + private static final long FP_INFINITE_CLASS_MASK = 0x08; + private static final long FP_NAN_CLASS_MASK = 0x10; + + private class ClassifyFloatOpBehavior implements OpBehaviorOther { + + @Override + public void evaluate(Emulate e, Varnode out, Varnode[] inputs) { + + if (out == null) { + throw new LowlevelError( + "isClassifiedFloat: missing required output (predicate-storage)"); + } + + if (inputs.length != 2) { + throw new LowlevelError( + "isClassifiedFloat: requires two inputs (float-storage, constant-float-class-mask)"); + } + + MemoryState memoryState = e.getMemoryState(); + + Varnode in1 = inputs[0]; // float value + if (in1.isConstant()) { + throw new LowlevelError("isClassifiedFloat: first input must not be constant"); + } + if (in1.getSize() != 4 && in1.getSize() != 8) { + throw new LowlevelError( + "isClassifiedFloat: invalid float size of " + in1.getSize()); + } + + Varnode in2 = inputs[1]; // constant float-classification + if (!in2.isConstant()) { + throw new LowlevelError("isClassifiedFloat: second input must be constant"); + } + + FloatFormat floatFormat = FloatFormatFactory.getFloatFormat(in1.getSize()); + BigFloat bigFloat = floatFormat.decodeBigFloat(memoryState.getValue(in1)); + + int floatClass = (int) in2.getOffset(); + + boolean result = false; + if ((floatClass & FP_ZERO_CLASS_MASK) != 0 && bigFloat.isZero()) { + result = true; + } + if ((floatClass & FP_NORMAL_CLASS_MASK) != 0 && bigFloat.isNormal()) { + result = true; + } + if ((floatClass & FP_SUBNORMAL_CLASS_MASK) != 0 && bigFloat.isDenormal()) { + result = true; + } + if ((floatClass & FP_INFINITE_CLASS_MASK) != 0 && bigFloat.isInfinite()) { + result = true; + } + if ((floatClass & FP_NAN_CLASS_MASK) != 0 && bigFloat.isNaN()) { + result = true; + } + + memoryState.setValue(out, result ? 0xff : 0); + } + } + + /** + * out = min(in1,in2) where in1/in2 may be constant + */ + private class SignedMinimumOpBehavior implements OpBehaviorOther { + + @Override + public void evaluate(Emulate e, Varnode out, Varnode[] inputs) { + + if (out == null) { + throw new LowlevelError("min: missing required output"); + } + + if (inputs.length != 2) { + throw new LowlevelError("min: requires two inputs"); + } + + MemoryState memoryState = e.getMemoryState(); + + Varnode in1 = inputs[0]; + Varnode in2 = inputs[1]; + + long value1 = in1.isConstant() ? in1.getOffset() : memoryState.getValue(in1); + value1 = Utils.sign_extend(value1, in1.getSize(), 8); + + long value2 = in2.isConstant() ? in2.getOffset() : memoryState.getValue(in2); + value2 = Utils.sign_extend(value2, in2.getSize(), 8); + + // TODO: Unsure if min operation is signed or unsigned + + memoryState.setValue(out, Math.min(value1, value2)); + } + + } + + /** + * Rdd = vmux(Pn,Rss,Rtt) + */ + private class VectorMultiplexOpBehavior implements OpBehaviorOther { + + @Override + public void evaluate(Emulate e, Varnode out, Varnode[] inputs) { + + if (out == null) { + throw new LowlevelError("vmux: missing required double-word output (Rdd)"); + } + + if (inputs.length != 3) { + throw new LowlevelError("vmux: requires three inputs"); + } + + MemoryState memoryState = e.getMemoryState(); + + Varnode in1 = inputs[0]; + Varnode in2 = inputs[1]; + Varnode in3 = inputs[2]; + + if (out.getSize() != 8 || in2.getSize() != 8 || in3.getSize() != 8) { + throw new LowlevelError( + "vmux: multiplexed input and output sizes must be double-word"); + } + + long predicate = in1.isConstant() ? in1.getOffset() : memoryState.getValue(in1); + long value2 = in2.isConstant() ? in2.getOffset() : memoryState.getValue(in2); + long value3 = in3.isConstant() ? in3.getOffset() : memoryState.getValue(in3); + + long result = 0; + for (int i = 0; i < 8; i++) { + long byteValue = ((predicate & 1) != 0 ? value2 : value3) & 0x0ff; + result |= byteValue << (i * 8); + predicate >>= 1; + value2 >>= 8; + value3 >>= 8; + } + + memoryState.setValue(out, result); + } + + } + + private abstract class VectorOpBehavior implements OpBehaviorOther { + + protected final String opName; + protected final int slotBitSize; + protected final long slotMask; + + VectorOpBehavior(String opName, int slotBitSize) { + this.opName = opName; + this.slotBitSize = slotBitSize; + slotMask = ~(-1L << slotBitSize); + } + + protected void evaluate(MemoryState memoryState, Varnode out, long[] inputs, + Function opFunction) { + + if (out == null) { + throw new LowlevelError(opName + ": missing required double-word output (Rdd)"); + } + if (out.getSize() != 8) { + throw new LowlevelError(opName + ": output size must be double-word"); + } + + long result = 0; + for (int slot = (64 / slotBitSize) - 1; slot >= 0; slot--) { + result <<= slotBitSize; + result |= opFunction.apply(slot) & slotMask; + } + memoryState.setValue(out, result); + } + } + + private class VectorLogicalShiftRightOpBehavior extends VectorOpBehavior { + + private final int shiftBitSize; + + VectorLogicalShiftRightOpBehavior(String opName, int slotBitSize, int shiftBitSize) { + super(opName, slotBitSize); + this.shiftBitSize = shiftBitSize; + } + + @Override + public void evaluate(Emulate e, Varnode out, Varnode[] inputs) { + if (inputs.length != 2) { + throw new LowlevelError(opName + ": requires two inputs"); + } + + MemoryState memoryState = e.getMemoryState(); + long source = memoryState.getValue(inputs[0]); + + // signed shift value (negative value is left shift) + long shiftValue = + inputs[1].isConstant() ? inputs[1].getOffset() : memoryState.getValue(inputs[1]); + int s = 64 - shiftBitSize; + shiftValue = (shiftValue << s) >> s; // sign-extend shift value + + final long shift = shiftValue; + evaluate(memoryState, out, new long[] { source, shift }, slot -> { + long r = 0; + if (Math.abs(shift) < 64) { + int slotShift = slot * slotBitSize; + r = (source >> slotShift) & slotMask; + if (shift < 0) { + r <<= -shift; + } + else { + r >>>= shift; + } + r &= slotMask; + } + return r; + }); + } + } + + private class VectorLogicalShiftLeftOpBehavior extends VectorOpBehavior { + + private final int shiftBitSize; + + VectorLogicalShiftLeftOpBehavior(String opName, int slotBitSize, int shiftBitSize) { + super(opName, slotBitSize); + this.shiftBitSize = shiftBitSize; + } + + @Override + public void evaluate(Emulate e, Varnode out, Varnode[] inputs) { + if (inputs.length != 2) { + throw new LowlevelError(opName + ": requires two inputs"); + } + + MemoryState memoryState = e.getMemoryState(); + long source = memoryState.getValue(inputs[0]); + + // signed shift value (negative value is right shift) + long shiftValue = + inputs[1].isConstant() ? inputs[1].getOffset() : memoryState.getValue(inputs[1]); + int s = 64 - shiftBitSize; + shiftValue = (shiftValue << s) >> s; // sign-extend shift value + + final long shift = shiftValue; + evaluate(memoryState, out, new long[] { source, shift }, slot -> { + long r = 0; + if (Math.abs(shift) < 64) { + int slotShift = slot * slotBitSize; + r = (source >> slotShift) & slotMask; + if (shift < 0) { + r >>>= -shift; + } + else { + r <<= shift; + } + r &= slotMask; + } + return r; + }); + } + } + + private class VectorAbsoluteValueOpBehavior extends VectorOpBehavior { + + private final long signBitMask; + + VectorAbsoluteValueOpBehavior(String opName, int slotBitSize) { + super(opName, slotBitSize); + signBitMask = 1 << (slotBitSize - 1); + } + + @Override + public void evaluate(Emulate e, Varnode out, Varnode[] inputs) { + if (inputs.length != 1) { + throw new LowlevelError(opName + ": requires one input"); + } + + MemoryState memoryState = e.getMemoryState(); + long source = memoryState.getValue(inputs[0]); + + evaluate(memoryState, out, new long[] { source }, slot -> { + int slotShift = slot * slotBitSize; + long r = (source >> slotShift) & slotMask; + if ((r & signBitMask) != 0) { + r = (~r + 1) & slotMask; // negate with 2's complement + } + return r; + }); + } + } + + private class DFMultiplyFixOpBehavior implements OpBehaviorOther { + + @Override + public void evaluate(Emulate e, Varnode out, Varnode[] inputs) { + + if (out == null || out.getSize() != 8) { + throw new LowlevelError("dfmpyfix: requires 8-byte output"); + } + + if (inputs.length != 2) { + throw new LowlevelError("dfmpyfix: requires two inputs"); + } + + for (int i = 0; i < 2; i++) { + if (inputs[i].getSize() != 8) { + throw new LowlevelError("dfmpyhh: requires two 8-byte inputs"); + } + } + + MemoryState memoryState = e.getMemoryState(); + long rss = memoryState.getValue(inputs[0]); + long rtt = memoryState.getValue(inputs[1]); + + BigFloat rssBf = fp64Format.decodeBigFloat(rss); + BigFloat rttBf = fp64Format.decodeBigFloat(rtt); + + long result = rss; + if (!rssBf.isNormal() && (getExponent(rtt, rttBf) >= 512) && rttBf.isNormal()) { + rssBf.mul(fp64Format.decodeBigFloat(0x4330000000000000L)); + result = fp64Format.getEncoding(rssBf).longValue(); + } + else if (!rttBf.isNormal() && (getExponent(rss, rssBf) >= 512) && rssBf.isNormal()) { + rssBf.mul(fp64Format.decodeBigFloat(0x3cb0000000000000L)); + result = fp64Format.getEncoding(rssBf).longValue(); + } + memoryState.setValue(out, result); + } + + } + + private class DFMultiplyHHOpBehavior implements OpBehaviorOther { + + @Override + public void evaluate(Emulate e, Varnode out, Varnode[] inputs) { + // Multiply high*high and accumulate with L*H value + + if (out == null || out.getSize() != 8) { + throw new LowlevelError("dfmpyhh: requires 8-byte output"); + } + + if (inputs.length != 3) { + throw new LowlevelError("dfmpyhh: requires three inputs"); + } + + for (int i = 0; i < 3; i++) { + if (inputs[i].getSize() != 8) { + throw new LowlevelError("dfmpyhh: requires three 8-byte inputs"); + } + } + + MemoryState memoryState = e.getMemoryState(); + long rdd = memoryState.getValue(inputs[0]); // accumulated + long rss = memoryState.getValue(inputs[1]); + long rtt = memoryState.getValue(inputs[2]); + + BigFloat rssBf = fp64Format.decodeBigFloat(rss); + BigFloat rttBf = fp64Format.decodeBigFloat(rtt); + + long result; + if (rssBf.isZero() || rssBf.isNaN() || rssBf.isInfinite() || rttBf.isZero() || + rttBf.isNaN() || rttBf.isInfinite()) { + result = fp64Format.getEncoding(BigFloat.mul(rssBf, rttBf)).longValue(); + } + else { + FPAccumulator x = new FPAccumulator(); + + x.sticky = (rdd & 1) != 0; + x.mant = toUnsignedBigInteger(rdd >> 1); + + long prod = (getMantissa(rss, rssBf) >>> 32) * (getMantissa(rtt, rttBf) >>> 32); + x.mant = toUnsignedBigInteger(prod).multiply(toUnsignedBigInteger(0x100000000L)) + .add(x.mant); + x.exp = getExponent(rss, rssBf) + getExponent(rtt, rttBf) - FP64_BIAS - 20; + + if (!rssBf.isNormal() || !rttBf.isNormal()) { + // crush to inexact zero + x.sticky = true; + x.exp = -4096; + } + + x.negative = isNegative(rss) ^ isNegative(rtt); + + result = round(x); + } + memoryState.setValue(out, result); + } + } + + private static class FPAccumulator { + BigInteger mant = BigInteger.ZERO; + int exp; + boolean negative; + boolean guard; + boolean round; + boolean sticky; + } + + private static BigInteger toUnsignedBigInteger(long ulong) { + if (ulong >= 0L) { + return BigInteger.valueOf(ulong); + } + int upper = (int) (ulong >>> 32); + int lower = (int) ulong; + return (BigInteger.valueOf(Integer.toUnsignedLong(upper))).shiftLeft(32) + .add(BigInteger.valueOf(Integer.toUnsignedLong(lower))); + } + + private static boolean isNegative(long f64) { + return f64 < 0; + } + + private static int getExponent(long f64, BigFloat f) { + int exp = (int) (f64 >> FP64_MANTISSA_BITS) & 0x7ff; + if (f.isNormal()) { + return exp; + } + if (f.isDenormal()) { + return exp + 1; + } + return -1; + } + + private static long getMantissa(long f64, BigFloat f) { + int shift = 64 - FP64_MANTISSA_BITS; + long aMant = (f64 << shift) >>> shift; + if (f.isNormal()) { + aMant |= (1L << FP64_MANTISSA_BITS); + } + else if (f.isZero()) { + aMant = 0L; + } + else if (!f.isDenormal()) { + aMant = ~0L; + } + return aMant; + } + + private static long getLo64(BigInteger b) { + return b.longValue(); + } + + private static long getHi64(BigInteger b) { + return b.shiftRight(64).longValue(); + } + + /** + * Perform normalization and rounding of FP64 accumulator value. + * + * @param x accumulator + * @return encoded fp64 value + */ + private static long round(FPAccumulator x) { + + if ((x.sticky || x.round || x.guard) && x.mant.equals(BigInteger.ZERO)) { + return fp64Format.getZeroEncoding(false); + } + + while (getHi64(x.mant) != 0 || (getLo64(x.mant) >>> (FP64_MANTISSA_BITS + 1) != 0)) { + normalizeRight(x, 1); + } + + while ((getLo64(x.mant) & (1L << FP64_MANTISSA_BITS)) == 0) { + normalizeLeft(x); + } + + while (x.exp <= 0) { + normalizeRight(x, 1 - x.exp); +// if (x.sticky || x.round || x.guard) { +// // raise underflow +// } + } + + if (getLo64(x.mant) >> (FP64_MANTISSA_BITS + 1) != 0) { + normalizeRight(x, 1); + } + + if (x.exp >= FP64_INFINITY_EXP) { + return fp64Format.getInfinityEncoding(x.negative); + } + + long f64 = 0; + if (x.negative) { + f64 = Long.MIN_VALUE; + } + if ((getLo64(x.mant) & (1L << FP64_MANTISSA_BITS)) != 0) { + f64 |= ((long) x.exp) << FP64_MANTISSA_BITS; + } + f64 |= getLo64(x.mant) & 0xfffffffffffffL; + return f64; + } + + private static void normalizeLeft(FPAccumulator x) { + x.exp--; + x.mant = x.mant.shiftLeft(1); + if (x.guard) { + x.mant = x.mant.or(BigInteger.ONE); + } + x.guard = x.round; + x.round = x.sticky; + } + + private static void normalizeRight(FPAccumulator a, int n) { + if (n > 130) { + a.sticky |= a.round | a.guard | (a.mant.compareTo(BigInteger.ZERO) == 0); + a.guard = a.round = false; + a.mant = BigInteger.ZERO; + a.exp += n; + return; + } + while (n >= 64) { + a.sticky |= a.round | a.guard | (getLo64(a.mant) != 0); + a.guard = ((getLo64(a.mant) >> 63) & 1) != 0; + a.round = ((getLo64(a.mant) >> 62) & 1) != 0; + a.mant = toUnsignedBigInteger(getHi64(a.mant)); + a.exp += 64; + n -= 64; + } + while (n > 0) { + a.exp++; + a.sticky |= a.round; + a.round = a.guard; + a.guard = (getLo64(a.mant) & 1) != 0; + a.mant = a.mant.shiftRight(1); + n--; + } + } + + public static void main(String[] args) { + + long expect = 0x4023b81d7dbf4880L; + long rdd = 0x00202752200f06f7L; // memoryState.getValue(inputs[1]); // accumulated + long rss = 0x40091eb851eb851fL; + long rtt = 0x40091eb851eb851fL; + + BigFloat expBf = fp64Format.decodeBigFloat(expect); + + BigFloat rddBf = fp64Format.decodeBigFloat(rdd); + BigFloat rssBf = fp64Format.decodeBigFloat(rss); + BigFloat rttBf = fp64Format.decodeBigFloat(rtt); + + BigFloat expProdBf = BigFloat.sub(expBf, rddBf); + + System.out.println("expectProd=" + fp64Format.round(expProdBf).toString()); + System.out.println("rss=" + fp64Format.round(rssBf).toString()); + System.out.println("rtt=" + fp64Format.round(rttBf).toString()); + + FPAccumulator x = new FPAccumulator(); + + x.sticky = (rdd & 1) != 0; + x.mant = toUnsignedBigInteger(rdd >> 1); + + long prod = (getMantissa(rss, rssBf) >>> 32) * (getMantissa(rtt, rttBf) >>> 32); + x.mant = + toUnsignedBigInteger(prod).multiply(toUnsignedBigInteger(0x100000000L)).add(x.mant); + x.exp = getExponent(rss, rssBf) + getExponent(rtt, rttBf) - FP64_BIAS - 20; + + if (!rssBf.isNormal() || !rttBf.isNormal()) { + // crush to inexact zero + x.sticky = true; + x.exp = -4096; + } + + x.negative = isNegative(rss) ^ isNegative(rtt); + + long result = round(x); + BigFloat resultBf = fp64Format.decodeBigFloat(result); + + System.out.println("result=" + fp64Format.round(resultBf).toString()); + System.out.println("expected=" + fp64Format.round(expBf).toString()); + + System.out.println( + "result: 0x" + Long.toHexString(result) + " Expected: 0x" + Long.toHexString(expect)); + + } + + private class DFMultiplyLHOpBehavior implements OpBehaviorOther { + + @Override + public void evaluate(Emulate e, Varnode out, Varnode[] inputs) { + // Multiply low*high and accumulate + // Rdd32 += (Rss.uw[0] * (0x00100000 | zxt 20->64 (Rtt.uw[1]))) << 1; + + if (out == null || out.getSize() != 8) { + throw new LowlevelError("dfmpylh: requires 8-byte output"); + } + + if (inputs.length != 3) { + throw new LowlevelError("dfmpylh: requires three inputs"); + } + + for (int i = 0; i < 3; i++) { + if (inputs[i].getSize() != 8) { + throw new LowlevelError("dfmpylh: requires three 8-byte inputs"); + } + } + + MemoryState memoryState = e.getMemoryState(); + long rdd = memoryState.getValue(inputs[0]); // accumulated + long rssLo = memoryState.getValue(inputs[1]) & 0xffffffffL; // Rss.uw[0] + long rttHi = memoryState.getValue(inputs[2]) >>> 32; // Rtt.uw[1] + + long prod = (rssLo * (0x00100000L | (rttHi & 0xfffffL))) << 1; + long result = rdd + prod; + + memoryState.setValue(out, result); + } + + } + + private class DFMultiplyLLOpBehavior implements OpBehaviorOther { + + @Override + public void evaluate(Emulate e, Varnode out, Varnode[] inputs) { + // Multiply low*low and shift off low 32 bits into sticky (in MSB) + + if (out == null || out.getSize() != 8) { + throw new LowlevelError("dfmpyll: requires 8-byte output"); + } + + if (inputs.length != 2) { + throw new LowlevelError("dfmpyll: requires two inputs"); + } + + for (int i = 0; i < 2; i++) { + if (inputs[i].getSize() != 8) { + throw new LowlevelError("dfmpyll: requires two 8-byte inputs"); + } + } + + MemoryState memoryState = e.getMemoryState(); + long rssLo = memoryState.getValue(inputs[0]) & 0xffffffffL; + long rttLo = memoryState.getValue(inputs[1]) & 0xffffffffL; + long prod = rssLo * rttLo; + long result = (prod >>> 32) << 1; + if ((prod & 0xffffffffL) != 0) { + result |= 1; + } + memoryState.setValue(out, result); + } + + } +} diff --git a/Ghidra/Processors/Hexagon/src/main/java/ghidra/program/emulation/HexagonFp32.java b/Ghidra/Processors/Hexagon/src/main/java/ghidra/program/emulation/HexagonFp32.java new file mode 100644 index 0000000000..86aebb0694 --- /dev/null +++ b/Ghidra/Processors/Hexagon/src/main/java/ghidra/program/emulation/HexagonFp32.java @@ -0,0 +1,56 @@ +/* ### + * IP: GHIDRA + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +package ghidra.program.emulation; + +public enum HexagonFp32 { + ; + public static final int FP32_FRAC_POS = 0; + public static final int FP32_FRAC_SIZE = 23; + public static final int FP32_FRAC_MASK = ((1 << FP32_FRAC_SIZE) - 1) << FP32_FRAC_POS; + public static final int FP32_EXP_POS = FP32_FRAC_POS + FP32_FRAC_SIZE; + public static final int FP32_EXP_SIZE = 8; + public static final int FP32_EXP_MASK = ((1 << FP32_EXP_SIZE) - 1) << FP32_EXP_POS; + public static final int FP32_SIGN_POS = FP32_EXP_POS + FP32_EXP_SIZE; + public static final int FP32_BIAS = (1 << FP32_EXP_SIZE - 1) - 1; + + static int maskFp32Exponent(int valueBits) { + return FP32_EXP_MASK & valueBits; + } + + static int maskFp32Fraction(int valueBits) { + return FP32_FRAC_MASK & valueBits; + } + + static boolean isFp32Zero(int exp, int frac) { + return exp == 0 && frac == 0; + } + + static boolean isFp32Normal(int exp, int frac) { + return exp != 0 && exp != FP32_EXP_MASK; + } + + static boolean isFp32Subnormal(int exp, int frac) { + return exp == 0 && frac != 0; + } + + static boolean isFp32Infinite(int exp, int frac) { + return exp == FP32_EXP_MASK && frac == 0; + } + + static boolean isFp32Nan(int exp, int frac) { + return exp == FP32_EXP_MASK && frac != 0; + } +} diff --git a/Ghidra/Processors/Hexagon/src/main/java/ghidra/program/emulation/HexagonFp64.java b/Ghidra/Processors/Hexagon/src/main/java/ghidra/program/emulation/HexagonFp64.java new file mode 100644 index 0000000000..3467aa9d77 --- /dev/null +++ b/Ghidra/Processors/Hexagon/src/main/java/ghidra/program/emulation/HexagonFp64.java @@ -0,0 +1,229 @@ +/* ### + * IP: GHIDRA + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +package ghidra.program.emulation; + +public enum HexagonFp64 { + ; + public static final int FP64_FRAC_POS = 0; + public static final int FP64_FRAC_SIZE = 52; + public static final long FP64_FRAC_MASK = ((1L << FP64_FRAC_SIZE) - 1) << FP64_FRAC_POS; + public static final int FP64_EXP_POS = FP64_FRAC_POS + FP64_FRAC_SIZE; + public static final int FP64_EXP_SIZE = 11; + public static final long FP64_EXP_MASK = ((1L << FP64_EXP_SIZE) - 1) << FP64_EXP_POS; + public static final int FP64_SIGN_POS = FP64_EXP_POS + FP64_EXP_SIZE; + public static final int FP64_BIAS = (1 << FP64_EXP_SIZE - 1) - 1; + public static final int FP64_EXP_INF = (int) (FP64_EXP_MASK >>> FP64_EXP_POS); + + static long maskFp64Exponent(long valueBits) { + return FP64_EXP_MASK & valueBits; + } + + static long maskFp64Fraction(long valueBits) { + return FP64_FRAC_MASK & valueBits; + } + + static boolean isFp64Zero(long exp, long frac) { + return exp == 0 && frac == 0; + } + + static boolean isFp64Normal(long exp, long frac) { + return exp != 0 && exp != FP64_EXP_MASK; + } + + static boolean isFp64Subnormal(long exp, long frac) { + return exp == 0 && frac != 0; + } + + static boolean isFp64Infinite(long exp, long frac) { + return exp == FP64_EXP_MASK && frac == 0; + } + + static boolean isFp64Nan(long exp, long frac) { + return exp == FP64_EXP_MASK && frac != 0; + } + + static boolean isFp64Negative(long bits) { + return bits < 0; + } + + static long getFp64Fraction(long exp, long frac) { + // Note: No additional shifting of frac necessary, as FP64_FRAC_POS = 0 + if (isFp64Normal(exp, frac)) { + return frac | (1L << FP64_FRAC_SIZE); + } + if (isFp64Zero(exp, frac)) { + return 0L; + } + if (!isFp64Subnormal(exp, frac)) { + return -1L; + } + return frac; + } + + static int getFp64Exponent(long exp, long frac) { + if (isFp64Normal(exp, frac)) { + return (int) (exp >>> FP64_EXP_POS); + } + if (isFp64Subnormal(exp, frac)) { + return (int) (exp >>> FP64_EXP_POS) + 1; + } + return -1; + } + + static long encSign(boolean negative) { + return negative ? Long.MIN_VALUE : 0; + } + + static long encExp(int exp, long mantUpper) { + if ((mantUpper >>> (FP64_FRAC_SIZE - 32)) == 0) { + return 0; + } + return Integer.toUnsignedLong(exp) << FP64_EXP_POS; + } + + static long encFrac(long mantUpper, int mantLower) { + return ((mantUpper << 32) | Integer.toUnsignedLong(mantLower)) & FP64_FRAC_MASK; + } + + public static long dfmpyhh(long rdd, long rss, long rtt) { + long expRss = maskFp64Exponent(rss); + long fracRss = maskFp64Fraction(rss); + + long expRtt = maskFp64Exponent(rtt); + long fracRtt = maskFp64Fraction(rtt); + + if (isFp64Zero(expRss, fracRss) || isFp64Nan(expRss, fracRss) || + isFp64Infinite(expRss, fracRss) || + isFp64Zero(expRtt, fracRtt) || isFp64Nan(expRtt, fracRtt) || + isFp64Infinite(expRtt, fracRtt)) { + return Double.doubleToRawLongBits( + Double.longBitsToDouble(rss) * Double.longBitsToDouble(rtt)); + } + + // Read Accumulated from rdd + boolean sticky = (rdd & 1) != 0; + int mantLower = (int) (rdd >> 1); + long mantUpper = rdd >> 33; + + long prod = (getFp64Fraction(expRss, fracRss) >>> 32) * + (getFp64Fraction(expRtt, fracRtt) >>> 32); + mantUpper += prod; + + int exp = getFp64Exponent(expRss, fracRss) + getFp64Exponent(expRtt, fracRtt) - + FP64_BIAS - 20; + if (!isFp64Normal(expRss, fracRss) || !isFp64Normal(expRtt, fracRtt)) { + // Crush to inexact 0 + sticky = true; + exp = -4096; + } + + boolean negative = isFp64Negative(rss) ^ isFp64Negative(rtt); + + // round + boolean round = false; + boolean guard = false; + if (sticky && mantLower == 0 && mantUpper == 0) { + return Double.doubleToRawLongBits(0.0); + } + + // normalize right for fraction + // 32 is size of mantLower + for (; mantUpper >>> (FP64_FRAC_SIZE + 1 - 32) != 0; exp++) { + sticky |= round; + round = guard; + guard = (mantLower & 1) != 0; + mantLower >>>= 1; + mantLower |= (mantUpper << 63) >>> 32; + mantUpper >>>= 1; + } + // (else) normalize left for fraction + for (; (mantUpper & (1L << FP64_FRAC_SIZE - 32)) == 0; exp--) { + mantUpper <<= 1; + mantUpper |= mantLower >>> 31; + mantLower <<= 1; + mantLower |= guard ? 1 : 0; + guard = round; + round = sticky; + } + // normalize right for exponent + if (1 - exp > 130) { // if (exp < -129) + sticky |= round | guard | (mantLower == 0 && mantUpper == 0); + guard = false; + round = false; + exp = 1; + } + for (; 1 - exp >= 64; exp += 64) { // while (exp <= -63) + // Can this be re-specialized to this 64|32-bit split? + sticky |= round | guard | (mantLower == 0 && (mantUpper & 0x0_ffff_ffffL) == 0); + guard = (mantUpper >>> 31) != 0; + round = (mantUpper >>> 30) != 0; + /** + * effective shift right 64 bits + * + * | ----- long upper ---- | int lower | + * + * |BB:AA:99:88:77:66:55:44|33:22:11:00| + * + * |00:00:00:00:00:00:00:00|BB:AA:99:88| + */ + mantLower = (int) (mantUpper >>> 32); + mantUpper = 0; + } + for (; 1 - exp >= 0; exp++) { + sticky |= round; + round = guard; + guard = (mantLower & 1) != 0; + mantLower >>>= 1; + mantLower |= (mantUpper << 63) >>> 32; + mantUpper >>>= 1; + } + + // one more normalize right for fraction + if (mantUpper >>> (FP64_FRAC_SIZE + 1 - 32) != 0) { + sticky |= round; + round = guard; + guard = (mantLower & 1) != 0; + mantLower >>>= 1; + mantLower |= (mantUpper << 63) >>> 32; + mantUpper >>>= 1; + exp++; + } + if (exp >= FP64_EXP_INF) { + return Double.doubleToRawLongBits(negative + ? Double.NEGATIVE_INFINITY + : Double.POSITIVE_INFINITY); + } + return encSign(negative) | encExp(exp, mantUpper) | encFrac(mantUpper, mantLower); + } + + public static long dfmpyfix(long rss, long rtt) { + long expRss = maskFp64Exponent(rss); + long fracRss = maskFp64Fraction(rss); + + long expRtt = maskFp64Exponent(rtt); + long fracRtt = maskFp64Exponent(rtt); + + if (!isFp64Normal(expRss, fracRss) && isFp64Normal(expRtt, fracRtt) && + expRtt >= (512 << FP64_EXP_POS)) { + return Double.doubleToRawLongBits(Double.longBitsToDouble(rss) * 0x1.0p52); + } + if (!isFp64Normal(expRtt, fracRtt) && isFp64Normal(expRss, fracRss) && + expRss >= (512 << FP64_EXP_POS)) { + return Double.doubleToRawLongBits(Double.longBitsToDouble(rss) * 0x1.0p-52); + } + return rss; + } +} diff --git a/Ghidra/Processors/Hexagon/src/main/java/ghidra/program/emulation/HexagonPcodeUseropLibraryFactory.java b/Ghidra/Processors/Hexagon/src/main/java/ghidra/program/emulation/HexagonPcodeUseropLibraryFactory.java new file mode 100644 index 0000000000..61b7cc92aa --- /dev/null +++ b/Ghidra/Processors/Hexagon/src/main/java/ghidra/program/emulation/HexagonPcodeUseropLibraryFactory.java @@ -0,0 +1,210 @@ +/* ### + * IP: GHIDRA + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +package ghidra.program.emulation; + +import java.util.function.Function; + +import ghidra.app.plugin.processors.sleigh.SleighLanguage; +import ghidra.pcode.error.LowlevelError; +import ghidra.pcode.exec.*; +import ghidra.pcode.exec.PcodeUseropLibraryFactory.UseropLibrary; +import ghidra.program.model.pcode.Varnode; + +@UseropLibrary("hexagon") +public class HexagonPcodeUseropLibraryFactory implements PcodeUseropLibraryFactory { + @Override + public PcodeUseropLibrary create(SleighLanguage language, + PcodeArithmetic arithmetic) { + return new HexagonPcodeUseropLibrary(language); + } + + public static class HexagonPcodeUseropLibrary extends AnnotatedPcodeUseropLibrary { + private static final int FP_ZERO_CLASS_MASK = 0x01; + private static final int FP_NORMAL_CLASS_MASK = 0x02; + private static final int FP_SUBNORMAL_CLASS_MASK = 0x04; + private static final int FP_INFINITE_CLASS_MASK = 0x08; + private static final int FP_NAN_CLASS_MASK = 0x10; + + public HexagonPcodeUseropLibrary(SleighLanguage language) { + SleighPcodeUseropDefinition.Factory factory = + new SleighPcodeUseropDefinition.Factory(language); + + putOp(factory.define("min").params("a", "b").body(args -> """ + if (a s<= b) goto ; + __op_output = b; + goto ; + + __op_output = a; + + """).build()); + + putOp(factory.define("vlslh") + .params("source", "shift") + .body(args -> genVecShift(args.get(0), 16, "<<", ">>")) + .build()); + putOp(factory.define("vlsrh") + .params("source", "shift") + .body(args -> genVecShift(args.get(0), 16, ">>", "<<")) + .build()); + putOp(factory.define("vlslw") + .params("source", "shift") + .body(args -> genVecShift(args.get(0), 32, "<<", ">>")) + .build()); + putOp(factory.define("vlsrw") + .params("source", "shift") + .body(args -> genVecShift(args.get(0), 32, ">>", "<<")) + .build()); + + putOp(factory.define("vmux").params("sel", "a", "b").body(args -> """ + local s:1; + local result:8; + """ + genVec(0, 8, 1, i -> """ + s = ((sel >> %d) & 1) * 0xff; + result[%d,8] = (a[%d,8] & s) | (b[%d,8] & ~s); + """.formatted(i, 8 * i, 8 * i, 8 * i)) + """ + __op_output = result; + """).build()); + + putOp(factory.define("vabsh").params("n").body(args -> genVecAbs(16)).build()); + putOp(factory.define("vabsw").params("n").body(args -> genVecAbs(32)).build()); + + putOp(factory.define("dfmpylh").params("rdd", "rss", "rtt").body(args -> """ + rss_lo:8 = rss & 0xffffffff; + rtt_hi:8 = rtt >> 32; + prod:8 = (rss_lo * (0x00100000 | (rtt_hi & 0xfffff))) << 1; + __op_output = rdd + prod; + """).build()); + putOp(factory.define("dfmpyll").params("rss", "rtt").body(args -> """ + rss_lo:8 = rss & 0xffffffff; + rtt_lo:8 = rtt & 0xffffffff; + prod:8 = rss_lo * rtt_lo; + result:8 = (prod >> 32) << 1; + if ((prod & 0xffffffff) == 0) goto ; + result = result + 1; + + __op_output = result; + """).build()); + + putOp(factory.define("isClassifiedFloat") + .params("bits", "cls") + .body(args -> switch (args.get(1).getSize()) { + case 4 -> "__op_output = __isClassifiedFloat32(bits, cls);"; + case 8 -> "__op_output = __isClassifiedFloat64(bits, cls);"; + default -> throw new LowlevelError( + "isClassifiedFloat: invalid float size of " + args.get(0).getSize()); + }) + .build()); + } + + protected String genVec(int start, int stop, int step, Function slot) { + StringBuffer buf = new StringBuffer(); + for (int i = start; i < stop; i += step) { + buf.append(slot.apply(i)); + } + return buf.toString(); + } + + protected String genVecShift(Varnode source, int slotSize, String posOp, String negOp) { + int regSize = source.getSize() * 8; + return """ + s:1 = (shift[0,8] << 1) s>> 1; + if (s s< 0) goto ; + """ + genVec(0, regSize, slotSize, slot -> """ + __op_output[%d,%d] = source[%d,%d] %s s; + """.formatted(slot, slotSize, slot, slotSize, posOp)) + """ + goto ; + + """ + genVec(0, regSize, slotSize, slot -> """ + __op_output[%d,%d] = source[%d,%d] %s s; + """.formatted(slot, slotSize, slot, slotSize, negOp)) + """ + + """; + } + + protected String genVecAbs(int slotSize) { + long signMask = Long.MIN_VALUE; + for (int i = 32; i >= slotSize; i >>>= 1) { + signMask |= (signMask >>> i); + } + long sm = signMask; + long mult = -1L >>> (64 - slotSize); + return """ + s = n & 0x%x; + ones = s >> %d; + mask = ones * 0x%x; + inv = n ^ mask; + """.formatted(sm, slotSize - 1, mult) + genVec(0, 64, slotSize, slot -> """ + __op_output[%d,%d] = inv[%d,%d] + ones[%d,%d]; + """.formatted(slot, slotSize, slot, slotSize, slot, slotSize)); + } + + @PcodeUserop(functional = true) + public static int __isClassifiedFloat32(int valueBits, int cls) { + int exp = HexagonFp32.maskFp32Exponent(valueBits); + int frac = HexagonFp32.maskFp32Fraction(valueBits); + if ((cls & FP_ZERO_CLASS_MASK) != 0 && HexagonFp32.isFp32Zero(exp, frac)) { + return 0xff; + } + if ((cls & FP_NORMAL_CLASS_MASK) != 0 && HexagonFp32.isFp32Normal(exp, frac)) { + return 0xff; + } + if ((cls & FP_SUBNORMAL_CLASS_MASK) != 0 && HexagonFp32.isFp32Subnormal(exp, frac)) { + return 0xff; + } + if ((cls & FP_INFINITE_CLASS_MASK) != 0 && HexagonFp32.isFp32Infinite(exp, frac)) { + return 0xff; + } + if ((cls & FP_NAN_CLASS_MASK) != 0 && HexagonFp32.isFp32Nan(exp, frac)) { + return 0xff; + } + return 0; + } + + @PcodeUserop(functional = true) + public static int __isClassifiedFloat64(long valueBits, int cls) { + long exp = HexagonFp64.maskFp64Exponent(valueBits); + long frac = HexagonFp64.maskFp64Fraction(valueBits); + if ((cls & FP_ZERO_CLASS_MASK) != 0 && HexagonFp64.isFp64Zero(exp, frac)) { + return 0xff; + } + if ((cls & FP_NORMAL_CLASS_MASK) != 0 && HexagonFp64.isFp64Normal(exp, frac)) { + return 0xff; + } + if ((cls & FP_SUBNORMAL_CLASS_MASK) != 0 && HexagonFp64.isFp64Subnormal(exp, frac)) { + return 0xff; + } + if ((cls & FP_INFINITE_CLASS_MASK) != 0 && HexagonFp64.isFp64Infinite(exp, frac)) { + return 0xff; + } + if ((cls & FP_NAN_CLASS_MASK) != 0 && HexagonFp64.isFp64Nan(exp, frac)) { + return 0xff; + } + return 0; + } + + // LATER: Could/should this be done in Sleigh instead? + @PcodeUserop(functional = true) + public static long dfmpyfix(long rss, long rtt) { + return HexagonFp64.dfmpyfix(rss, rtt); + } + + // LATER: Could/should this be done in Sleigh instead? + @PcodeUserop(functional = true) + public static long dfmpyhh(long rdd, long rss, long rtt) { + return HexagonFp64.dfmpyhh(rdd, rss, rtt); + } + } +} diff --git a/Ghidra/Processors/Hexagon/src/test.processors/java/ghidra/test/processors/HexagonPcodeEmulatorTest.java b/Ghidra/Processors/Hexagon/src/test.processors/java/ghidra/test/processors/HexagonPcodeEmulatorTest.java new file mode 100644 index 0000000000..a878aa2fab --- /dev/null +++ b/Ghidra/Processors/Hexagon/src/test.processors/java/ghidra/test/processors/HexagonPcodeEmulatorTest.java @@ -0,0 +1,115 @@ +/* ### + * IP: GHIDRA + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +package ghidra.test.processors; + +import static org.junit.Assert.assertArrayEquals; +import static org.junit.Assert.fail; + +import org.junit.Test; + +import ghidra.app.util.PseudoInstruction; +import ghidra.pcode.emu.*; +import ghidra.pcode.exec.*; +import ghidra.pcode.exec.PcodeExecutorStatePiece.Reason; +import ghidra.program.model.address.Address; +import ghidra.program.model.address.AddressSpace; +import ghidra.program.model.lang.LanguageID; +import ghidra.program.model.lang.RegisterValue; +import ghidra.program.model.pcode.PcodeOp; +import ghidra.test.AbstractGhidraHeadlessIntegrationTest; +import ghidra.util.NumericUtilities; + +public class HexagonPcodeEmulatorTest extends AbstractGhidraHeadlessIntegrationTest { + @Test + public void testCunitSample() throws Throwable { + PcodeEmulator emu = new PcodeEmulator( + getLanguageService().getLanguage(new LanguageID("Hexagon:LE:32:default"))) { + @Override + protected BytesPcodeThread createThread(String name) { + return new BytesPcodeThread(name, this) { + @Override + protected PcodeThreadExecutor createExecutor() { + return new PcodeThreadExecutor<>(this) { + @Override + public void stepOp(PcodeOp op, PcodeFrame frame, + PcodeUseropLibrary library) { + //System.err.println(" StepOp: " + op); + super.stepOp(op, frame, library); + } + }; + } + + @Override + protected SleighInstructionDecoder createInstructionDecoder( + PcodeExecutorState sharedState) { + return new SleighInstructionDecoder(language, sharedState) { + @Override + public PseudoInstruction decodeInstruction(Address address, + RegisterValue context) { + PseudoInstruction instruction = + super.decodeInstruction(address, context); + //System.err.println("Decoded " + address + ": " + instruction); + return instruction; + } + }; + } + }; + } + }; + PcodeThread thread = emu.newThread(); + AddressSpace as = emu.getLanguage().getDefaultSpace(); + + byte[] code_db54 = NumericUtilities.convertStringToBytes(""" + 09c09da0284a000042c300782e4a000003c0007841e7007800c06270f9e29ea702c06370f8e39ea784c + e035a20c0c049ffe0dea742c0c049fee2dea7e2ffde97c4ffde97fbe0dea700c203f502c405f5f8c100 + 5afde0dea7a4ffde9702c07d7060ffde9700c0c2a121e8007802c0007820ff9e97f5e29ea7fcc9035a6 + 0c0c049f9e0dea722ffde97dcc1005a02c07d7004c1c04900c4c2a142e8007823ff9e97f8e0dea700c0 + 637001c06270a2fe9e9704ffde97dec9035a81e8007820ff9e9702ff9e972ace035a1ec01e96""" + .replaceAll("\\s+", "")); + emu.getSharedState().setVar(as, 0xdb54, code_db54.length, false, code_db54); + + byte[] code_27a00 = NumericUtilities.convertStringToBytes(""" + 00478185004780850440c14326c0c1432e40205c004882754840c1416ac0c1412640005c00448275004 + 4c04408c6c04401458275024682758c40c141aec8c1430248c0a103cac0a100527f53204cc04029cec0 + 4000478275c440c191e6c0c14300409f520644c0a138c6c0401aefff59""" + .replaceAll("\\s+", "")); + emu.getSharedState().setVar(as, 0x27a00, code_27a00.length, false, code_27a00); + + byte[] src = new byte[64]; + for (int i = 0; i < src.length; i++) { + src[i] = (byte) (31 * i + 5); + } + emu.getSharedState().setVar(as, 0x10002000, src.length, false, src); + + emu.addBreakpoint(as.getAddress(0xDEADBEEFL), "1:1"); + //thread.getExecutor().executeSleigh("PC=0xdb54; SP=0x40000000;"); + thread.getExecutor() + .executeSleigh("PC=0x27a00; SP=0x4000000; R0=0x10001000; R1=0x10002000; R2=" + + src.length + "; LR=0xDEADBEEF;"); + thread.reInitialize(); + + try { + thread.run(); + fail(); + } + catch (InterruptPcodeExecutionException e) { + // We hit the breakpoint. Good. + } + + byte[] dst = emu.getSharedState().getVar(as, 0x10001000, src.length, false, Reason.INSPECT); + assertArrayEquals(src, dst); + } +} diff --git a/Ghidra/Processors/Hexagon/src/test.processors/java/ghidra/test/processors/Hexagon_O0_EmulatorTest.java b/Ghidra/Processors/Hexagon/src/test.processors/java/ghidra/test/processors/Hexagon_O0_EmulatorTest.java new file mode 100644 index 0000000000..6cb710cfeb --- /dev/null +++ b/Ghidra/Processors/Hexagon/src/test.processors/java/ghidra/test/processors/Hexagon_O0_EmulatorTest.java @@ -0,0 +1,74 @@ +/* ### + * IP: GHIDRA + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +package ghidra.test.processors; + +import ghidra.program.model.listing.Program; +import ghidra.program.model.symbol.Symbol; +import ghidra.program.model.symbol.SymbolUtilities; +import ghidra.test.processors.support.EmulatorTestRunner; +import ghidra.test.processors.support.ProcessorEmulatorTestAdapter; +import junit.framework.Test; + +public class Hexagon_O0_EmulatorTest extends ProcessorEmulatorTestAdapter { + + /** + * Known Failures: + * - All nalign_i2,4,8 tests are known to fail since the llvm compiler for Hexagon + * produces code which handles reads and writes inconsistently and does not + * attempt to force use of byte read/write for non-aligned accesses. The processor + * H/W will throw an exception for unaligned accesses. + */ + + private static final String LANGUAGE_ID = "Hexagon:LE:32:default"; + private static final String COMPILER_SPEC_ID = "default"; + + private static final String[] REG_DUMP_SET = new String[] {}; + + public Hexagon_O0_EmulatorTest(String name) throws Exception { + super(name, LANGUAGE_ID, COMPILER_SPEC_ID, REG_DUMP_SET); + + // Ignore known issues with alignment tests + addIgnoredTests( + // Alignment tests need to declare the char array with proper alignment + // since Hexagon will access char array in a char-aligned fashion for + // the various size. + "nalign_i2_Main", + "nalign_i4_Main", + "nalign_i8_Main"); + } + + @Override + protected void initializeState(EmulatorTestRunner testRunner, Program program) + throws Exception { + super.initializeState(testRunner, program); + testRunner.setRegister("SP", 0x40000000L); // stack, unused location + Symbol globalDataSym = SymbolUtilities.getLabelOrFunctionSymbol(program, "GLOBAL", + m -> { + /* ignore */ }); + assertNotNull("GLOBAL data symbol not found", globalDataSym); + testRunner.setRegister("GP", globalDataSym.getAddress().getOffset()); + } + + @Override + protected String getProcessorDesignator() { + return "Hexagon_CLANG_LLVM_O0"; + } + + public static Test suite() { + return ProcessorEmulatorTestAdapter + .buildEmulatorTestSuite(Hexagon_O0_EmulatorTest.class); + } +} diff --git a/Ghidra/Processors/Hexagon/src/test.processors/java/ghidra/test/processors/Hexagon_O3_EmulatorTest.java b/Ghidra/Processors/Hexagon/src/test.processors/java/ghidra/test/processors/Hexagon_O3_EmulatorTest.java new file mode 100644 index 0000000000..d76b6dc95f --- /dev/null +++ b/Ghidra/Processors/Hexagon/src/test.processors/java/ghidra/test/processors/Hexagon_O3_EmulatorTest.java @@ -0,0 +1,62 @@ +/* ### + * IP: GHIDRA + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +package ghidra.test.processors; + +import ghidra.program.model.listing.Program; +import ghidra.program.model.symbol.Symbol; +import ghidra.program.model.symbol.SymbolUtilities; +import ghidra.test.processors.support.EmulatorTestRunner; +import ghidra.test.processors.support.ProcessorEmulatorTestAdapter; +import junit.framework.Test; + +public class Hexagon_O3_EmulatorTest extends ProcessorEmulatorTestAdapter { + + private static final String LANGUAGE_ID = "Hexagon:LE:32:default"; + private static final String COMPILER_SPEC_ID = "default"; + + private static final String[] REG_DUMP_SET = new String[] {}; + + public Hexagon_O3_EmulatorTest(String name) throws Exception { + super(name, LANGUAGE_ID, COMPILER_SPEC_ID, REG_DUMP_SET); + + addIgnoredTests( + // Hexagon Tools 8.5.10 LLVM compiler produces incorrect O3 optimized do/while loop code + "pcode_RolledDoWhileLoop_Main", + "pcode_Unrolled2DoWhileLoop_Main"); + } + + @Override + protected void initializeState(EmulatorTestRunner testRunner, Program program) + throws Exception { + super.initializeState(testRunner, program); + testRunner.setRegister("SP", 0x40000000L); // stack, unused location + Symbol globalDataSym = SymbolUtilities.getLabelOrFunctionSymbol(program, "GLOBAL", + m -> { + /* ignore */ }); + assertNotNull("GLOBAL data symbol not found", globalDataSym); + testRunner.setRegister("GP", globalDataSym.getAddress().getOffset()); + } + + @Override + protected String getProcessorDesignator() { + return "Hexagon_CLANG_LLVM_O3"; + } + + public static Test suite() { + return ProcessorEmulatorTestAdapter + .buildEmulatorTestSuite(Hexagon_O3_EmulatorTest.class); + } +} diff --git a/Ghidra/Processors/Hexagon/src/test/java/ghidra/app/plugin/assembler/sleigh/HexagonAssemblyTest.java b/Ghidra/Processors/Hexagon/src/test/java/ghidra/app/plugin/assembler/sleigh/HexagonAssemblyTest.java new file mode 100644 index 0000000000..231c7453d0 --- /dev/null +++ b/Ghidra/Processors/Hexagon/src/test/java/ghidra/app/plugin/assembler/sleigh/HexagonAssemblyTest.java @@ -0,0 +1,70 @@ +/* ### + * IP: GHIDRA + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +package ghidra.app.plugin.assembler.sleigh; + +import java.math.BigInteger; + +import org.junit.Test; + +import ghidra.app.plugin.assembler.sleigh.sem.AssemblyPatternBlock; +import ghidra.program.model.lang.LanguageID; +import ghidra.program.model.lang.RegisterValue; + +public class HexagonAssemblyTest extends AbstractAssemblyTest { + + @Override + protected LanguageID getLanguageID() { + return new LanguageID("Hexagon:LE:32:default"); + } + + String makeCtx(int packetOffset, long packetBits) { + RegisterValue ctxVal = new RegisterValue(lang.getContextBaseRegister()); + ctxVal = ctxVal.assign(lang.getRegister("packetOffset"), BigInteger.valueOf(packetOffset)); + ctxVal = ctxVal.assign(lang.getRegister("packetBits"), BigInteger.valueOf(packetBits)); + return AssemblyPatternBlock.fromRegisterValue(ctxVal).fillMask().toString(); + } + + @Test + public void testAssemble_memb_R0_mR1() { + assertOneCompatRestExact("memb R0,(R1)", "00:40:01:91", 0x000c0000); + } + + @Test + public void testAssemble_jump_if_t_cmp_eq_mR0new_n0_0xc0010() { + assertOneCompatRestExact("jump.if:t cmp.eq(R0.new,#0x0),0x000c0010", "0b:e0:02:24", + makeCtx(1, 0x40000000), 0x000c0000, + "jump.if:t cmp.eq(R0.new,#0x0),0x000c0010"); + } + + @Test + public void testAssemble_assign_R0_P0() { + assertOneCompatRestExact("assign R0,P0", "00:40:40:89", 0x000c0000); + } + + @Test + public void testAssemble_cmp_gtu_P0_R1_n0x9__jump_if_P0new_t_0xc0010() { + assertOneCompatRestExact("cmp.gtu P0,R1,#0x9 ; jump.if(P0.new):t 0x000c0010", "0b:69:01:11", + makeCtx(1, 0x40000000), 0x000c0000, + "cmp.gtu P0,R1,#0x9 ; jump.if(P0.new):t 0x000c0010"); + } + + @Test + public void testAssemble_memw_mSP_n0x4_R0new() { + assertOneCompatRestExact("memw (SP+#0x4),R0.new", "01:d4:bd:a1", + makeCtx(2, 0x50000000), 0x000c0000, + "memw (SP+#0x4),R0.new"); + } +} diff --git a/Ghidra/Processors/Hexagon/src/test/java/ghidra/program/emulation/HexagonPcodeUseropLibraryTest.java b/Ghidra/Processors/Hexagon/src/test/java/ghidra/program/emulation/HexagonPcodeUseropLibraryTest.java new file mode 100644 index 0000000000..8778b81e74 --- /dev/null +++ b/Ghidra/Processors/Hexagon/src/test/java/ghidra/program/emulation/HexagonPcodeUseropLibraryTest.java @@ -0,0 +1,237 @@ +/* ### + * IP: GHIDRA + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +package ghidra.program.emulation; + +import static org.hamcrest.MatcherAssert.assertThat; +import static org.junit.Assert.assertNotNull; + +import java.util.Map; + +import org.hamcrest.Matchers; +import org.junit.*; + +import ghidra.app.plugin.processors.sleigh.SleighLanguage; +import ghidra.pcode.exec.*; +import ghidra.program.emulation.HexagonPcodeUseropLibraryFactory.HexagonPcodeUseropLibrary; +import ghidra.program.model.lang.LanguageID; +import ghidra.program.util.DefaultLanguageService; + +public class HexagonPcodeUseropLibraryTest extends AbstractEmulationEquivalenceTest { + static final LanguageID LANGI_ID_HEXAGON = new LanguageID("Hexagon:LE:32:default"); + + static SleighLanguage HEXAGON; + + @Before + public void setupHexagon() throws Exception { + if (HEXAGON == null) { + HEXAGON = (SleighLanguage) DefaultLanguageService.getLanguageService() + .getLanguage(LANGI_ID_HEXAGON); + } + } + + @Test + public void testFoundById() { + PcodeUseropLibrary lib = PcodeUseropLibraryFactory + .createUseropLibraryFromId("hexagon", HEXAGON, + BytesPcodeArithmetic.forLanguage(HEXAGON)); + assertThat(lib, Matchers.instanceOf(HexagonPcodeUseropLibrary.class)); + } + + @Test + public void testFoundByLang() { + PcodeUseropLibrary lib = PcodeUseropLibraryFactory + .createUseropLibraryForLanguage(HEXAGON, BytesPcodeArithmetic.forLanguage(HEXAGON)); + assertNotNull(lib.getUserops().get("dfmpyfix")); + assertNotNull(lib.getUserops().get("dfmpyhh")); + } + + @Test + public void testDfClass() throws Exception { + doTestEquiv(HEXAGON, + Map.ofEntries( + Map.entry("P3", "ffff"), // Kind of hacky, but Pd2 &= result + Map.entry("R1R0", "3ff0000000000000")), + buf -> buf.assemble("dfclass P3,R1R0,#0x2"), 1, + Map.ofEntries( + Map.entry("P3", "ff"), + Map.entry("PC", "400004"), + Map.entry("P0.new", "ff"), + Map.entry("P1.new", "ff"), + Map.entry("P2.new", "ff"), + Map.entry("P3.new", "ff"), + Map.entry("R1R0", "3ff0000000000000"))); + } + + @Test + public void testVMux() throws Exception { + doTestEquiv(HEXAGON, + Map.ofEntries( + Map.entry("P0", "96"), + Map.entry("R1R0", "aaaaaaaaaaaaaaaa"), + Map.entry("R9R8", "bbbbbbbbbbbbbbbb")), + buf -> buf.assemble("vmux R1R0,P0,R1R0,R9R8"), 1, + Map.ofEntries( + Map.entry("R1R0_", "aabbbbaabbaaaabb"), + Map.entry("P0", "96"), + Map.entry("PC", "400004"), + Map.entry("P0.new", "ff"), + Map.entry("P1.new", "ff"), + Map.entry("P2.new", "ff"), + Map.entry("P3.new", "ff"), + Map.entry("R1R0", "aaaaaaaaaaaaaaaa"), + Map.entry("R9R8", "bbbbbbbbbbbbbbbb"))); + } + + static final long DF_ANY = 0x3f80_0000_0000_0000L; + static final long DF_HEX_NAN = -1L; + static final long DF_MAX = Double.doubleToRawLongBits(Double.MAX_VALUE); + static final long DF_MIN = Double.doubleToRawLongBits(Double.MIN_NORMAL); + static final long DF_NEG_ONE = Double.doubleToRawLongBits(-1.0); + static final long DF_NEG_ZERO = Double.doubleToRawLongBits(-0.0); + static final long DF_ONE = Double.doubleToRawLongBits(1.0); + static final long DF_ONE_HH = 0x3ff0_01ff_8000_0000L; + static final long DF_QNAN = 0x7ff8_0000_0000_0000L; + static final long DF_SNAN = 0x7ff7_0000_0000_0000L; + static final long DF_ZERO = Double.doubleToRawLongBits(0.0); + + protected void runTestDfmpyhh(long accNew, long accInit, long a, long b) + throws Exception { + doTestEquiv(HEXAGON, + Map.ofEntries( + Map.entry("R1R0", Long.toHexString(accInit)), + Map.entry("R3R2", Long.toHexString(a)), + Map.entry("R9R8", Long.toHexString(b))), + buf -> buf.assemble("dfmpyhh+= R1R0,R3R2,R9R8"), 1, + Map.ofEntries( + Map.entry("R1R0_", Long.toHexString(accNew)), + Map.entry("PC", "400004"), + Map.entry("P0.new", "ff"), + Map.entry("P1.new", "ff"), + Map.entry("P2.new", "ff"), + Map.entry("P3.new", "ff"), + Map.entry("R1R0", Long.toHexString(accInit)), + Map.entry("R3R2", Long.toHexString(a)), + Map.entry("R9R8", Long.toHexString(b)))); + } + + protected void runTestDfmpylh(long accNew, long accInit, long a, long b) + throws Exception { + doTestEquiv(HEXAGON, + Map.ofEntries( + Map.entry("R1R0", Long.toHexString(accInit)), + Map.entry("R3R2", Long.toHexString(a)), + Map.entry("R9R8", Long.toHexString(b))), + buf -> buf.assemble("dfmpylh+= R1R0,R3R2,R9R8"), 1, + Map.ofEntries( + Map.entry("R1R0_", Long.toHexString(accNew)), + Map.entry("PC", "400004"), + Map.entry("P0.new", "ff"), + Map.entry("P1.new", "ff"), + Map.entry("P2.new", "ff"), + Map.entry("P3.new", "ff"), + Map.entry("R1R0", Long.toHexString(accInit)), + Map.entry("R3R2", Long.toHexString(a)), + Map.entry("R9R8", Long.toHexString(b)))); + } + + protected void runTestDfmpyll(long accNew, long accInit, long a, long b) + throws Exception { + doTestEquiv(HEXAGON, + Map.ofEntries( + Map.entry("R1R0", Long.toHexString(accInit)), + Map.entry("R3R2", Long.toHexString(a)), + Map.entry("R9R8", Long.toHexString(b))), + buf -> buf.assemble("dfmpyll R1R0,R3R2,R9R8"), 1, + Map.ofEntries( + Map.entry("R1R0_", Long.toHexString(accNew)), + Map.entry("PC", "400004"), + Map.entry("P0.new", "ff"), + Map.entry("P1.new", "ff"), + Map.entry("P2.new", "ff"), + Map.entry("P3.new", "ff"), + Map.entry("R1R0", Long.toHexString(accInit)), + Map.entry("R3R2", Long.toHexString(a)), + Map.entry("R9R8", Long.toHexString(b)))); + } + + @Test + public void testDfmpyhhOnes() throws Exception { + runTestDfmpyhh(DF_ONE_HH, DF_ONE, DF_ONE, DF_ONE); + } + + @Test + @Ignore + public void testDfmpyhhZeroAnyQNan() throws Exception { + runTestDfmpyhh(DF_HEX_NAN, DF_ZERO, DF_ANY, DF_QNAN); + } + + @Test + @Ignore + public void testDfmpyhhZeroAnySNan() throws Exception { + runTestDfmpyhh(DF_HEX_NAN, DF_ZERO, DF_ANY, DF_SNAN); + } + + @Test + @Ignore + public void testDfmpyhhZeroQNanSNan() throws Exception { + runTestDfmpyhh(DF_HEX_NAN, DF_ZERO, DF_QNAN, DF_SNAN); + } + + @Test + @Ignore + public void testDfmpyhhZeroSNanQNan() throws Exception { + runTestDfmpyhh(DF_HEX_NAN, DF_ZERO, DF_SNAN, DF_QNAN); + } + + @Test + public void testDfmpyhhMain() throws Exception { + runTestDfmpyhh( + 0x4023_b81d_7dbf_4880L, + 0x0020_2752_200f_06f7L, + 0x4009_1eb8_51eb_851fL, + 0x4009_1eb8_51eb_851fL); + } + + @Test + public void testDfmpylhMins() throws Exception { + runTestDfmpylh(0x10_0000_0000_0000L, DF_MIN, DF_MIN, DF_MIN); + } + + @Test + public void testDfmpylhNegOneMaxMin() throws Exception { + runTestDfmpylh(0xc00f_ffff_ffe0_0000L, DF_NEG_ONE, DF_MAX, DF_MIN); + } + + @Test + public void testDfmpylhMaxZeroNegOne() throws Exception { + runTestDfmpylh(0x7fef_ffff_ffff_ffffL, DF_MAX, DF_ZERO, DF_NEG_ONE); + } + + @Test + public void testDfmpyllMins() throws Exception { + runTestDfmpyll(0, -1L, DF_MIN, DF_MIN); + } + + @Test + public void testDfmpyllNegOneMin() throws Exception { + runTestDfmpyll(0, -1L, DF_NEG_ONE, DF_MIN); + } + + @Test + public void testDfmpyllMaxes() throws Exception { + runTestDfmpyll(0x1_ffff_fffdL, -1L, DF_MAX, DF_MAX); + } +} diff --git a/Ghidra/Test/IntegrationTest/src/test.slow/java/ghidra/program/model/pcode/PcodeEmitContextCrossBuildTest.java b/Ghidra/Test/IntegrationTest/src/test.slow/java/ghidra/program/model/pcode/PcodeEmitContextCrossBuildTest.java new file mode 100644 index 0000000000..74575d1b79 --- /dev/null +++ b/Ghidra/Test/IntegrationTest/src/test.slow/java/ghidra/program/model/pcode/PcodeEmitContextCrossBuildTest.java @@ -0,0 +1,906 @@ +/* ### + * IP: GHIDRA + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +package ghidra.program.model.pcode; + +import static org.junit.Assert.*; + +import org.apache.commons.lang3.StringUtils; +import org.junit.*; + +import ghidra.app.plugin.processors.sleigh.SleighLanguage; +import ghidra.program.database.ProgramBuilder; +import ghidra.program.model.address.Address; +import ghidra.program.model.address.AddressSpace; +import ghidra.program.model.lang.ParallelInstructionLanguageHelper; +import ghidra.program.model.listing.*; +import ghidra.program.model.symbol.*; +import ghidra.test.AbstractProgramBasedTest; + +public class PcodeEmitContextCrossBuildTest extends AbstractProgramBasedTest { + private ProgramBuilder builder; + private Address baseAddr; + private AddressSpace defaultSpace; + private Listing listing; + private SleighLanguage language; + private Address testUniqueInCrossbuildAddr; + private Address testCallotherOverrideSingletonPacketAddr; + private ParallelInstructionLanguageHelper parallelHelper; + private ReferenceManager refManager; + private Address func1Addr; + private Address testCallotherOverrideCrossbuildAddr; + private Address func2Addr; + private Address testFallthroughOverrideTerminalAddr; + private Address testFallthroughOverrideMidPacketAddr; + private Address testFlowOverrideSingletonCallAddr; + private Address testFlowOverrideCallInPacketAddr; + private Address testUniqueSubpieceAddr; + private Address testRegisterSubpieceAddr; + + private static final int ASL_PLUS_INSTANCES = 16; + + //singleton instruction packet whose pcode has exactly one varnode in the unique space + private static final String ASL_PLUS_TERMINAL_BYTES = "c0 c0 01 8e "; + + // example of lower SUBPIECE use on unique + private static final String VASRW_BYTES = "44 c2 00 c5"; + + // example of lower SUBPIECE use on register + private static final String BOUNDSCHECK_BYTES = "a1 e2 02 d2"; + + private static final String ADDSAT_NON_TERMINAL_BYTES = "80 40 00 d5 "; + + private static final String MEMW_LOCKED_NON_TERMINAL_BYTES = "00 42 b0 a0 "; + + private static final String MEMW_LOCKED_TERMINAL_BYTES = "00 c2 b0 a0 "; + + private static final String CALL_TERMINAL_BYTES = "c6 c7 00 5a "; + + private static final String CALL_NON_TERMINAL_BYTES = "c4 47 00 5a "; + + private static final String BASE_ADDRESS = "0x100000"; + + private static final String DEST_FUNC1_ADDR = "0x101000"; + + private static final String DEST_FUNC2_ADDR = "0x102000"; + + @Before + public void setup() throws Exception { + buildProgram(); + initialize(); + } + + @Override + @After + public void tearDown() throws Exception { + env.dispose(); + builder.dispose(); + } + + @Override + public Program getProgram() { + return program; + } + + private void buildProgram() throws Exception { + builder = new ProgramBuilder("crossbuildEmitTest", "Hexagon:LE:32:default"); + builder.createMemory(".text", BASE_ADDRESS, 0x10000); + builder.createEmptyFunction("func1", DEST_FUNC1_ADDR, 4, null); + builder.createEmptyFunction("func2", DEST_FUNC2_ADDR, 4, null); + + //testUniqueAddresses + StringBuilder sb = new StringBuilder(); + for (int i = 0; i < ASL_PLUS_INSTANCES; i++) { + sb.append(ASL_PLUS_TERMINAL_BYTES); + } + + //testUniqueInCrossbuild + sb.append(ASL_PLUS_TERMINAL_BYTES); + sb.append(ADDSAT_NON_TERMINAL_BYTES); + sb.append(ASL_PLUS_TERMINAL_BYTES); + + //testCallotherOverrideSingletonPacket + sb.append(MEMW_LOCKED_TERMINAL_BYTES); + + //testCallotherOverrideCrossbuild + sb.append(MEMW_LOCKED_NON_TERMINAL_BYTES); + sb.append(ASL_PLUS_TERMINAL_BYTES); + + //testFallthroughOverrideTerminal + sb.append(ASL_PLUS_TERMINAL_BYTES); + sb.append(ASL_PLUS_TERMINAL_BYTES); + sb.append(ASL_PLUS_TERMINAL_BYTES); + + //testFallthroughOverrideMidPacket + sb.append(MEMW_LOCKED_NON_TERMINAL_BYTES); + sb.append(ADDSAT_NON_TERMINAL_BYTES); + sb.append(ASL_PLUS_TERMINAL_BYTES); + sb.append(ASL_PLUS_TERMINAL_BYTES); + + //testFlowOverrideSingleCall + sb.append(CALL_TERMINAL_BYTES); + + //testFlowOverrideCallInPacket + //testSimpleCallReferenceOverride + sb.append(CALL_NON_TERMINAL_BYTES); + sb.append(ASL_PLUS_TERMINAL_BYTES); + + // testUniqueSubpiece (access directly at sub-offset of unique varnode) + sb.append(VASRW_BYTES); + + // testRegisterSubpiece + sb.append(BOUNDSCHECK_BYTES); + + String byteString = sb.toString().trim(); + builder.setBytes(BASE_ADDRESS, byteString); + int byteLength = (byteString.length() - StringUtils.countMatches(byteString, ' ')) / 2; + + builder.disassemble(BASE_ADDRESS, byteLength, false); + program = builder.getProgram(); + defaultSpace = program.getAddressFactory().getDefaultAddressSpace(); + baseAddr = defaultSpace.getAddress(BASE_ADDRESS); + testUniqueInCrossbuildAddr = baseAddr.add(ASL_PLUS_INSTANCES * 4); + testCallotherOverrideSingletonPacketAddr = testUniqueInCrossbuildAddr.add(12); + listing = program.getListing(); + language = (SleighLanguage) program.getLanguage(); + parallelHelper = language.getParallelInstructionHelper(); + refManager = program.getReferenceManager(); + func1Addr = defaultSpace.getAddress(DEST_FUNC1_ADDR); + testCallotherOverrideCrossbuildAddr = testCallotherOverrideSingletonPacketAddr.add(4); + func2Addr = defaultSpace.getAddress(DEST_FUNC2_ADDR); + testFallthroughOverrideTerminalAddr = testCallotherOverrideCrossbuildAddr.add(8); + testFallthroughOverrideMidPacketAddr = testFallthroughOverrideTerminalAddr.add(12); + testFlowOverrideSingletonCallAddr = testFallthroughOverrideMidPacketAddr.add(16); + testFlowOverrideCallInPacketAddr = testFlowOverrideSingletonCallAddr.add(4); + testUniqueSubpieceAddr = testFlowOverrideCallInPacketAddr.add(8); + testRegisterSubpieceAddr = testUniqueSubpieceAddr.add(4); + } + + /** + * Test that offsets of varnodes in the unique space are adjusted based on + * the unique allocation mask of the language and the address of an + * instruction. + * + 00100000 c0 c0 01 8e asl+= R0,R1,#0x0 + 00100004 c0 c0 01 8e asl+= R0,R1,#0x0 + 00100008 c0 c0 01 8e asl+= R0,R1,#0x0 + 0010000c c0 c0 01 8e asl+= R0,R1,#0x0 + 00100010 c0 c0 01 8e asl+= R0,R1,#0x0 + 00100014 c0 c0 01 8e asl+= R0,R1,#0x0 + 00100018 c0 c0 01 8e asl+= R0,R1,#0x0 + 0010001c c0 c0 01 8e asl+= R0,R1,#0x0 + 00100020 c0 c0 01 8e asl+= R0,R1,#0x0 + 00100024 c0 c0 01 8e asl+= R0,R1,#0x0 + 00100028 c0 c0 01 8e asl+= R0,R1,#0x0 + 0010002c c0 c0 01 8e asl+= R0,R1,#0x0 + 00100030 c0 c0 01 8e asl+= R0,R1,#0x0 + 00100034 c0 c0 01 8e asl+= R0,R1,#0x0 + 00100038 c0 c0 01 8e asl+= R0,R1,#0x0 + 0010003c c0 c0 01 8e asl+= R0,R1,#0x0 + */ + @Test + public void testUniqueAddresses() { + int uniqueMask = language.getUniqueAllocationMask(); + assertEquals(0xff, uniqueMask); + for (int i = 0; i < ASL_PLUS_INSTANCES; ++i) { + //verify the test instruction + Instruction inst = listing.getInstructionAt(baseAddr.add(4 * i)); + assertNotNull(inst); + assertEquals("asl+= R0,R1,#0x0", inst.toString().trim()); + assertFalse(parallelHelper.isParallelInstruction(inst)); + assertTrue(parallelHelper.isEndOfParallelInstructionGroup(inst)); + PcodeOp[] ops = inst.getPcode(); + assertEquals(8, ops.length); + + //verify the op with output in the unique space + PcodeOp shift = ops[4]; + assertEquals(PcodeOp.INT_LEFT, shift.getOpcode()); + Varnode shiftOut = shift.getOutput(); + assertNotNull(shiftOut); + assertTrue(shiftOut.isUnique()); + + //verify that the address in the unique space has the adjustment + //or'd in + long actualOffset = shiftOut.getOffset(); + long adjustment = (inst.getAddress().getOffset() & uniqueMask) << 8; + if (i == 0) { + assertTrue(adjustment == 0); + } + else { + assertTrue(adjustment != 0); + } + assertEquals(actualOffset, actualOffset | adjustment); + } + } + + /** + * Tests that a unique defined in the main section of an instruction and used in a named + * section is correctly referenced in the pcode of a separate instruction that crossbuilds the + * named section. + * + 00100040 c0 c0 01 8e asl+= R0,R1,#0x0 + 00100044 80 40 00 d5 add:sat R0,R0.L,R0.L + 00100048 c0 c0 01 8e || asl+= R0,R1,#0x0 + */ + @Test + public void testUniqueInCrossbuild() { + //verify the instructions used in the test + Instruction aslSingleton = listing.getInstructionAt(testUniqueInCrossbuildAddr); + Instruction addSat = listing.getInstructionAt(testUniqueInCrossbuildAddr.add(4)); + Instruction aslPacket = listing.getInstructionAt(testUniqueInCrossbuildAddr.add(8)); + assertNotNull(aslSingleton); + assertEquals("asl+= R0,R1,#0x0", aslSingleton.toString().trim()); + assertFalse(parallelHelper.isParallelInstruction(aslSingleton)); + assertTrue(parallelHelper.isEndOfParallelInstructionGroup(aslSingleton)); + assertNotNull(addSat); + assertEquals("add:sat R0,R0.L,R0.L", addSat.toString().trim()); + assertFalse(parallelHelper.isParallelInstruction(addSat)); + assertFalse(parallelHelper.isEndOfParallelInstructionGroup(addSat)); + assertNotNull(aslPacket); + assertEquals("asl+= R0,R1,#0x0", aslPacket.toString().trim()); + assertTrue(parallelHelper.isParallelInstruction(aslPacket)); + assertTrue(parallelHelper.isEndOfParallelInstructionGroup(aslPacket)); + + //grab the unique varnode which is the output of the SCARRY op in addSat + long uniqueOffset = -1; + long uniqueSize = 0; + for (PcodeOp op : addSat.getPcode()) { + if (op.getOpcode() == PcodeOp.INT_SCARRY) { + Varnode uniqueOut = op.getOutput(); + assertTrue(uniqueOut.isUnique()); + uniqueOffset = uniqueOut.getOffset(); + uniqueSize = uniqueOut.getSize(); + break; + } + } + //verify that we found the INT_SCARRY op + assertFalse(uniqueOffset == -1); + + //verify that this varnode is an input to an op in the pcode for aslPacket + boolean foundIt = false; + for (PcodeOp op : aslPacket.getPcode()) { + if (op.getOpcode() == PcodeOp.INT_OR) { + Varnode uniqueIn = op.getInput(1); + assertTrue(uniqueIn.isUnique()); + assertEquals(uniqueOffset, uniqueIn.getOffset()); + assertEquals(uniqueSize, uniqueIn.getSize()); + foundIt = true; + break; + } + } + assertTrue(foundIt); + + //verify that the singleton asl instruction does not have an INT_OR op + //(so the INT_OR op must have come from a crossbuild from the add:sat instruction) + foundIt = false; + for (PcodeOp op : aslSingleton.getPcode()) { + if (op.getOpcode() == PcodeOp.INT_OR) { + foundIt = true; + } + } + assertFalse(foundIt); + } + + /** + * Tests that a unique lower-subpiece (LE) on a COPY directly access the smaller portion + * of the unique varnode. + * + 00100080 44 c2 00 c5 vasrw R4,R1R0,R2 + */ + @Test + public void testUniqueSubpiece() { + + // NOTE: Really need big-endian language to fully test + + //verify the instructions used in the test + Instruction vasrwSingleton = listing.getInstructionAt(testUniqueSubpieceAddr); + assertNotNull(vasrwSingleton); + assertEquals("vasrw R4,R1R0,R2", vasrwSingleton.toString().trim()); + assertFalse(parallelHelper.isParallelInstruction(vasrwSingleton)); + assertTrue(parallelHelper.isEndOfParallelInstructionGroup(vasrwSingleton)); + + //grab the unique varnode which is the input of the SCARRY op in addSat + long uniqueOffset = -1; + long uniqueSize = 0; + boolean foundIt = false; + for (PcodeOp op : vasrwSingleton.getPcode()) { + if (op.getOpcode() == PcodeOp.INT_ADD) { + Varnode uniqueOut = op.getOutput(); + assertTrue(uniqueOut.isUnique()); + uniqueOffset = uniqueOut.getOffset(); + assertEquals(0, uniqueOffset & 0x7f); + uniqueSize = uniqueOut.getSize(); + assertEquals(4, uniqueSize); + } + else if (uniqueOffset != -1 && op.getOpcode() == PcodeOp.COPY) { + Varnode uniqueIn = op.getInputs()[0]; + assertTrue(uniqueIn.isUnique()); + assertEquals(uniqueOffset, uniqueIn.getOffset()); + assertEquals(2, uniqueIn.getSize()); + foundIt = true; + break; + } + } + //verify that we found the INT_ADD and COPY ops + assertFalse(uniqueOffset == -1); + assertTrue(foundIt); + } + + /** + * Tests that a register lower-subpiece (LE) on uses the SUBPIECE op properly + * + 00100084 a1 e2 02 d2 boundscheck:raw:hi P1,R3R2,R3R2 + */ + @Test + public void testRegisterSubpiece() { + + // NOTE: Really need big-endian language to fully test + + //verify the instructions used in the test + Instruction boundscheckSingleton = listing.getInstructionAt(testRegisterSubpieceAddr); + assertNotNull(boundscheckSingleton); + assertEquals("boundscheck:raw:hi P1,R3R2,R3R2", boundscheckSingleton.toString().trim()); + assertFalse(parallelHelper.isParallelInstruction(boundscheckSingleton)); + assertTrue(parallelHelper.isEndOfParallelInstructionGroup(boundscheckSingleton)); + + //grab the unique varnode which is the input of the SCARRY op in addSat + long uniqueOffset = -1; + long uniqueSize = 0; + boolean foundIt = false; + for (PcodeOp op : boundscheckSingleton.getPcode()) { + if (op.getOpcode() == PcodeOp.SUBPIECE) { + + // Check output + Varnode uniqueOut = op.getOutput(); + assertTrue(uniqueOut.isUnique()); + uniqueOffset = uniqueOut.getOffset(); + assertEquals(0, uniqueOffset & 0x7f); + uniqueSize = uniqueOut.getSize(); + assertEquals(4, uniqueSize); + + // Check inputs + Varnode[] inputs = op.getInputs(); + assertTrue(inputs[0].isRegister()); + assertEquals(8, inputs[0].getOffset()); + assertEquals(8, inputs[0].getSize()); + assertTrue(inputs[1].isConstant()); + assertEquals(4, inputs[1].getOffset()); + assertEquals(4, inputs[1].getSize()); + foundIt = true; + break; + } + } + //verify that we found the SUBPIECE op + assertFalse(uniqueOffset == -1); + assertTrue(foundIt); + } + + /** + * Verify that a CALLOTHER_OVERRIDE_CALL reference modifies the + * first CALLOTHER op in a singleton instruction packet + * + 0010004c 00 c2 b0 a0 memw_loc (R16,P0),R2 + */ + @Test + public void testCallotherOverrideSingletonPacket() { + //verify the instruction used in the test + Instruction memw_locked_last = + listing.getInstructionAt(testCallotherOverrideSingletonPacketAddr); + assertNotNull(memw_locked_last); + assertEquals("memw_locked (R16,P0),R2", memw_locked_last.toString().trim()); + assertTrue(parallelHelper.isEndOfParallelInstructionGroup(memw_locked_last)); + + //verify that the pcode from the instruction doesn't change if you + //request overrides + PcodeOp[] memw_locked_last_original = memw_locked_last.getPcode(); + assertTrue(PcodeEmitContextTest.equalPcodeOpArrays(memw_locked_last_original, + memw_locked_last.getPcode(false))); + assertTrue(PcodeEmitContextTest.equalPcodeOpArrays(memw_locked_last_original, + memw_locked_last.getPcode(true))); + + //apply a CALLOTHER_OVERRIDE_CALL reference + int id = program.startTransaction("test"); + Reference overrideRef = + refManager.addMemoryReference(testCallotherOverrideSingletonPacketAddr, func1Addr, + RefType.CALLOTHER_OVERRIDE_CALL, SourceType.USER_DEFINED, -1); + refManager.setPrimary(overrideRef, true); + program.endTransaction(id, true); + + //verify that the pcode doesn't change if you request no overrides + assertTrue(PcodeEmitContextTest.equalPcodeOpArrays(memw_locked_last_original, + memw_locked_last.getPcode())); + assertTrue(PcodeEmitContextTest.equalPcodeOpArrays(memw_locked_last_original, + memw_locked_last.getPcode(false))); + + //verify that the first CALLOTHER op is changed to a CALL if you request overrides + PcodeOp[] memw_locked_last_overridden = memw_locked_last.getPcode(true); + assertEquals(memw_locked_last_original.length, memw_locked_last_overridden.length); + assertEquals(14, memw_locked_last_overridden.length); + for (int i = 0; i < 14; ++i) { + PcodeOp orig = memw_locked_last_original[i]; + PcodeOp overridden = memw_locked_last_overridden[i]; + if (i == 4) { + assertEquals(PcodeOp.CALLOTHER, orig.getOpcode()); + assertEquals(PcodeOp.CALL, overridden.getOpcode()); + } + else { + if (i == 12) { + //just to document that a second CALLOTHER op exists (and is unchanged) + assertEquals(PcodeOp.CALLOTHER, overridden.getOpcode()); + } + assertTrue(PcodeEmitContextTest.equalPcodeOps(orig, overridden)); + } + } + } + + /** + * Tests applying CALLOTHER_OVERRIDE_CALL references to an instruction with two CALLOTHER + * ops, one in the main section and another in a named section. When this instruction is + * part of a packet, placing an overriding reference on the address corresponding to the + * main section will override the first (main) CALLOTHER, and placing a reference on the + * (separate) address corresponding to the named section will override the second CALLOTHER. + * + 00100050 00 42 b0 a0 memw_loc (R16,P0),R2 + 00100054 c0 c0 01 8e || asl+= R0,R1,#0x0 + * + */ + @Test + public void testCallotherOverrideCrossbuild() { + //verify the instructions used for the test + Instruction memw_locked_nonterminal = + listing.getInstructionAt(testCallotherOverrideCrossbuildAddr); + Instruction asl_plus_last = + listing.getInstructionAfter(testCallotherOverrideCrossbuildAddr); + assertNotNull(memw_locked_nonterminal); + assertEquals("memw_locked (R16,P0),R2", memw_locked_nonterminal.toString().trim()); + assertFalse(parallelHelper.isParallelInstruction(memw_locked_nonterminal)); + assertFalse(parallelHelper.isEndOfParallelInstructionGroup(memw_locked_nonterminal)); + assertNotNull(asl_plus_last); + assertEquals("asl+= R0,R1,#0x0", asl_plus_last.toString().trim()); + assertTrue(parallelHelper.isParallelInstruction(asl_plus_last)); + assertTrue(parallelHelper.isEndOfParallelInstructionGroup(asl_plus_last)); + + //verify that the pcode is the same whether or not you ask for overrides + PcodeOp[] memw_unmod = memw_locked_nonterminal.getPcode(); + assertEquals(7, memw_unmod.length); + assertTrue(PcodeEmitContextTest.equalPcodeOpArrays(memw_unmod, + memw_locked_nonterminal.getPcode(false))); + assertTrue(PcodeEmitContextTest.equalPcodeOpArrays(memw_unmod, + memw_locked_nonterminal.getPcode(true))); + PcodeOp[] asl_plus_unmod = asl_plus_last.getPcode(); + assertTrue( + PcodeEmitContextTest.equalPcodeOpArrays(asl_plus_unmod, asl_plus_last.getPcode(false))); + assertTrue( + PcodeEmitContextTest.equalPcodeOpArrays(asl_plus_unmod, asl_plus_last.getPcode(true))); + + //apply override at the address of the main section + int id = program.startTransaction("test"); + Reference overrideRefMain = + refManager.addMemoryReference(memw_locked_nonterminal.getAddress(), func1Addr, + RefType.CALLOTHER_OVERRIDE_CALL, SourceType.USER_DEFINED, -1); + refManager.setPrimary(overrideRefMain, true); + program.endTransaction(id, true); + + //verify that the pcode does not change if you ask for no overrides + assertTrue(PcodeEmitContextTest.equalPcodeOpArrays(memw_unmod, + memw_locked_nonterminal.getPcode())); + assertTrue(PcodeEmitContextTest.equalPcodeOpArrays(memw_unmod, + memw_locked_nonterminal.getPcode(false))); + + //verify that the callother op in the main section is changed but in named section + //it is not + PcodeOp[] memw_mod = memw_locked_nonterminal.getPcode(true); + assertEquals(memw_unmod.length, memw_mod.length); + for (int i = 0; i < memw_unmod.length; ++i) { + if (i == 4) { + assertEquals(PcodeOp.CALL, memw_mod[i].getOpcode()); + assertEquals(func1Addr.getOffset(), memw_mod[i].getInput(0).getOffset()); + assertTrue(memw_mod[i].getInput(0).isAddress()); + assertEquals(PcodeOp.CALLOTHER, memw_unmod[i].getOpcode()); + } + else { + assertTrue(PcodeEmitContextTest.equalPcodeOps(memw_unmod[i], memw_mod[i])); + } + } + assertEquals(10, asl_plus_unmod.length); + assertTrue( + PcodeEmitContextTest.equalPcodeOpArrays(asl_plus_unmod, asl_plus_last.getPcode(false))); + assertTrue( + PcodeEmitContextTest.equalPcodeOpArrays(asl_plus_unmod, asl_plus_last.getPcode(true))); + + //apply a second override at the address of the named section + id = program.startTransaction("test"); + Reference overrideRefNamed = refManager.addMemoryReference(asl_plus_last.getAddress(), + func2Addr, RefType.CALLOTHER_OVERRIDE_CALL, SourceType.USER_DEFINED, -1); + refManager.setPrimary(overrideRefNamed, true); + program.endTransaction(id, true); + + //verify no changes if you request no overrides + assertTrue( + PcodeEmitContextTest.equalPcodeOpArrays(asl_plus_unmod, asl_plus_last.getPcode(false))); + assertTrue(PcodeEmitContextTest.equalPcodeOpArrays(memw_unmod, + memw_locked_nonterminal.getPcode(false))); + + //verify that both CALLOTHER ops are changed if you do request overrides + assertTrue(PcodeEmitContextTest.equalPcodeOpArrays(memw_mod, + memw_locked_nonterminal.getPcode(true))); + PcodeOp[] asl_plus_mod = asl_plus_last.getPcode(true); + assertEquals(asl_plus_unmod.length, asl_plus_mod.length); + for (int i = 0; i < asl_plus_unmod.length; ++i) { + if (i == 8) { + assertEquals(PcodeOp.CALLOTHER, asl_plus_unmod[i].getOpcode()); + assertEquals(PcodeOp.CALL, asl_plus_mod[i].getOpcode()); + assertEquals(func2Addr.getOffset(), asl_plus_mod[i].getInput(0).getOffset()); + assertTrue(asl_plus_mod[i].getInput(0).isAddress()); + } + else { + assertTrue(PcodeEmitContextTest.equalPcodeOps(asl_plus_unmod[i], asl_plus_mod[i])); + } + } + + //set the override at the address of the main section to non-primary + id = program.startTransaction("test"); + refManager.setPrimary(overrideRefMain, false); + program.endTransaction(id, true); + + //verify that the CALLOTHER in the main section is unchanged + assertTrue(PcodeEmitContextTest.equalPcodeOpArrays(memw_unmod, + memw_locked_nonterminal.getPcode())); + assertTrue(PcodeEmitContextTest.equalPcodeOpArrays(memw_unmod, + memw_locked_nonterminal.getPcode(false))); + assertTrue(PcodeEmitContextTest.equalPcodeOpArrays(memw_unmod, + memw_locked_nonterminal.getPcode(true))); + + //verify that the CALLOTHER op in the names section is unchanged if you + //request no overrides + assertTrue( + PcodeEmitContextTest.equalPcodeOpArrays(asl_plus_unmod, asl_plus_last.getPcode())); + assertTrue( + PcodeEmitContextTest.equalPcodeOpArrays(asl_plus_unmod, asl_plus_last.getPcode(false))); + + //verify the CALLOTHER op in the named section is changed if you request overrides + assertTrue( + PcodeEmitContextTest.equalPcodeOpArrays(asl_plus_mod, asl_plus_last.getPcode(true))); + } + + /** + * Tests that a fallthrough override applied to a singleton packet simply appends a + * BRANCH op. + * + 00100058 c0 c0 01 8e asl+= R0,R1,#0x0 + 0010005c c0 c0 01 8e asl+= R0,R1,#0x0 + 00100060 c0 c0 01 8e asl+= R0,R1,#0x0 + */ + @Test + public void testFallthroughOverrideTerminal() { + //verify the instruction used in the test + Instruction aslTerminal = listing.getInstructionAt(testFallthroughOverrideTerminalAddr); + assertNotNull(aslTerminal); + assertEquals("asl+= R0,R1,#0x0", aslTerminal.toString().trim()); + assertFalse(parallelHelper.isParallelInstruction(aslTerminal)); + assertTrue(parallelHelper.isEndOfParallelInstructionGroup(aslTerminal)); + + //verify that asking for overrides has no effect on the pcode + PcodeOp[] asl_unmod = aslTerminal.getPcode(); + assertTrue(PcodeEmitContextTest.equalPcodeOpArrays(asl_unmod, aslTerminal.getPcode(false))); + assertTrue(PcodeEmitContextTest.equalPcodeOpArrays(asl_unmod, aslTerminal.getPcode(true))); + + //apply a fallthrough override + int id = program.startTransaction("test"); + aslTerminal.setFallThrough(aslTerminal.getAddress().add(8)); + program.endTransaction(id, true); + + //verify that pcode is unchanged if you request no overrides + assertTrue(PcodeEmitContextTest.equalPcodeOpArrays(asl_unmod, aslTerminal.getPcode())); + assertTrue(PcodeEmitContextTest.equalPcodeOpArrays(asl_unmod, aslTerminal.getPcode(false))); + + //verify that if you request override a BRANCH op is appended to the pcode for the + //instruction and that there are no other changes + PcodeOp[] asl_mod = aslTerminal.getPcode(true); + assertEquals(asl_unmod.length + 1, asl_mod.length); + for (int i = 0; i < asl_unmod.length; ++i) { + assertTrue(PcodeEmitContextTest.equalPcodeOps(asl_unmod[i], asl_mod[i])); + } + PcodeOp appended = asl_mod[asl_mod.length - 1]; + assertEquals(PcodeOp.BRANCH, appended.getOpcode()); + assertTrue(appended.getInput(0).isAddress()); + assertEquals(aslTerminal.getAddress().add(8).getOffset(), appended.getInput(0).getOffset()); + } + + /** + * Tests that a fallthrough override applied to an instruction in a packet appends + * a branch to the main section and does not change the pcode in a named section. + * + 00100064 00 42 b0 a0 memw_loc (R16,P0),R2 + 00100068 80 40 00 d5 || add:sat R0,R0.L,R0.L + 0010006c c0 c0 01 8e || asl+= R0,R1,#0x0 + 00100070 c0 c0 01 8e asl+= R0,R1,#0x0 + */ + @Test + public void testFallthroughOverrideMidPacket() { + //verify the instructions used in the test + Instruction memw_locked = listing.getInstructionAt(testFallthroughOverrideMidPacketAddr); + assertNotNull(memw_locked); + assertEquals("memw_locked (R16,P0),R2", memw_locked.toString().trim()); + assertFalse(parallelHelper.isParallelInstruction(memw_locked)); + assertFalse(parallelHelper.isEndOfParallelInstructionGroup(memw_locked)); + Instruction addSat = listing.getInstructionAfter(memw_locked.getAddress()); + assertNotNull(addSat); + assertEquals("add:sat R0,R0.L,R0.L", addSat.toString().trim()); + assertTrue(parallelHelper.isParallelInstruction(addSat)); + assertFalse(parallelHelper.isEndOfParallelInstructionGroup(addSat)); + Instruction aslTerminal = listing.getInstructionAfter(addSat.getAddress()); + assertNotNull(aslTerminal); + assertEquals("asl+= R0,R1,#0x0", aslTerminal.toString().trim()); + assertTrue(parallelHelper.isParallelInstruction(aslTerminal)); + assertTrue(parallelHelper.isEndOfParallelInstructionGroup(aslTerminal)); + + //verify that pcode unchanged when asking for overrides to be applied + PcodeOp[] memw_locked_unmod = memw_locked.getPcode(); + assertTrue(PcodeEmitContextTest.equalPcodeOpArrays(memw_locked_unmod, + memw_locked.getPcode(false))); + assertTrue( + PcodeEmitContextTest.equalPcodeOpArrays(memw_locked_unmod, memw_locked.getPcode(true))); + PcodeOp[] addSat_unmod = addSat.getPcode(); + assertTrue(PcodeEmitContextTest.equalPcodeOpArrays(addSat_unmod, addSat.getPcode(false))); + assertTrue(PcodeEmitContextTest.equalPcodeOpArrays(addSat_unmod, addSat.getPcode(true))); + PcodeOp[] aslTerminal_unmod = aslTerminal.getPcode(); + assertTrue(PcodeEmitContextTest.equalPcodeOpArrays(aslTerminal_unmod, + aslTerminal.getPcode(false))); + assertTrue( + PcodeEmitContextTest.equalPcodeOpArrays(aslTerminal_unmod, aslTerminal.getPcode(true))); + + //verify that the pcode for aslTerminal contains an "unlock" pcodeop (crossbuilt from memw_locked) + PcodeOp callother = aslTerminal_unmod[15]; + assertEquals(PcodeOp.CALLOTHER, callother.getOpcode()); + assertEquals("unlock", + language.getUserDefinedOpName((int) callother.getInput(0).getOffset())); + + //apply the fallthrough override + int id = program.startTransaction("test"); + memw_locked.setFallThrough(memw_locked.getAddress().add(12)); + program.endTransaction(id, true); + + //verify that pcode at address of main section is unchanged when overrides are not applied + assertTrue(PcodeEmitContextTest.equalPcodeOpArrays(memw_locked_unmod, + memw_locked.getPcode(false))); + + //verify that the pcode at the address for the main section has a BRANCH appended when + //overrides are applied and is otherwise unchanged + PcodeOp[] memw_locked_mod = memw_locked.getPcode(true); + assertEquals(memw_locked_unmod.length + 1, memw_locked_mod.length); + for (int i = 0; i < memw_locked_unmod.length; ++i) { + assertTrue( + PcodeEmitContextTest.equalPcodeOps(memw_locked_unmod[i], memw_locked_mod[i])); + } + PcodeOp appended = memw_locked_mod[memw_locked_mod.length - 1]; + assertEquals(PcodeOp.BRANCH, appended.getOpcode()); + assertEquals(memw_locked.getAddress().add(12).getOffset(), + appended.getInput(0).getOffset()); + assertTrue(appended.getInput(0).isAddress()); + + //verify that pcode at address where the named section is crossbuilt is unchanged + //whether or not overides are requested + assertTrue( + PcodeEmitContextTest.equalPcodeOpArrays(aslTerminal_unmod, aslTerminal.getPcode())); + assertTrue(PcodeEmitContextTest.equalPcodeOpArrays(aslTerminal_unmod, + aslTerminal.getPcode(false))); + assertTrue( + PcodeEmitContextTest.equalPcodeOpArrays(aslTerminal_unmod, aslTerminal.getPcode(true))); + + } + + /** + * Tests that a BRANCH override applied to a CALL instruction in a singleton + * packet replaes the CALL op with a BRANCH + * + 00100074 c6 c7 00 5a call func1 undefined func1(void) + */ + @Test + public void testFlowOverrideSingletonCall() { + //verify the instructions used in the test + Instruction call = listing.getInstructionAt(testFlowOverrideSingletonCallAddr); + assertNotNull(call); + assertEquals("call 0x00101000", call.toString().trim()); + assertFalse(parallelHelper.isParallelInstruction(call)); + assertTrue(parallelHelper.isEndOfParallelInstructionGroup(call)); + + //verify that the pcode is the same whether or not you request overrides + PcodeOp[] call_unmod = call.getPcode(); + assertTrue(PcodeEmitContextTest.equalPcodeOpArrays(call_unmod, call.getPcode(true))); + assertEquals(7, call_unmod.length); + + //verify the CALL op exists + assertEquals(PcodeOp.CALL, call_unmod[6].getOpcode()); + assertEquals(func1Addr, call_unmod[6].getInput(0).getAddress()); + + //apply the fallthrough override + int id = program.startTransaction("test"); + call.setFlowOverride(FlowOverride.BRANCH); + program.endTransaction(id, true); + + //verify that nothing changes if you ask for no overrides + assertTrue(PcodeEmitContextTest.equalPcodeOpArrays(call_unmod, call.getPcode(false))); + + //verify that the CALL is changed to a BRANCH if you request overrides + //and there are no other changes + PcodeOp[] call_mod = call.getPcode(true); + assertEquals(call_unmod.length, call_mod.length); + for (int i = 0; i < call_mod.length - 1; i++) { + assertTrue(PcodeEmitContextTest.equalPcodeOps(call_unmod[i], call_mod[i])); + } + PcodeOp overridden = call_mod[6]; + assertTrue(PcodeEmitContextTest.equalInputsAndOutput(overridden, call_unmod[6])); + assertEquals(PcodeOp.BRANCH, overridden.getOpcode()); + } + + /** + * Tests that to override the flow of a CALL instruction in a packet the flow override + * must be placed on the instruction where the CALL op is crossbuilt (which is not the "call" + * instruction in this example). + * + 00100078 c4 47 00 5a call func1 + 0010007c c0 c0 01 8e || asl+= R0,R1,#0x0 undefined func1(void) + */ + @Test + public void testFlowOverrideCallInPacket() { + //verify the instructions used in the test + Instruction call = listing.getInstructionAt(testFlowOverrideCallInPacketAddr); + assertNotNull(call); + assertEquals("call 0x00101000", call.toString().trim()); + assertFalse(parallelHelper.isParallelInstruction(call)); + assertFalse(parallelHelper.isEndOfParallelInstructionGroup(call)); + Instruction asl_plus = listing.getInstructionAfter(call.getAddress()); + assertNotNull(asl_plus); + assertEquals("asl+= R0,R1,#0x0", asl_plus.toString().trim()); + assertTrue(parallelHelper.isParallelInstruction(asl_plus)); + assertTrue(parallelHelper.isEndOfParallelInstructionGroup(asl_plus)); + + PcodeOp[] call_unmod = call.getPcode(); + PcodeOp[] asl_plus_unmod = asl_plus.getPcode(); + + //verify that there are no changes if you ask for overrides + assertTrue(PcodeEmitContextTest.equalPcodeOpArrays(call_unmod, call.getPcode(true))); + assertTrue( + PcodeEmitContextTest.equalPcodeOpArrays(asl_plus_unmod, asl_plus.getPcode(true))); + + //apply a BRANCH override at the address of the call instruction. This should have + //no effect on the pcode, since the CALL op is in a named section and will be crossbuilt + //into the pcode of the next instruction + //(note that the associated action would be disabled in the gui for the call instruction) + int id = program.startTransaction("test"); + call.setFlowOverride(FlowOverride.BRANCH); + program.endTransaction(id, true); + + // verify no changes whether or not you ask for overrides + assertTrue(PcodeEmitContextTest.equalPcodeOpArrays(call_unmod, call.getPcode(false))); + assertTrue( + PcodeEmitContextTest.equalPcodeOpArrays(asl_plus_unmod, asl_plus.getPcode(false))); + assertTrue(PcodeEmitContextTest.equalPcodeOpArrays(call_unmod, call.getPcode(true))); + assertTrue( + PcodeEmitContextTest.equalPcodeOpArrays(asl_plus_unmod, asl_plus.getPcode(true))); + + //apply a BRANCH override at the address of the asl instruction. + id = program.startTransaction("test"); + asl_plus.setFlowOverride(FlowOverride.BRANCH); + program.endTransaction(id, true); + + // verify no changes if you don't ask for overrides + assertTrue(PcodeEmitContextTest.equalPcodeOpArrays(call_unmod, call.getPcode(false))); + assertTrue( + PcodeEmitContextTest.equalPcodeOpArrays(asl_plus_unmod, asl_plus.getPcode(false))); + + //pcode for call instruction should not change if you ask for overrides + assertTrue(PcodeEmitContextTest.equalPcodeOpArrays(call_unmod, call.getPcode(true))); + + //verify that the CALL instruction becomes a BRANCH when overrides are requested + //and that there are no other changes + PcodeOp[] asl_plus_mod = asl_plus.getPcode(true); + assertEquals(asl_plus_unmod.length, asl_plus_mod.length); + for (int i = 0; i < asl_plus_unmod.length; ++i) { + PcodeOp mod = asl_plus_mod[i]; + PcodeOp unmod = asl_plus_unmod[i]; + if (i < (asl_plus_unmod.length - 1)) { + assertTrue(PcodeEmitContextTest.equalPcodeOps(unmod, mod)); + } + else { + assertTrue(PcodeEmitContextTest.equalInputsAndOutput(unmod, mod)); + assertEquals(PcodeOp.CALL, unmod.getOpcode()); + assertEquals(PcodeOp.BRANCH, mod.getOpcode()); + } + } + } + + /** + * Tests that to override the destination of a CALL instruction in a packet a simple reference + * must be placed on the instruction where the CALL op is crossbuilt (which is not the "call" + * instruction in this example). + 00100078 c4 47 00 5a call func1 + 0010007c c0 c0 01 8e || asl+= R0,R1,#0x0 undefined func1(void) + */ + @Test + public void testSimpleCallReferenceOverride() { + //verify the instructions used in the test + Instruction call = listing.getInstructionAt(testFlowOverrideCallInPacketAddr); + assertNotNull(call); + assertEquals("call 0x00101000", call.toString().trim()); + assertFalse(parallelHelper.isParallelInstruction(call)); + assertFalse(parallelHelper.isEndOfParallelInstructionGroup(call)); + Instruction asl_plus = listing.getInstructionAfter(call.getAddress()); + assertNotNull(asl_plus); + assertEquals("asl+= R0,R1,#0x0", asl_plus.toString().trim()); + assertTrue(parallelHelper.isParallelInstruction(asl_plus)); + assertTrue(parallelHelper.isEndOfParallelInstructionGroup(asl_plus)); + + PcodeOp[] call_unmod = call.getPcode(); + PcodeOp[] asl_plus_unmod = asl_plus.getPcode(); + + //verify that there are no changes if you ask for overrides + assertTrue(PcodeEmitContextTest.equalPcodeOpArrays(call_unmod, call.getPcode(true))); + assertTrue( + PcodeEmitContextTest.equalPcodeOpArrays(asl_plus_unmod, asl_plus.getPcode(true))); + + //apply a simple overriding reference at the address of the call instruction + //verify that it has no effect on the Pcode, since the CALL op is crossbuilt to + //a different address + int id = program.startTransaction("test"); + Reference simpleCallRef = refManager.addMemoryReference(call.getAddress(), func2Addr, + RefType.UNCONDITIONAL_CALL, SourceType.USER_DEFINED, -1); + //any default reference is primary, so need to set simpleCallRef to primary to unseat it + refManager.setPrimary(simpleCallRef, true); + program.endTransaction(id, true); + + // verify no changes whether or not you ask for overrides + assertTrue(PcodeEmitContextTest.equalPcodeOpArrays(call_unmod, call.getPcode(false))); + assertTrue( + PcodeEmitContextTest.equalPcodeOpArrays(asl_plus_unmod, asl_plus.getPcode(false))); + assertTrue(PcodeEmitContextTest.equalPcodeOpArrays(call_unmod, call.getPcode(true))); + assertTrue( + PcodeEmitContextTest.equalPcodeOpArrays(asl_plus_unmod, asl_plus.getPcode(true))); + + id = program.startTransaction("test"); + simpleCallRef = refManager.addMemoryReference(asl_plus.getAddress(), func2Addr, + RefType.UNCONDITIONAL_CALL, SourceType.USER_DEFINED, -1); + //any default reference is primary, so need to set simpleCallRef to primary to unseat it + refManager.setPrimary(simpleCallRef, true); + program.endTransaction(id, true); + + // verify no changes if you don't ask for overrides + assertTrue(PcodeEmitContextTest.equalPcodeOpArrays(call_unmod, call.getPcode(false))); + assertTrue( + PcodeEmitContextTest.equalPcodeOpArrays(asl_plus_unmod, asl_plus.getPcode(false))); + + //pcode for call instruction should not change if you ask for overrides + assertTrue(PcodeEmitContextTest.equalPcodeOpArrays(call_unmod, call.getPcode(true))); + + //verify that the CALL target changes if overrides are requested + //and that there are no other changes + PcodeOp[] asl_plus_mod = asl_plus.getPcode(true); + assertEquals(asl_plus_unmod.length, asl_plus_mod.length); + for (int i = 0; i < asl_plus_unmod.length; ++i) { + PcodeOp mod = asl_plus_mod[i]; + PcodeOp unmod = asl_plus_unmod[i]; + if (i < (asl_plus_unmod.length - 1)) { + assertTrue(PcodeEmitContextTest.equalPcodeOps(unmod, mod)); + } + else { + assertEquals(PcodeOp.CALL, unmod.getOpcode()); + assertEquals(PcodeOp.CALL, mod.getOpcode()); + assertEquals(func1Addr, unmod.getInput(0).getAddress()); + assertEquals(func2Addr, mod.getInput(0).getAddress()); + } + } + } +}