Files
ghidra/Ghidra/Processors/Hexagon/data/languages/hexagon.cspec
2026-03-23 15:30:23 -04:00

154 lines
4.2 KiB
XML
Executable File

<?xml version="1.0" encoding="UTF-8"?>
<compiler_spec>
<data_organization>
<absolute_max_alignment value="0" />
<machine_alignment value="8" />
<default_alignment value="1" />
<default_pointer_alignment value="4" />
<char_type signed="false" />
<pointer_size value="4" />
<wchar_size value="4" />
<short_size value="2" />
<integer_size value="4" />
<long_size value="4" />
<long_long_size value="8" />
<float_size value="4" />
<double_size value="8" />
<long_double_size value="8" />
<size_alignment_map>
<entry size="1" alignment="1" />
<entry size="2" alignment="2" />
<entry size="4" alignment="4" />
<entry size="8" alignment="8" />
</size_alignment_map>
</data_organization>
<global>
<range space="ram"/>
<range space="register" first="0x800" last="0x8ff" /> <!-- Registers: S0-S63 -->
</global>
<stackpointer register="SP" space="ram"/>
<prefersplit style="inhalf">
<register name="R1R0_"/>
<register name="R1R0"/>
<register name="R3R2_"/>
<register name="R3R2"/>
<register name="R5R4_"/>
<register name="R5R4"/>
<register name="R7R6_"/>
<register name="R7R6"/>
<register name="R9R8_"/>
<register name="R9R8"/>
<register name="R11R10_"/>
<register name="R11R10"/>
<register name="R13R12_"/>
<register name="R13R12"/>
<register name="R15R14_"/>
<register name="R15R14"/>
<register name="R17R16_"/>
<register name="R17R16"/>
<register name="R19R18_"/>
<register name="R19R18"/>
<register name="R21R20_"/>
<register name="R21R20"/>
<register name="R23R22_"/>
<register name="R23R22"/>
<register name="R25R24_"/>
<register name="R25R24"/>
</prefersplit>
<default_proto>
<prototype name="__stdcall" extrapop="0" stackshift="0">
<input>
<pentry minsize="1" maxsize="4">
<register name="R0"/>
</pentry>
<pentry minsize="1" maxsize="4">
<register name="R1"/>
</pentry>
<pentry minsize="5" maxsize="8">
<register name="R1R0"/>
</pentry>
<pentry minsize="1" maxsize="4">
<register name="R2"/>
</pentry>
<pentry minsize="1" maxsize="4">
<register name="R3"/>
</pentry>
<pentry minsize="5" maxsize="8">
<register name="R3R2"/>
</pentry>
<pentry minsize="1" maxsize="4">
<register name="R4"/>
</pentry>
<pentry minsize="1" maxsize="4">
<register name="R5"/>
</pentry>
<pentry minsize="5" maxsize="8">
<register name="R5R4"/>
</pentry>
<pentry minsize="1" maxsize="500" align="1"> <!-- unable to stipulate alignment properly - see ABI spec -->
<addr offset="0" space="stack"/>
</pentry>
</input>
<output>
<pentry minsize="1" maxsize="8">
<register name="R1R0"/>
</pentry>
</output>
<unaffected>
<register name="R16"/>
<register name="R17"/>
<register name="R18"/>
<register name="R19"/>
<register name="R20"/>
<register name="R21"/>
<register name="R22"/>
<register name="R23"/>
<register name="R24"/>
<register name="R25"/>
<register name="R26"/>
<register name="R27"/>
<register name="SP"/>
<register name="FP"/>
<register name="LC0"/>
<register name="LC1"/>
<register name="SA0"/>
<register name="SA1"/>
<register name="P3P0"/>
<register name="M0"/>
<register name="M1"/>
<register name="GP"/>
<register name="UGP"/>
<register name="FP"/>
</unaffected>
</prototype>
</default_proto>
<!-- Injections for various compiler helper functions -->
<callfixup name="prolog_save_regs">
<pcode><body>
<![CDATA[
ptr:4 = 0; # can't handle empty pcode
]]>
</body></pcode>
</callfixup>
<callfixup name="prolog_restore_regs">
<pcode><body>
<![CDATA[
ptr:4 = FP;
FP = *[ram]:4 ptr;
ptr = ptr + 4;
LR = *[ram]:4 ptr;
SP = ptr + 4;
]]>
</body></pcode>
</callfixup>
</compiler_spec>