mirror of
https://github.com/NationalSecurityAgency/ghidra.git
synced 2026-04-25 17:25:17 +02:00
299 lines
13 KiB
Plaintext
299 lines
13 KiB
Plaintext
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attach variables [ sr ] [
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# 0x...0 0x...4 0x...8 0x...c
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LBEG LEND LCOUNT SAR # 0x0_
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BR LITBASE _ _ # 0x1_
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_ _ _ _ # 0x2_
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SCOMPARE1 _ _ _ # 0x3_
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ACCLO ACCHI _ _ # 0x4_
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_ _ _ _ # 0x5_
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_ _ _ _ # 0x6_
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_ _ _ _ # 0x7_
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M0 M1 M2 M3 # 0x8_
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_ _ _ _ # 0x9_
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_ _ _ _ # 0xa_
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_ _ _ _ # 0xb_
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_ _ _ _ # 0xc_
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_ _ _ _ # 0xd_
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_ _ _ _ # 0xe_
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_ _ _ _ # 0xf_
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# 0x...0 0x...4 0x...8 0x...c
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_ _ _ _ # 0x10_
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_ _ _ _ # 0x11_
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WindowBase WindowStart _ _ # 0x12_
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_ _ _ _ # 0x13_
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_ _ _ PTEVADDR # 0x14_
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_ _ _ _ # 0x15_
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_ MMID RASID ITLBCFG # 0x16_
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DTLBCFG _ _ _ # 0x17_
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IBREAKENABLE MEMCTL CACHEATTR ATOMCTL # 0x18_
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_ _ _ _ # 0x19_
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DDR _ MEPC MEPS # 0x1a_
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MESAVE MESR MECR MEVADDR # 0x1b_
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_ _ _ _ # 0x1c_
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_ _ _ _ # 0x1d_
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_ _ _ _ # 0x1e_
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_ _ _ _ # 0x1f_
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# 0x...0 0x...4 0x...8 0x...c
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IBREAKA0 IBREAKA1 _ _ # 0x20_
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_ _ _ _ # 0x21_
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_ _ _ _ # 0x22_
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_ _ _ _ # 0x23_
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DBREAKA0 DBREAKA1 _ _ # 0x24_
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_ _ _ _ # 0x25_
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_ _ _ _ # 0x26_
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_ _ _ _ # 0x27_
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DBREAKC0 DBREAKC1 _ _ # 0x28_
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_ _ _ _ # 0x29_
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_ _ _ _ # 0x2a_
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_ _ _ _ # 0x2b_
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_ EPC1 EPC2 EPC3 # 0x2c_
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EPC4 EPC5 EPC6 EPC7 # 0x2d_
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_ _ _ _ # 0x2e_
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_ _ _ _ # 0x2f_
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# 0x...0 0x...4 0x...8 0x...c
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DEPC _ EPS2 EPS3 # 0x30_
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EPS4 EPS5 EPS6 EPS7 # 0x31_
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_ _ _ _ # 0x32_
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_ _ _ _ # 0x33_
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_ EXCSAVE1 EXCSAVE2 EXCSAVE3 # 0x34_
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EXCSAVE4 EXCSAVE5 EXCSAVE6 EXCSAVE7 # 0x35_
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_ _ _ _ # 0x36_
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_ _ _ _ # 0x37_
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CPENABLE INTERRUPT INTSET INTCLEAR # 0x38_
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INTENABLE _ PS VECBASE # 0x39_
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EXCCAUSE DEBUGCAUSE CCOUNT PRID # 0x3a_
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ICOUNT ICOUNTLEVEL EXCVADDR _ # 0x3b_
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CCOMPARE0 CCOMPARE1 CCOMPARE2 _ # 0x3c_
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MISC0 MISC1 MISC2 MISC3 # 0x3d_
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_ _ _ _ # 0x3e_
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_ _ _ _ # 0x3f_
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# 0x...0 0x...4 0x...8 0x...c
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];
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attach variables [ ar as at n_ar n_as n_at ] [
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a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15
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];
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attach variables [ fr fs ft ] [
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f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 f12 f13 f14 f15
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];
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attach variables [ br bs bt ] [
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b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 b14 b15
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];
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# Various 32-bit pointers relative to PC. Any operands that are split across non-consecutive
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# bits are named foo_LL.LM_ML.MM, where LL is the least significant bits of the least
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# singificant operand half, LM the most significant bits of the least significant operand half, etc.
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attach variables [ mw ] [
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M0 M1 M2 M3
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];
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attach variables [ my ] [
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M2 M3
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];
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attach variables [ mx ] [
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M0 M1
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];
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#implemented pcodeops
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define pcodeop breakpoint;
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define pcodeop dhi;
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define pcodeop dhu;
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define pcodeop dhwb;
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define pcodeop dhwbi;
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define pcodeop dii;
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define pcodeop diu;
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define pcodeop diwb;
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define pcodeop diwbi;
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define pcodeop dpfl;
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define pcodeop dpfr;
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define pcodeop dpfro;
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define pcodeop dpfw;
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define pcodeop dpfwo;
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define pcodeop dsync;
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define pcodeop esync;
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define pcodeop excw;
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define pcodeop extw;
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define pcodeop idtlb;
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define pcodeop ihi;
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define pcodeop ihu;
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define pcodeop iii;
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define pcodeop iitlb;
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define pcodeop iiu;
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define pcodeop ill;
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define pcodeop ipf;
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define pcodeop ipfl;
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define pcodeop isync;
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define pcodeop acquire;
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define pcodeop ldct;
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define pcodeop lict;
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define pcodeop licw;
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define pcodeop memw;
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define pcodeop nsa;
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define pcodeop nsau;
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define pcodeop pdtlb;
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define pcodeop pitlb;
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define pcodeop rdtlb0;
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define pcodeop rdtlb1;
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define pcodeop rer;
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define pcodeop restore4;
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define pcodeop restore8;
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define pcodeop restore12;
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define pcodeop rfdd;
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define pcodeop rfde;
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define pcodeop rfdo;
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define pcodeop rfe;
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define pcodeop rfi;
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define pcodeop rfme;
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define pcodeop rfue;
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define pcodeop rfwo;
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define pcodeop rfwu;
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define pcodeop ritlb0;
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define pcodeop ritlb1;
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define pcodeop rsil;
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define pcodeop rsr;
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define pcodeop rsync;
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define pcodeop rur;
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define pcodeop s32c1i;
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define pcodeop release;
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define pcodeop restoreRegWindow;
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define pcodeop rotateRegWindow;
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define pcodeop sdct;
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define pcodeop sict;
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define pcodeop sicw;
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define pcodeop simcall;
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define pcodeop syscall;
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define pcodeop swap4;
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define pcodeop swap8;
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define pcodeop swap12;
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define pcodeop waiti;
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define pcodeop wdtlb;
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define pcodeop wer;
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define pcodeop witlb;
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define pcodeop wsr;
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define pcodeop wur;
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define pcodeop xsr;
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# Various 32-bit pointers relative to PC. Any operands that are split across non-consecutive
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# bits are named foo_LL_LM_ML_MM, where LL is the least significant bits of the least
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# singificant operand half, LM the most significant bits of the least significant operand half, etc.
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ri8_srel: rel is ri8_si8 [ rel = inst_start + ri8_si8 + 4; ] { export *:4 rel; }
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bri12_srel: rel is bri12_si12 [ rel = inst_start + bri12_si12 + 4; ] { export *:4 rel; }
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ri6_rel: rel is ri6_i6_4_2 & ri6_i6_0_4 [
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rel = inst_start + ((ri6_i6_4_2 << 4) | ri6_i6_0_4) + 4;
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] { export *:4 rel; }
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call_srel: rel is call_o18 [ rel = inst_start + call_o18 + 4; ] { export *:4 rel; }
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call_srel_sh2: rel is call_o18 [
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rel = (inst_start & ~3) + ( call_o18 << 2 ) + 4;
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] { export *:4 rel; }
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srel_oex_sh2: rel is ri16_i16 [
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rel = ((inst_start + 3) & ~3) + ((ri16_i16 | 0xffff0000) << 2);
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] { export *:4 rel; }
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# Immediates split across the instruction.
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u5_8_11_20: tmp is op2_0 & op_s [ tmp = (op2_0 << 4) | op_s; ] { export *[const]:4 tmp; }
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u5_4_7_20: tmp is op2_0 & op_t [ tmp = 32 - ((op2_0 << 4) | op_t); ] { export *[const]:4 tmp; }
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u5_8_11_16: tmp is op1_0 & op_s [ tmp = (op1_0 << 4) | op_s; ] { export *[const]:4 tmp; }
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u5_4_7_12: tmp is op_r_0 & op_t [ tmp = (op_r_0 << 4) | op_t; ] { export *[const]:4 tmp; }
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u5_8_11_4: tmp is op_t_0 & op_s [ tmp = (op_t_0 << 4) | op_s; ] { export *[const]:4 tmp; }
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# Signed 12-bit (extended to 16) immediate, used by MOVI.
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movi_si16: tmp is op_st_i8 & ri8_i8 [
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tmp = (op_st_i8 << 8) | ri8_i8;
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] { export *[const]:2 tmp; }
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# An “asymmetric” immediate from -32..95, used by MOVI.N.
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movin_si8: tmp is n_op_s_0_3 & ri6_si6_0_4 [
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tmp = ((((n_op_s_0_3 & 7) << 4) | (ri6_si6_0_4 & 15)) |
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((((n_op_s_0_3 >> 2) & 1) & ((n_op_s_0_3 >> 1) & 1)) << 7));
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] { export *[const]:1 tmp; }
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# Immediates shifted or with offset.
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ri8_si8_sh8: tmp is ri8_si8 [ tmp = ri8_si8 << 8; ] { export *[const]:4 tmp; }
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bri12_i12_sh3: tmp is bri12_i12 [ tmp = bri12_i12 << 3; ] { export *[const]:4 tmp; }
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ri8_i8_sh2: tmp is ri8_i8 [ tmp = ri8_i8 << 2; ] { export *[const]:4 tmp; }
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u9_16_23_sb1: tmp is ri8_i8 [ tmp = ri8_i8 << 1; ] { export *[const]:4 tmp; }
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u5_20_23_plus1: tmp is op2 [ tmp = op2 + 1; ] { export *[const]:4 tmp; }
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u8_20_23_sb4: tmp is op2 [ tmp = op2 << 4; ] { export *[const]:4 tmp; }
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u5_4_7_plus7: tmp is op_t [ tmp = op_t + 7; ] { export *[const]:4 tmp; }
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n_u6_12_15_sb2: tmp is ri6_i6_0_4 [ tmp = ri6_i6_0_4 << 2; ] { export *[const]:4 tmp; }
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# One-extended. FIXME: Verify this. Only used by [LS]32E (window extension), which aren’t yet
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# implemented.
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s5_12_15_oex: tmp is op_r [ tmp = (op_r << 2) - 64; ] { export *[const]:2 tmp; }
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# Some 4-bit immediates with mappings that can’t be (easily) expressed in a single disassembly action.
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# n_u4_4_7 with 0 being -1, used by ADDI.N.
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n_s4_4_7_nozero: tmp is n_op_s = 0 [ tmp = -1; ] { export *[const]:4 tmp; }
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n_s4_4_7_nozero: tmp is n_op_s [ tmp = n_op_s+0; ] { export *[const]:4 tmp; }
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# B4CONST(ar) (Branch Immediate) encodings, pg. 41 f.
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r_b4const: tmp is ar = 0 [ tmp = 0xffffffff; ] { export *[const]:4 tmp; }
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r_b4const: tmp is ar = 1 [ tmp = 0x1; ] { export *[const]:4 tmp; }
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r_b4const: tmp is ar = 2 [ tmp = 0x2; ] { export *[const]:4 tmp; }
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r_b4const: tmp is ar = 3 [ tmp = 0x3; ] { export *[const]:4 tmp; }
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r_b4const: tmp is ar = 4 [ tmp = 0x4; ] { export *[const]:4 tmp; }
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r_b4const: tmp is ar = 5 [ tmp = 0x5; ] { export *[const]:4 tmp; }
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r_b4const: tmp is ar = 6 [ tmp = 0x6; ] { export *[const]:4 tmp; }
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r_b4const: tmp is ar = 7 [ tmp = 0x7; ] { export *[const]:4 tmp; }
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r_b4const: tmp is ar = 8 [ tmp = 0x8; ] { export *[const]:4 tmp; }
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r_b4const: tmp is ar = 9 [ tmp = 0xa; ] { export *[const]:4 tmp; }
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r_b4const: tmp is ar = 10 [ tmp = 0xc; ] { export *[const]:4 tmp; }
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r_b4const: tmp is ar = 11 [ tmp = 0x10; ] { export *[const]:4 tmp; }
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r_b4const: tmp is ar = 12 [ tmp = 0x20; ] { export *[const]:4 tmp; }
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r_b4const: tmp is ar = 13 [ tmp = 0x40; ] { export *[const]:4 tmp; }
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r_b4const: tmp is ar = 14 [ tmp = 0x80; ] { export *[const]:4 tmp; }
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r_b4const: tmp is ar = 15 [ tmp = 0x100; ] { export *[const]:4 tmp; }
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# B4CONSTU(ar) (Branch Unsigned Immediate) encodings, pg. 42.
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r_b4constu: tmp is ar = 0 [ tmp = 0x8000; ] { export *[const]:4 tmp; }
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r_b4constu: tmp is ar = 1 [ tmp = 0x1000; ] { export *[const]:4 tmp; }
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r_b4constu: tmp is ar = 2 [ tmp = 0x2; ] { export *[const]:4 tmp; }
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r_b4constu: tmp is ar = 3 [ tmp = 0x3; ] { export *[const]:4 tmp; }
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r_b4constu: tmp is ar = 4 [ tmp = 0x4; ] { export *[const]:4 tmp; }
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r_b4constu: tmp is ar = 5 [ tmp = 0x5; ] { export *[const]:4 tmp; }
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r_b4constu: tmp is ar = 6 [ tmp = 0x6; ] { export *[const]:4 tmp; }
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r_b4constu: tmp is ar = 7 [ tmp = 0x7; ] { export *[const]:4 tmp; }
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r_b4constu: tmp is ar = 8 [ tmp = 0x8; ] { export *[const]:4 tmp; }
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r_b4constu: tmp is ar = 9 [ tmp = 0xa; ] { export *[const]:4 tmp; }
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r_b4constu: tmp is ar = 10 [ tmp = 0xc; ] { export *[const]:4 tmp; }
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r_b4constu: tmp is ar = 11 [ tmp = 0x10; ] { export *[const]:4 tmp; }
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r_b4constu: tmp is ar = 12 [ tmp = 0x20; ] { export *[const]:4 tmp; }
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r_b4constu: tmp is ar = 13 [ tmp = 0x40; ] { export *[const]:4 tmp; }
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r_b4constu: tmp is ar = 14 [ tmp = 0x80; ] { export *[const]:4 tmp; }
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r_b4constu: tmp is ar = 15 [ tmp = 0x100; ] { export *[const]:4 tmp; }
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Ret4: loc is epsilon [loc = ((inst_start + 3) & 0x0fffffff) | 0x40000000; ] { ret:4 = loc; export ret; }
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Ret8: loc is epsilon [loc = ((inst_start + 3) & 0x0fffffff) | 0x80000000; ] { ret:4 = loc; export ret; }
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Ret12: loc is epsilon [loc = ((inst_start + 3) & 0x0fffffff) | 0xc0000000; ] { ret:4 = loc; export ret; }
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:^instruction is phase=0 & loopMode=1 & instruction [ phase=1; ] {
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build instruction;
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if (LCOUNT == 0 || $(PS_EXCM)) goto inst_next;
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LCOUNT = LCOUNT - 1;
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goto [LBEG];
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}
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:^instruction is phase=0 & loopMode=1 & loopEnd=1 & instruction
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[ loopMode=0; phase=1; ] {
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build instruction;
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}
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:^instruction is phase=0 & loopMode=0 & instruction
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[ phase=1; ] {
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build instruction;
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}
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