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368efef620
Teach the DSL and both arch backends to handle memory operands of the form [pb, pc, field_ref], meaning base + index + field_offset. On aarch64, since x21 already caches pb + pc (the instruction pointer), this emits a single `ldr dst, [x21, #offset]` instead of the previous `mov t0, x21` + `ldr dst, [t0, #offset]` two-instruction sequence. On x86_64, this emits `[r14 + r13 + offset]` which is natively supported by x86 addressing modes. Convert all `lea t0, [pb, pc]` + `loadNN tX, [t0, field]` pairs in the DSL to the new single-instruction form, saving one instruction per IC access and other field loads in GetById, PutById, GetLength, GetGlobal, SetGlobal, and CallBuiltin handlers.