mirror of
https://github.com/LadybirdBrowser/ladybird
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51758f3022
Generator::allocate_register used to scan the free pool to find the lowest-numbered register and then Vec::remove it, making every allocation O(n) in the size of the pool. When loading https://x.com/ on my Linux machine, we spent ~800ms in this function alone! This logic only existed to match the C++ register allocation ordering while transitioning from C++ to Rust in the LibJS compiler, so now we can simply get rid of it and make it instant. :^) So drop the "always hand out the lowest-numbered free register" policy and use the pool as a plain LIFO stack. Pushing and popping the back of the Vec are both O(1), and peak register usage is unchanged since the policy only affects which specific register gets reused, not how aggressively.
52 lines
1.3 KiB
Plaintext
52 lines
1.3 KiB
Plaintext
$69cce752 async-await.js:9:1
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Registers: 7
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Blocks: 1
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Constants:
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[0] = Undefined
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block0:
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[ 0] GetGlobal dst:reg6, `f`
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[ 18] Call dst:reg5, callee:reg6, this_value:Undefined, f
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[ 38] End value:reg5
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f$c9505126 async-await.js:7:5
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Registers: 10
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Blocks: 8
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Constants:
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[0] = Undefined
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[1] = Int32(42)
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[2] = Int32(1)
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block0:
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[ 0] Yield continuation_label:block1, value:Undefined
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block1:
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[ 10] GetGlobal dst:reg6, `Promise`
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[ 28] GetById dst:reg7, base:reg6, `resolve` (Promise.resolve)
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[ 48] Call dst:reg5, callee:reg7, this_value:reg6, Promise.resolve, arguments:[Int32(42)]
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[ 70] Mov dst:reg7, src:reg0
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[ 80] Await continuation_label:block2, argument:reg5
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block2:
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[ 90] Mov dst:reg7, src:reg0
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[ a0] GetCompletionFields type_dst:reg6, value_dst:reg8, completion:reg7
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[ b0] JumpStrictlyEquals lhs:reg6, rhs:Int32(1), true_target:block3, false_target:block4
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block3:
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[ c8] Await continuation_label:block5, argument:reg8
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block4:
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[ d8] Throw src:reg8
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block5:
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[ e0] Mov dst:reg5, src:reg0
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[ f0] GetCompletionFields type_dst:reg7, value_dst:reg6, completion:reg5
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[ 100] JumpStrictlyEquals lhs:reg7, rhs:Int32(1), true_target:block6, false_target:block7
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block6:
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[ 118] Yield value:reg6
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block7:
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[ 128] Throw src:reg6
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