mirror of
https://github.com/LadybirdBrowser/ladybird
synced 2026-04-30 11:37:16 +02:00
3a08f7b95f
Teach the Rust bytecode generator to treat the synthetic entry GetLexicalEnvironment as a removable prologue load. We still model reg4 as the saved entry lexical environment during codegen, but assemble() now deletes that load when no emitted instruction refers to the saved environment register. This keeps the semantics of unwinding and environment restoration intact while letting empty functions and other simple bodies start at their first real instruction.
48 lines
1.4 KiB
Plaintext
48 lines
1.4 KiB
Plaintext
$6ef6ff9a parameter-createvariable-order.js:7:1
|
|
Registers: 7
|
|
Blocks: 1
|
|
Constants:
|
|
[0] = Undefined
|
|
[1] = Int32(1)
|
|
[2] = Int32(2)
|
|
[3] = Int32(3)
|
|
|
|
block0:
|
|
[ 0] GetGlobal dst:reg6, `f`
|
|
[ 18] Call dst:reg5, callee:reg6, this_value:Undefined, f, arguments:[Int32(1), Int32(2), Int32(3)]
|
|
[ 48] End value:reg5
|
|
|
|
|
|
f$40c96172 parameter-createvariable-order.js:2:5
|
|
Registers: 7
|
|
Blocks: 1
|
|
Locals: inner~0
|
|
Constants:
|
|
[0] = Undefined
|
|
|
|
block0:
|
|
[ 0] CreateVariable `a`, is_immutable:false, is_global:false, is_strict:false
|
|
[ 10] CreateVariable `b`, is_immutable:false, is_global:false, is_strict:false
|
|
[ 20] CreateVariable `c`, is_immutable:false, is_global:false, is_strict:false
|
|
[ 30] InitializeLexicalBinding `a`, src:arg0
|
|
[ 48] InitializeLexicalBinding `b`, src:arg1
|
|
[ 60] InitializeLexicalBinding `c`, src:arg2
|
|
[ 78] Mov dst:inner~0, src:Undefined
|
|
[ 88] NewFunction dst:reg5, shared_function_data_index:0 (inner)
|
|
[ a0] Mov2 dst1:inner~0, src1:reg5, dst2:reg6, src2:inner~0
|
|
[ b8] Call dst:reg5, callee:reg6, this_value:Undefined, inner
|
|
[ d8] Return value:reg5
|
|
|
|
|
|
inner$350d7dbe parameter-createvariable-order.js:3:9
|
|
Registers: 8
|
|
Blocks: 1
|
|
|
|
block0:
|
|
[ 0] GetBinding dst:reg5, `a`
|
|
[ 18] GetBinding dst:reg6, `b`
|
|
[ 30] Add dst:reg7, lhs:reg5, rhs:reg6
|
|
[ 40] GetBinding dst:reg5, `c`
|
|
[ 58] Add dst:reg6, lhs:reg7, rhs:reg5
|
|
[ 68] Return value:reg6
|