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ladybird/Libraries/LibJS/AsmIntGen
Andreas Kling 8936cda523 AsmIntGen: Cache pb+pc in callee-saved x21 on aarch64
Pin x21 = pb + pc (the instruction pointer) as a callee-saved register
that survives C++ calls. x21 is set during dispatch and remains valid
throughout the entire handler.

This eliminates redundant `add x9, x26, x25` instructions from every
load_operand, store_operand, load_label, and dispatch_next sequence.
Also optimizes `lea dst, [pb, pc]` to `mov dst, x21`.

For dispatch_next, the next opcode is loaded via `ldrb w9, [x21, #size]`
and x21 is updated incrementally (`add x21, x21, #size`), which also
improves the dependency chain vs recomputing from x26 + x25.

dispatch_current is promoted from a DSL macro to a codegen instruction
so it can set x21 for the next handler.
2026-03-07 22:18:22 +01:00
..